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Transcript of Mr.R.benschwartz Technology Related Issues in Manufacturing
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R.BENSCHWARTZ
Teaching FacultyCEG Anna University
MOS FABRICATION TECHNOLOGY
RELATED ISSUES IN VLSI
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Introduction
FDP_VLSI_ANNA UNIV2
Integrated circuits: many transistors on one chip. Very Large Scale Integration(VLSI): bucketloads!
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors Today: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication Rest of the course: How to build a good CMOS chip
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VLSI Design Flow
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ENTITY test isport a: in bit;end ENTITY test;
DRCLVSERC
Circuit Design
Functional Design
and Logic Design
Physical Design
Physical Verification
and Signoff
Fabrication
System Specification
Architectural Design
Chip
Packaging and Testing
Chip Planning
Placement
Signal Routing
Partitioning
Timing Closure
Clock Tree Synthesis
2
011SpringerVerlag
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Description of an IC
FDP_VLSI_ANNA UNIV4
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Why do I care how transistors are
made?"
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If designers understand the physical process, they will comprehend the reasonfor the underlying design rules and in turn use this knowledge to create a betterdesign.
Understanding the manufacturing steps is also important when debugging somedifficult chip failures and improving yield
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FDP_VLSI_ANNA UNIV6
Silicon is a group IV element (4 valence electrons) Forms covalent bonds with four neighbor atoms (3D cubic
crystal lattice) Si is a poor conductor, but conduction characteristics may be
altered Add impurities/dopants (replaces silicon atom in lattice):
Makes a better conductor GroupV element (phosphorus/arsenic) => 5 valence electrons
Leaves an electron free => n-type semiconductor (electrons, negative
carriers) Group III element (boron) => 3 valence electrons
Borrows an electron from neighbor => p-type semiconductor (holes, positivecarriers)
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Dopants
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Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
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Moores Law: Then
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1965: Gordon Moore plotted transistor on each chip Fit straight line on semi log scale
Transistor counts have doubled every 24 months
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
[Moore65]
Electronics Magazine
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Feature Size
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Minimum feature size shrinking 30% every 2-3 years
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Corollaries
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Many other factors grow exponentially Ex: clock frequency, processor performance
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Levels of inter connection
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FAB- Outline
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Silicon Wafer Creation
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The Silicon valence of 4 means that it can form a crystalline structure This crystalline structure can be grown
We start with a Seed, which is a small piece of pure, crystalline Silicon
We then melt raw, impure Silicon into a crucible(aka, Silica)
We dip the Seed into the molten Silicon and pull it out slowly while turning-
As the molten Silicon cools, it forms covalent bonds with the Seed-these bonds track the crystal
structure of the Seed, forming more Silicon crystal As the Silicon is pulled out, it forms a long cylinder-this cylinder is called an Ingot-
The ingot is a long cylinder of pure, crystal, Silicon
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Silicon Wafers-
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The seed withdrawal and rotation rates determine the diameterof the ingot.
Growth rates vary from 30 to 180 mm/hour.
The wafers are generally available in diameters of 150 mm, 200 mm, or 300
mm, and are mirror-polished and rinsed before shipment from the wafer
manufacturer.
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Photolithography-
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The patterning is achieved by a process called photolithography, from the Greekphoto (light), lithos (stone), and graphe (picture), which literally means"carving pictures in stone using light."
This is the process of creating patterns on a smooth surface, in our case a Siliconwafer-
This is accomplished by selectively exposing parts of the wafer while otherparts are protected-
The exposed sections are susceptible to doping, removal, or metallization
Specific patterns can be created to form regions of conductors, insulators, ordoping
Putting these patterns onto a wafer is called Photolithography-
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Photoresist
FDP_VLSI_ANNA UNIV16
A material that is acid resistant under normal conditions-
To begin with, it is insoluble to acids
When exposed to UV light, the material becomes soluble to acids
We can put photoresist on a wafer and then selectively expose regions to UV
Then we can soak the entire thing in acid and only the parts of the photoresist
that were exposed to UV light will be removed
This allows us to form a protective barrier on certain parts of the wafer while
exposing others parts
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Types of Photoresists (PR):
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Positive: PR pattern is same as mask. On exposure to light, light degrades the polymers (described
in more detail later) resulting in the photoresist being more soluble in developers. The PRcan be removed in inexpensive solvents such as acetone.
Negative: PR pattern is the inverse of the mask. On exposure to light, light polymerizes the rubbers
in the photoresist to strengthen itsresistance to dissolution in the developer. The resist
has to be removed in special stripping chemicals. These resists tend to be extremelymoisture sensitive.
Combination: Same photoresist can be used for both negative and positive pattern transfer. Can be
removed in inexpensivesolvents.
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Mask
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Masks-a mask in an opaque plate (i.e., not transparent) with holes/shapes thatallow UV light to pass-this is kind of like an overhead transparency
The mask contains the pattern that we wish to form on the target wafer
We pass UV light through the Mask and create soluble patterns in thephotoresist
Each pattern we wish to create requires unique mask-the physical glass platethat is used during fabrication is called a Reticle
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Photolithography Systems
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Contact:Resist is in contact with the mask: 1:1 magnification
Advantages:
Inexpensive equipment ($~50,000-150,000), moderately high resolution (~0.5 um orbetter but limited by resist thickness- 0.1 um demonstrated)
Disadvantages:
Contact with the mask degrades the mask (pinholes and scratches are created on the metal-oxide layers of the mask, particles or dirt are directly imaged in the wafer, Wafer bowing orlocal loss of planarization results in non uniform resolution due to mask-wafer gapvariations., and no magnification
Proximity: Resist is almost, but not in contact with the mask: 1:1 magnification
Advantages:
Inexpensive equipment, low resolution (~1-2 um or slightly better)
Disadvantages:
Diffraction effects limit accuracy of pattern transfer. Less repeatable than contact methods,no magnification
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Photolithography Systems
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Projection: Mask image is projected a distance from the mask and de-magnified to asmaller image: 1:4 -1:10 magnification
Advantages:
Can be very high resolution (~0.065 um or slightly better), No mask contactresults in almost no mask wear (high production compatible), mask defects orparticles on mask are reduced in size on the wafer.
Disadvantages:
Extremely expensive and complicated equipment, diffraction effects limitaccuracy of pattern transfer.
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Issues with Photolithography
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Resolution:
How small of features can you make.
Registration:
Can you repeatability align one layer to another.
Throughput:
Can these be done in a cost effective time. (50-100 wafers an hour, down to
1 chip perhour).
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Etching
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When talking about etching, we typically talk about the etch patterns that can be formed Isotropic-
Etches equally in all direction-wet etch is isotropic-this etch leads toundercutting
Anisotropic
The etch rate is dependant on the direction of the etch-dry etch is anisotropic Wet or dry etching
Used to remove unwanted metal. Pirhana solution is a 3:1 to 5:1 mix of sulphuricacid and hydrogen peroxide that is used to clean wafers of organic and metalcontaminants or photoresist after metal patterning.
Plasma etching Dry etch process with fluorine or chlorine gas used for metallization steps. The
plasma charges the etch gas ions, which are attracted to the appropriately chargedsilicon surface. Very sharp etch profiles can be achieved using plasma etching.
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Ion Implantation:-
FDP_VLSI_ANNA UNIV23
The process of adding impurities to a silicon wafer Wafer is put in a chamber with an Ion source (i.e., B, P, As)
Ions are accelerated toward the wafer using an E-field
Ions collide with the wafer, tunneling into the crystal structure
Photolithography allows us to selectively implant the regions we want (i.e., N-wells, Sources, Drains)
As the impurities crash into the crystal, they damage or break the covalentbonds-
We can repair these bonds using a process called annealing, which heats the
material up and then slowly cools it down allowing the new bonds to form
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Deposition
FDP_VLSI_ANNA UNIV24
Process of addingmaterial to the wafer (as opposed to growing, whichconsumes part of the target)- This is how we put down the polysilicon layer for the gate contact (in
addition to insulators and metal) Polysilicon is a polycrystalline material (SiH4) which is a conductor Polysilicon originally starts with a high resistivity, but when doped its
resistively comes down The most common type of deposition is Chemical Vapor Deposition
(CVD)Chemical Vapor Deposition
Wafer is put into a chamber with a gas (i.e., Si and H2) The gas then forms a chemical reaction with the Silicon dioxide (SiO2)
and Silicon to form a bond, the polysilicon is then added via chemicalreactions.-
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nMOS Transistor
FDP_VLSI_ANNA UNIV25
Four terminals: gate, source, drain, body Gateoxidebody stack looks like a capacitor
Gate and body are conductors
SiO2(oxide) is a very good insulator
Called metaloxidesemiconductor (MOS) capacitor Even though gate is
no longer made of metal
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+Body
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nMOS Operation
FDP_VLSI_ANNA UNIV26
Body is usually tied to ground (0 V) When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
0
S
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nMOS Operation Cont.
FDP_VLSI_ANNA UNIV27
When the gate is at a high voltage: Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from sourcethrough channel to drain, transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
1
S
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pMOS Transistor
FDP_VLSI_ANNA UNIV28
Similar, but doping and voltages reversed Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
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Inverter Cross-section
FDP_VLSI_ANNA UNIV29
Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
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Well and Substrate Taps
FDP_VLSI_ANNA UNIV30
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection called Shottky
Diode
Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
YGND V
DD
n+p+
substrate tapwell
tap
n+ p+
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Inverter Mask Set
FDP_VLSI_ANNA UNIV31
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
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Detailed Mask Views
FDP_VLSI_ANNA UNIV32
Six masks n-well
Polysilicon
n+ diffusion
p+ diffusion Contact
Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
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CMOS technologies
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Four dominant CMOS technologies N-well process
P-well process
Twin-tub process
Silicon on insulator (SOI)
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Fabrication
FDP_VLSI_ANNA UNIV34
Chips are built in huge factories called fabs
Contain clean rooms as large as football fields
The RCA clean is a standard set of wafer cleaning steps which need to be
performed before high-temperature processing steps (oxidation, diffusion, CVD)
of silicon wafers in semiconductor manufacturing.
Werner Kern developed the basic procedure in 1965 while working for RCA,
the Radio Corporation of America. It involves the following :
Removal of the organic contaminants (Organic Clean)
Removal of thin oxide layer (Oxide Strip)
Removal of ionic contamination (Ionic Clean)
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Fabrication Steps
FDP_VLSI_ANNA UNIV35
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2(oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
p substrate
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Oxidation
FDP_VLSI_ANNA UNIV36
Grow Forming silicon dioxide (SiO2) on top of Si wafer
9001200 C with H2O or O2in oxidation furnace
Two common approaches to oxidation of silicon:
Wet oxidation: when the oxidizing atmosphere contains wafer vapor. The temperature is usually
between 900 oC and 1000 oC. This is a rapid process.
Dry oxidation: when the oxidizing atmosphere is pure oxygen. Temperatures are in the region of
1200 oC to achieve an acceptable growth rate.
Atomic layer deposition (ALD)a process in which a thin chemical layer (material A) is
attached to a surface and then a chemical (material B) is introduced to produce a thin layer of the
required layer The process is then repeated and the required layer is built up layer by layer.
p substrate
SiO2
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Photoresist
FDP_VLSI_ANNA UNIV37
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
p substrate
SiO2
Photoresist
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Lithography
FDP_VLSI_ANNA UNIV38
One of the most critical problems in CMOS fabrication is the technique used to create apattern
The photolithographic process starts with the desired pattern definition for the layer.
Expose photoresist through n-well mask
Strip off exposed photoresist
The process for transferring the mask pattern to the surface of a silicon region Coat photoresist
Exposure step
Etching
p substrate
SiO2
Photoresist
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Etch
FDP_VLSI_ANNA UNIV39
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist
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Strip Photoresist
FDP_VLSI_ANNA UNIV40
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step
p substrate
SiO2
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n-well
FDP_VLSI_ANNA UNIV41
n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
n well
SiO2
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Strip Oxide
FDP_VLSI_ANNA UNIV42
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
p substrate
n well
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Polysilicon
FDP_VLSI_ANNA UNIV43
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Thin gate oxidePolysilicon
p substraten well
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Polysilicon Patterning
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Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxidePolysilicon
n well
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Self-Aligned Process
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Use oxide and masking to expose where n+ dopants shouldbe diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact
p substraten well
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N-diffusion
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Pattern oxide and form n+ regions
Self-aligned processwhere gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it doesnt melt
during later processing
p substraten well
n+ Diffusion
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N-diffusion cont.
FDP_VLSI_ANNA UNIV47
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n wellp substrate
n+n+ n+
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N-diffusion cont.
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Strip off oxide to complete patterning step
n wellp substrate
n+n+ n+
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P-Diffusion
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Similar set of steps form p+ diffusion regions for pMOS source and drain andsubstrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
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Contacts
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Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
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Metalization
FDP_VLSI_ANNA UNIV51
Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+
Metal
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Latchup
FDP_VLSI_ANNA UNIV52
Transient currents flowing in substrate during startup can cause VSUB torise, turning on Vsub. This will turn on Vwell, which turns on Vsubharder in a positive feedback loop, causing large current to flowbetween Vdd/GND (destructive current!).
Keep Rwell, Rsub low, also place numerous well taps to collect straycharge.
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Twin-Tub (Twin-Well) CMOS Process
FDP_VLSI_ANNA UNIV53
This technology provides the basis for separate optimization of the nMOS and pMOS
transistors, thus making it possible for threshold voltage, body effect and the channeltransconductanceof both types of transistors to be tuned independently.
Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxiallayer on top.
This epitaxial layer provides the actual substrate on which the n-well and the p-well
are formed. Since two independent doping steps are performed for the creation of the well
regions, the dopant concentrations can be carefully optimized to produce the desireddevice characteristics. The Twin-Tub process is shown below.
In the conventional p & n-well CMOS process, thedoping density of the well region is typically aboutone order of magnitude higher than the substrate,which, among other effects, results in unbalanceddrain parasitics. The twin-tub process avoids thisproblem.
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Benefits of SOI
FDP_VLSI_ANNA UNIV54
No parasitic bipolar devices
No Latchup
Sources
Cosmic Rays (aircraft electronics vulnerable)Decaying uranium and thorium impurities in integrated circuit interconnect
Generates electron-hole pairs in substrate
Excess carriers collected by diffusion terminals of transistorsCan cause upset of state nodesfloating nodes, DRAM cells most vulnerable
Not as much substrate to generate charge in!
Alpha Particles
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Another subtle advantage:
FDP_VLSI_ANNA UNIV55
Lower thresold voltage In bulk-CMOS, Vt varies with channel length
variations in polysilicon etching shows up as variations in threshold voltages
Vt must be high enough in the worst case (lowest Vt) to limit subthresholdleakage, so nominal threshold must b higher
SOI has lower Vt variations than bulk-CMOS So nominal Vt can be lower, resulting in faster circuits, esp. for lower VDD
The immunity to latch-up, resistance to alpha-particle strikes makes SOIattractive for space-based ICs, military applications seeking radiation hardness
Honeywell is a leader in CMOS SOI for military, space applications Smaller diffusion capacitance makes it attractive for low-power design (lowers
dynamic power dissipation)
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Wafer Inspection
FDP_VLSI_ANNA UNIV56
Each IC on the completed wafer is electronically tested by the tester.
After this inspection, the front-end processing is complete
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Dicing
FDP_VLSI_ANNA UNIV57
In back end processing, a wafer completed in front end processing is cut intoindividual IC chips and encapsulated into packages.
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Power Supply Voltage
FDP_VLSI_ANNA UNIV58
GND = 0 V In 1980s, VDD= 5V
VDDhas decreased in modern processes High VDDwould damage modern tiny transistors
Lower VDDsaves power
VDD= 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
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Layout
FDP_VLSI_ANNA UNIV59
Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed,
cost, and power)
Feature sizef= distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design rules
Express rules in terms of l=f/2
E.g. l= 0.3 mm in 0.6 mm process
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LAYOUT DEIGN RULES
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Prescription for preparing photo masks in fabrication of IC Circuit designer links process engineer in manufacturing phase
OBJECTIVE To obtain the circuit with optimum yield
As small a geometry as possible
No compromise in reliability of the circuit
More conservative more likely the circuit will function
More aggressive greater the improvements in performance
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LAYOUT DEIGN RULES
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Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)
All widths, spacings, and distances are written in the form
Value = lm
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Layout Layers and Design Rules
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Size rules,such asminimum width:
The dimensions of any component (shape), e.g., length of a boundary edge orarea of the shape, cannot be smaller than given minimum values. These values
vary across different metal layers.
Separation rules, such asminimum separation:
Two shapes, either on the same layer or on adjacent layers, must be aminimum (rectilinear or Euclidean diagonal) distance apart.
Overlap rules, such asminimum overlap: Two connected shapes on adjacent layers must have a certain amount of
overlap due to inaccuracy of mask alignment to previously-made patterns onthe wafer.
Categories of design rules
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Layout Layers and Design Rules
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Categories of design rules
Minimum Width:a
Minimum Separation:b,c,d
Minimum Overlap: e
a
d
c
l
b
e
l: smallest meaningful technology-dependentunit of length
2
011SpringerVerlag
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Physical Design Optimizations
FDP_VLSI_ANNA UNIV64
Technology constraints
enable fabrication for a specific technology node and are derived fromtechnology restrictions. Examples include minimum layout widths and spacing
values between layout shapes. Electrical constraints
ensure the desired electrical behavior of the design. Examples include meetingmaximum timing constraints for signal delay and staying below maximumcoupling capacitances.
Geometry (design methodology) constraints
Introduced to reduce the overall complexity of the design process. Examplesinclude the use of preferred wiring directions during routing, and theplacement of standard cells in rows.
Types of constraints
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Constraints & issues
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Its important that these rules dont represent hard boundary between correctand incorrect fabrication
Represent the maximum tolerance that ensures very high probability of correctfabrication i.e) if the manufacturer finds a violation in design rules may stillfunction correctly he can proceed fabrication
But frequent departure from this may seriously prevent the success of thedesign
Constraints in Design rule
Line width
Interlayer registration
Two main issues:
Geometrical reproduction of features that can be reproduced by the maskingand lithographical process
Interactions between different layers
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Approaches used to describe design
rules
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In general micron rules - few microns resolution Alpha() and beta () rules Lambda based rules
Alpha() and beta () rules Feature size by and Grid size by
and related by a constant factor for Scaling Lambda based rules
Popularized by Mead and Conway in 1980 based on single parameter
No valid reason that micron rules cannot be used
Transistor dimensions are in W/L ratio NFETs are usually twice the width PFETs are usually twice the width of NFETs
Holes move more slowly than electrons (must be wider to deliver same current)
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Design rules and gate layout
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MOSIS design rules
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MOSIS design rules
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Vdd
GND
OUT
IN2
IN1OUT
IN2
IN1
OUTIN1
Vdd
GND
IN2
Contact
Diffusion layer
p-typetransistor
n-typetransistor
Metal layer
Poly layer
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1.3 VLSI Design Styles
Power (Vdd)-Rail
Ground (GND)-Rail
Contact
Vdd
GND
OUTIN2
IN1 OUTIN2
IN1
OUTIN1
Vdd
GND
IN2
Diffusion layer
p-typetransistor
n-typetransistor
Metal layer
Poly layer
Layout Layers and Design Rules
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y y g
Layout layers of an inverter cell
with external connections
Contact
Metal1
polysilicon
p/n diffusion
Vdd
GND
Via
Metal2
Inverter Cell
ExternalConnections
2
011SpringerVerlag
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LAYER REPRSENTATION
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CMOS process is too complexinhibit visualization of all mask levels Colour scheme is proposed by Jet propulsion Laboratory, California Institute of
Technology
For convenience the CIF (Caltech Intermediate Form) layer names as used byJPL
It is noted by four alpha numeric characters
Process CIF Character
P-channel MOS P
N-Channel MOS N
Bulk CMOS C
Silicon On Insulator S
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CMOS Process Enhancements
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Multiple threshold voltages
Low-Vt more on current, but greater subthreshold leakage
High-Vt less current, but smaller subthreshold leakage
User low-Vt devices on critical paths and higher-Vt devices elsewhere to limit
leakage power
Multiple masks and implantation steps are used to set the various thresholds
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CMOS Process Enhancements
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Silicon on insulator (SOI) process The transistors are fabricated on an insulator Two major insulators are used, SiOs and sapphire Two major advantages: elimination of the capacitance between the
source/drain regions and body, leading to higher-speed devices;
lower subthreshold leakageHigh-k gate dielectrics
MOS needs high gate capacitance to attract charge to channelverythin SiO2 gate dieletrics
Scaling trends indicate the gate leakage will be unacceptably large insuch thin gates
Gates could use thicker dielectrics and hence leak less if a materialwith a higher dielectric constant were available
CMOS Process Enhancements
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CMOS Process Enhancements
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Higher Mobility Increasing the mobility () of the semiconductor improves drive current
and transistor speed.
This has been achieved by using silicon germanium (SiGe) for bipolartransistors in the same process as conventional CMOS devices
SiGe transistors can be constructed on conventional CMOS processing by
adding a few extra implantation steps. The resulting bipolar transistors have extremely good radio frequency (RF)
performance.
Strainedsilicon"silicon into which is implanted germanium atoms thatstretch the silicon lattice
This yields an increase in the mobility of the devices over conventional silicon of up to 70%and which corresponds to roughly a 30% increase in performance.
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CMOS Process Enhancements
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High-voltage Transistors
High-voltage MOSFETs can also be integrated onto conventional CMOS
processes for switching and high-power applications.
Gate oxide thickness and channel length have to be larger than usual toprevent breakdown. Specialized process steps are necessary to achieve very
high breakdown voltages.
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CMOS Process Enhancements
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Low Dielectrics Low-k dielectrics between wires are attractive because they decreasethe wire capacitance . This reduces both wire delay and powerconsumption.
Adding fluorine to the silicon dioxide creates fluorosilicate glass(FSG) with a dielectric constant of 3.6, widely used in 130 nm
processes. Adding carbon to the oxide can reduce the dielectric constant to 2.7-
3. Alternatively, porous polymer-based dielectrics can deliver evenlower dielectric constants.
Challenge
Developing low-k dielectrics that can withstand the hightemperatures during processing and the forces applied during CMP isa major challenge.
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BeyondConventional CMOS
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Nanotechnology is presently a hot research area seeking alternative structuresto
Replace CMOS when scaling finally runs out of steam.
For example, carbon nanotubes have been used to demonstrate transistorbehavior and build inverters
They are of interest as the nanotube is smaller than the predicted end- point forCMOS gate lengths.
Presently, the speeds are quite slow and the manufacturing techniques arelimited, but they may be of interest in the future.
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Manufacturing Issues
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Moving to new process for new designs
Failing to account the parasitic effect of metal fills
Failing to include process calibration test structures
Stack Height Effect
Substrate Noise
Self-Heating
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THANK YOU