MPMC Unit-1
-
Upload
as-krishna -
Category
Education
-
view
461 -
download
13
description
Transcript of MPMC Unit-1
![Page 1: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/1.jpg)
1
The 8085 Bus Structure
The 8-bit 8085 CPU (or MPU – Micro Processing Unit) communicates with the other units using a 16-bit address bus, an 8-bit data bus and a control bus.
![Page 2: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/2.jpg)
2
The 8085 Bus Structure
Address Bus
Consists of 16 address lines: A0 – A15
Operates in unidirectional mode: The address bits are always sent from the MPU to peripheral devices, not reverse.
16 address lines are capable of addressing a total of 216 = 65,536 (64k) memory locations.
Address locations: 0000 (hex) – FFFF (hex)
![Page 3: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/3.jpg)
3
The 8085 Bus Structure Data Bus
Consists of 8 data lines: D0 – D7
Operates in bidirectional mode: The data bits are sent from the MPU to peripheral devices, as well as from the peripheral devices to the MPU.
Data range: 00 (hex) – FF (hex)
Control Bus
Consists of various lines carrying the control signals such as read / write enable, flag bits.
![Page 4: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/4.jpg)
4
The 8085: CPU Internal Structure
The internal architecture of the 8085 CPU is capable of performing the following operations:
Store 8-bit data (Registers, Accumulator)
Perform arithmetic and logic operations (ALU)
Test for conditions (IF / THEN)
Sequence the execution of instructions
Store temporary data in RAM during execution
![Page 5: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/5.jpg)
5
The 8085: CPU Internal Structure
Simplified block diagram
![Page 6: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/6.jpg)
6
The 8085: Registers
![Page 7: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/7.jpg)
7
The 8085: CPU Internal Structure
Registers
Six general purpose 8-bit registers: B, C, D, E, H, L
They can also be combined as register pairs to perform 16-bit operations: BC, DE, HL
Registers are programmable (data load, move, etc.)
Accumulator
Single 8-bit register that is part of the ALU !
Used for arithmetic / logic operations – the result is always stored in the accumulator.
![Page 8: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/8.jpg)
8
The 8085: CPU Internal Structure
Flag Bits
Indicate the result of condition tests.
Carry, Zero, Sign, Parity, etc.
Conditional operations (IF / THEN) are executed based on the condition of these flag bits.
Program Counter (PC)
Contains the memory address (16 bits) of the instruction that will be executed in the next step.
Stack Pointer (SP)
![Page 9: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/9.jpg)
9 9
Features of 8086Features of 8086
- 8086 is a 16 bit microprocessor, It can - 8086 is a 16 bit microprocessor, It can perform read & write operation on both 8 or perform read & write operation on both 8 or 16 bit data..16 bit data..- 8086 has 16 bit data bus & 20 bit address - 8086 has 16 bit data bus & 20 bit address bus. bus.
![Page 10: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/10.jpg)
10 10
Features of 8086 ( continued)Features of 8086 ( continued)
- 20 bit address lines capable of addressing - 20 bit address lines capable of addressing 1MB memory location1MB memory location- 16 bit data are stored in 2 consecutive - 16 bit data are stored in 2 consecutive memory locationsmemory locations- 8086 can generate 16 bit I/O address , 256 - 8086 can generate 16 bit I/O address , 256 = 65536 I/O ports= 65536 I/O ports
![Page 11: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/11.jpg)
11 11
Features of 8086 ( continued)Features of 8086 ( continued)
- 8086 has fourteen 16 bit registers- 8086 has fourteen 16 bit registers - 8086 has multiplexed address & data bus- 8086 has multiplexed address & data bus- 8086 operates in 2 modes , minimum( single - 8086 operates in 2 modes , minimum( single processor )processor ) & maximum( multi processor) modes & maximum( multi processor) modes
- 8086 has 6 byte prefetch instruction Queue- 8086 has 6 byte prefetch instruction Queue
![Page 12: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/12.jpg)
12 12
Registers OrganisationRegisters Organisation• 16-Bit General Purpose Registers
– can access all 16-bits at once– can access just high (H) byte, or low (L) byte
only the GeneralPurpose registersallow access as8-bit High/Lowsub-registers
![Page 13: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/13.jpg)
13 13
Registers Organisation (continued)Registers Organisation (continued)
• Register Set16-Bit Segment Addressing Registers
CS Code SegmentDS Data SegmentSS Stack SegmentES Extra Segment
![Page 14: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/14.jpg)
14 14
Registers Organisation (continued)Registers Organisation (continued)
16-Bit Offset Addressing RegistersSP Stack PointerBP Base PointerSI Source IndexDI Destination Index
![Page 15: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/15.jpg)
15 15
Registers Organisation (continued)Registers Organisation (continued)
16-Bit Control/Status Registers- IP Instruction Pointer (Program Counter
for execution control)- FLAGS 16-bit register• It is not a 16-bit value but it is a
collection of 9 bit-flags (six are unused)• Flag is set when it is equal to 1• Flag is clear when it is equal to 0
![Page 16: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/16.jpg)
16 16
ArchitectureArchitecture
![Page 17: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/17.jpg)
17 17
Architecture (continued)Architecture (continued)
• The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU).
• The BIU fetches instructions, reads and writes data, and computes the 20-bit address
• The EU decodes and executes the instructions using the 16-bit ALU.
![Page 18: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/18.jpg)
18 18
Architecture (continued)Architecture (continued)
• The BIU contains the following registers- IP - the Instruction Pointer
- CS - the Code Segment Register- DS - the Data Segment Register- SS - the Stack Segment Register- ES - the Extra Segment Register
![Page 19: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/19.jpg)
19 19
Architecture (continued)Architecture (continued)
• The BIU fetches instructions using the CS and IP, written CS:IP, to construct the 20-bit address. Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
![Page 20: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/20.jpg)
20 20
Architecture (continued)Architecture (continued)
• The EU contains the following 16-bit general purpose registers:
» AX - the Accumulator» BX - the Base Register» CX - the Count Register» DX - the Data Register» SP - the Stack Pointer \ defaults to» BP - the Base Pointer / Stack segment» SI - the Source Index Register» DI - the Destination Register
![Page 21: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/21.jpg)
21 21
Architecture (continued)Architecture (continued)
HIGH BYTE GP REGISTERS LOW BYTE
AHBHCHDH
AXBXCXDX
ALBLCLDL
8 BIT 16 BIT 8 BIT
![Page 22: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/22.jpg)
22 22
Architecture (continued)Architecture (continued)ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBPSIDI
FLAGS
AXBXCXDX
Extra SegmentCode SegmentStack SegmentData SegmentInstruction Pointer
AccumulatorBase RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
16 bit arithmetic
![Page 23: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/23.jpg)
23 23
General purpose RegistersGeneral purpose Registers
• AX – Accumulator Register – Preferred register to use in arithmetic, logic and
data transfer instructions because it generates the shortest Machine Language Code
– Must be used in multiplication and division operations
– Must also be used in I/O operations
![Page 24: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/24.jpg)
24 24
General purpose Registers (conti..)General purpose Registers (conti..)
• BX– Base Register– Also serves as an address register– Used in array operations– Used in Table Lookup operations (XLAT )
![Page 25: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/25.jpg)
25 25
General purpose Registers (conti..)General purpose Registers (conti..)
• CX– Count register– Used as a loop counter– Used in shift and rotate operations
• DX– Data register– Used in multiplication and division– Also used in I/O operations
![Page 26: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/26.jpg)
26 26
Pointer & Index RegistersPointer & Index Registers
• Contain the offset addresses of memory locations
• Can also be used in arithmetic and other operations
• SP: Stack pointer – Used with SS to access the stack segment
![Page 27: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/27.jpg)
27 27
Pointer & Index Registers (continued)Pointer & Index Registers (continued)
• BP: Base Pointer– Primarily used to access data on the stack– Can be used to access data in other segments
• SI: Source Index register– is required for some string operations– When string operations are performed, the SI
register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations.
![Page 28: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/28.jpg)
28 28
Pointer & Index Registers (continued)Pointer & Index Registers (continued)
• DI: Destination Index register – is also required for some string operations.– When string operations are performed, the DI
register points to memory locations in the data segment which is addressed by the ES register. Thus, DI is associated with the ES in string operations.
• The SI and the DI registers may also be used to access data stored in arrays
![Page 29: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/29.jpg)
29 29
Segment RegistersSegment Registers
• Are Address registers• Store the memory addresses of instructions
and data• Memory Organization
– Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1 meg of addressable memory
![Page 30: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/30.jpg)
30 30
Segment Registers (continued)Segment Registers (continued)
– Addresses are expressed as 5 hex digits from 00000 - FFFFF
– Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!
– Solution: Memory Segment• Block of 64K (65,536) consecutive memory bytes• A segment number is a 16 bit number
![Page 31: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/31.jpg)
31 31
Segment Registers (continued)Segment Registers (continued)
• Segment numbers range from 0000 to FFFF• Within a segment, a particular memory
location is specified with an offset• An offset also ranges from 0000 to FFFF
![Page 32: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/32.jpg)
32 32
Segment Registers (continued)Segment Registers (continued)
Memory Model for 20-bit Address Space
![Page 33: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/33.jpg)
33 33
• to calculate physical memory address
![Page 34: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/34.jpg)
34 34
Memory Address Generation
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
![Page 35: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/35.jpg)
35 35
Flag RegisterFlag Register
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
![Page 36: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/36.jpg)
36
8086 Addressing Modes
![Page 37: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/37.jpg)
37
What is the Addressing Mode ?add dest, source ; dest +source→destadd ax,bx ; ax +bx→ax
The addressing mode means where and how the CPU gets the operands when the instruction is executed.
![Page 38: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/38.jpg)
38
• Addressing modes for Sequential Control Addressing modes for Sequential Control Transfer InstructionsTransfer Instructions
--------These Instructions transfer control to the These Instructions transfer control to the next sequential instruction in the programnext sequential instruction in the program
• Addressing modes for Control TransferAddressing modes for Control Transfer InstructionsInstructions
-----These Instructions transfer control to -----These Instructions transfer control to some predefined address Ex:INT CALLsome predefined address Ex:INT CALL
![Page 39: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/39.jpg)
39
Addressing modes for Sequential Control Addressing modes for Sequential Control
Transfer InstructionsTransfer Instructions Three types of 8086 addressing modes
• Immediate Addressing Mode ---CPU gets the operand from the instruction • Register Addressing Mode ---CPU gets the operand from one of the internal
registers
• Memory Addressing Mode ---CPU gets the operand from the memory location(s)
![Page 40: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/40.jpg)
40
ExpMOV AL, 80HMachine code:B080H
AL
B0H
80H
Instruction Queue
MACHINECODE
B8
12H
Instruction Queue
AL
MACHINECODE
AH
34H
12
34
80H
80H
12 34
1. Immediate Addressing Mode
MOV AX, 1234HMachine Code:B83412H
![Page 41: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/41.jpg)
41
Exp : MOV AX, CX
89
C1
Memory AX
CX Machine code
2. Register Addressing Mode
![Page 42: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/42.jpg)
42
• Specify an offset address (effective address) using expressions of the form (different parts of expression are optional):
– [ Base Register + Index Register+ Displacement]• 1) Base Register---BX, BP• 2) Index Register---SI, DI• 3) Displacement ---constant value• Example: 1) add ax,[20h] 2) add ax,[bx] 3) add ax,[bx+20h] 4) add ax, [bx+si] 5) add ax, [bx+si+20h]
3. Memory Addressing Mode
![Page 43: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/43.jpg)
43
⑴ Direct Addressing ModeExp: MOV AL, [1064H]
Machine code:A06410H
• The offset address of the operand is provided in the instruction directly;
• The physical address can be calculated using the content of DS and the offset :
PA = (DS)*10H+Offset
3. Memory Addressing Mode
![Page 44: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/44.jpg)
44
⑴ Direct Addressing ModeExample: MOV AL, [1064h] ;Assume (DS)=2000HMachine code: A06410H
21064H
( DS)*10H=20000H
20000H
21064H
AL
A0
64
10
45
…
CodeSegment
DataSegment
45
45
+ 1064H
![Page 45: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/45.jpg)
45
⑵ Register Indirect Addressing Mode
• The address of memory location is in a register (SI,DI,or BX only)
• The physical address is calculated using the content of DS and the register(SI,DI,BX) PA = (DS)*10H+(SI)/(DI)/(BX)
3. Memory Addressing Mode
![Page 46: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/46.jpg)
46
50
40
……
M
AX
⑵ Register Indirect Addressing Mode ASSUME: (DS)=3000H, (SI)=2000H, (BX)=1000H
30000H
(DS)*10H=30000H(SI)= 2000H+
32000H
32000H
40 50
50
40
……
64H
M
AL 30000H
(DS)*10h= 30000H (BX)= 1000H+
31000H
31000H64H
64H
MOV [BX], ALMOV AX, [SI]
![Page 47: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/47.jpg)
47
⑶ Register Relative Addressing
EA=
(BX)(BP)(DI)(SI)
+ Displacement
For physical address calculation: DS is used for BX,DI,SI; SS is used for BP
PA=(DS)*10H+(BX)/(DI)/(SI)+DispOR
PA=(SS)*10H+(BP)+Disp
![Page 48: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/48.jpg)
48
⑶ Register Relative AddressingMOV CL, [BX+1064H] ;assume: (DS)=2000h, (bx)=1000h ;Machine Code: 8A8F6410
22064H
22064H
8F
64
10
45
…
CodeSegment
DataSegment
8A
…
CL
45
45 21000H
(BX)= 1000H
(DS)*10h= 20000H
20000H
+ 1064H
PA=(ds)*10h+(bx)+1064hPA=(ds)*10h+(bx)+1064h
![Page 49: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/49.jpg)
49
⑷ Based Indexed Addressing
EA=(BX)(BP) +
(DI)(SI)
• Base register(bx or bp) determines which segment(data or stack) the operand is stored;• if using BX, the operand is defaultly located in Data segment,then: PA=(DS)*10H+(BX)+(DI)/(SI)
• if using BP, the operand is defaultly located in stack segment,then: PA=(SS)*10H+(BP)+(DI)/(SI)
![Page 50: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/50.jpg)
50
⑷ Based Indexed Addressing
Example: MOV AH, [BP][SI];Assume(ss)=4000h,(bp)=2000h,(si)=1200h
56H
……
M
AH 40000H
(SS)*10H= 40000H(BP)= 2000H
+
43200H
43200H
(SI)= 1200H
56H
56H
PA=(ss)*10h+(bp)+(si)PA=(ss)*10h+(bp)+(si)
![Page 51: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/51.jpg)
51
⑸ Based Indexed Relative Addressing
EA=(BX)(BP) +
(DI)(SI) + Displacement
if using BX, the operand is defaultly located in Data segment,then: PA=(DS)*10H+(BX)+(DI)/(SI)+disp
if using BP, the operand is defaultly located in stack segment,then: PA=(SS)*10H+(BP)+(DI)/(SI)+disp
![Page 52: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/52.jpg)
52
⑸ Based Indexed Relative Addressing MOV [BX+DI+1234H], AH
;assume (ds)=4000h,(bx)=0200h,(di)=0010h;machine code:88A13412h
A1
34
12
…
Codesegment
Datasegment
88
…
45AH
40000H
(DS)*10H=40000H(BX)= 0200H
+
(DI)= 0010H 1234H
45
45
41444H
41444H
![Page 53: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/53.jpg)
53
Summary on the 8086 memory addressing modes
operand offset address Default Overridden ( effective address ) Segment Register Segment Register
3. Register [SI/DI/BX/BP+disp] (SI)/(DI)/(BX)/(BP)+disp DS CS ES SS Relative Addressing
2. Register [BX]/[SI] /[DI] Content of the R DS CS ES SS Indirect Addressing
1. Direct Addressing [disp] disp DS CS ES SS
4. Based Indexed [BX+SI/DI] (BX)+disp DS CS ES SS Addressing [BP+SI/DI] (BP)+disp SS CS ES DS
5. Based Indexed [BX+SI/DI+disp] (BX)+(SI)/(DI)+disp DS CS ES SS Relative Addressing [BP+SI/DI+disp] (BP)+(SI)/(DI)+disp SS CS ES DS
![Page 54: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/54.jpg)
54
Examples:Assume: (BX)=6000H, (BP)=4000H, (SI)=2000H, (DS)=3000H, (ES)=3500H, (SS)=5000H
3000:0520 30520HDirect Addressing
2. MOV AX, [BX]
1. MOV AX, [0520H]
5. MOV AX, ES: [BX+SI+0050H]
4. MOV AX, [BP+6060H]
Register Indirect Addressing 3000:6000 36000H
Register Relative Addressing
Register Relative Addressing
3. MOV AX, [SI+1000H] 3000:3000 33000H
5000:A060 5A060H
3500:8050 3D050HBased Indexed Relative Addressing
Instruction Instruction addressingaddressing logical logical physical physical modemode address address address address
![Page 55: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/55.jpg)
55
•Addressing modes for Control Transfer Addressing modes for Control Transfer InstructionsInstructions
Modes for Control Modes for Control Transfer InstructionsTransfer Instructions
Inter-segmentInter-segment
Intra-segmentIntra-segment
Inter-segment-In DirectInter-segment-In Direct
Inter-segment-DirectInter-segment-Direct
Intra-segment DirectIntra-segment Direct
Intra-segment IndirectIntra-segment Indirect
![Page 56: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/56.jpg)
56
Inter-segment-Direct Addressing ModeInter-segment-Direct Addressing ModeThe address to which control is to be transferred lies in the different The address to which control is to be transferred lies in the different segment and appears directly In the instruction as an immediate segment and appears directly In the instruction as an immediate displacement value w.r.t IP If the displacement is displacement value w.r.t IP If the displacement is 8-bits(-128<d<+127)(short) If the displacement is 8-bits(-128<d<+127)(short) If the displacement is 16-bits(-32768<d<+32767)(Long)16-bits(-32768<d<+32767)(Long)
Ex: CALL 0020:0010HEx: CALL 0020:0010H
segment1
CS
Assume CS=2000h,IP=0000hAssume CS=2000h,IP=0000h
After JMP,CS= 0020h,IP=0010hAfter JMP,CS= 0020h,IP=0010h
segment2
IP
20
00
10
Sub-routine
…
00
…
0020
Op-code for CALL
0010
2000hCS
![Page 57: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/57.jpg)
57
Inter-segment-IN-Direct Addressing ModeInter-segment-IN-Direct Addressing ModeThe address to which control is to be transferredThe address to which control is to be transferred lies in the different \segment and it is passed to lies in the different \segment and it is passed to thethe instruction indirectly i.e contents of a memory instruction indirectly i.e contents of a memory blockblock containing four bytes containing four bytes IP(LSB),IP(MSB),CS(LSB),CS(MSB)IP(LSB),IP(MSB),CS(LSB),CS(MSB)
Ex: CALL [BX]Ex: CALL [BX]
IP(LSB)10
IP(MSB)00
CS(LSB)20
Sub-routine
…
segment1
…
0020CS
Before JMP,Assume BX=100h, CS=3000h,IP=200hBefore JMP,Assume BX=100h, CS=3000h,IP=200h
Op-code for CALL
After JMP,CS= 0020h,IP=0010hAfter JMP,CS= 0020h,IP=0010h
segment2
0010IP
3000hCS
CS(MSB)00
0010IP
![Page 58: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/58.jpg)
58
Intra-segment-Direct Addressing ModeIntra-segment-Direct Addressing ModeThe address to which control is to be transferred lies in the sameThe address to which control is to be transferred lies in the samesegment and appears directly In the instruction as an immediate segment and appears directly In the instruction as an immediate displacement value w.r.t IP If the displacement is displacement value w.r.t IP If the displacement is 8-bits(-128<d<+127)(short) If the displacement is 8-bits(-128<d<+127)(short) If the displacement is 16-bits(-32768<d<+32767)(Long)16-bits(-32768<d<+32767)(Long)
Ex: CALL 500hEx: CALL 500h
CodeSegment
Assume CS=2000h,IP=0000hAssume CS=2000h,IP=0000h
After CALL,CS= 2000h,IP=IP+500hAfter CALL,CS= 2000h,IP=IP+500h
IP
00
05
Op-code for CALL2000hCS
0500Sub-routine
0000IP
![Page 59: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/59.jpg)
59
IP
Intra-segment-In-Direct Addressing ModeIntra-segment-In-Direct Addressing ModeIn this mode the displacement to which control is to be transferred,In this mode the displacement to which control is to be transferred,Is in the same segment in which the control transfer instruction liesIs in the same segment in which the control transfer instruction liesBut it is passed to the instruction indirectlyBut it is passed to the instruction indirectly
Ex: CALL [BX]Ex: CALL [BX]
CodeSegment
Assume CS=2000h,IP=0000h , BX=800hAssume CS=2000h,IP=0000h , BX=800h
After CALL,CS= 2000h,IP=IP+800hAfter CALL,CS= 2000h,IP=IP+800h
IP
00
05
Op-code for CALL2000hCS
0800Sub-routine
0000IP
![Page 60: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/60.jpg)
60
Example:Example:
The Contents of different registers are given below. Form effective addresses for The Contents of different registers are given below. Form effective addresses for different addressing modesdifferent addressing modesOffset(displacement)= 5000HOffset(displacement)= 5000HAX=1000H,BX=2000H,SI=3000H,DI=4000H,BP=5000H,SP=6000H,CS=0000H,DS=1000HAX=1000H,BX=2000H,SI=3000H,DI=4000H,BP=5000H,SP=6000H,CS=0000H,DS=1000HSS=2000H,IP=7000HSS=2000H,IP=7000HShifting a number four times is equivalent to multiplying it by 16Shifting a number four times is equivalent to multiplying it by 16D D or 10 or 10HH
![Page 61: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/61.jpg)
61
Instruction Set &
Assembler Directives
![Page 62: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/62.jpg)
62
Programming in 8088/8086
Three levels of languages available to program a microprocessor:
Machine Languages, Assembly Languages, and High-level Languages.
Machine Language
A sequence of binary codes for the instruction to be executed by
microcomputers.
Long binary bits can be simplified by using Hexadecimal format
It is difficult to program and error prone.
Different uP (micro-processor) uses different machine codes.
![Page 63: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/63.jpg)
63
Programming in 8088/8086 (cont.)
Assembly Language
To simplify the programming, assembly language (instead of machine language) is used.
Assembly language uses 2- to 4-letter mnemonics to represent each instruction type. E.g. “Subtraction” is represented by SUB
Four fields in assembly language statement:
Label, OP Code, Operand and Comment fields.
Programs will be ‘translated’ into machine language, by Assembler, so it can be loaded into memory for execution.
High-Level Language
High level languages, like C, Basic or Pascal, can also be used to program
microcomputers.
An interpreter or a compiler is used to ‘translate’ high level language statement to machine code. High level language is easier to read by human and is more suitable when the programs involves complex data structures.
![Page 64: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/64.jpg)
64
Assemblers
Programming the instructions directly in machine code is possible but every machine codes depending on how the data is stored.
The process of converting the microprocessor instructions to the binary machine code can be performed automatically by a computer program, called an ASSEMBLER. Popular assemblers include IBM macro Assembler, Microsoft Macro Assembler (MASM) and Borland Turbo Assembler(installed on IE NT Network).
Most assemblers accept an input text file containing lines with a rigorously defined syntax split into four fields.
Not all fields need to be present in a line. Eg. A line can be just a comment line if it starts with semicolon;
![Page 65: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/65.jpg)
65
Source Codes, Object Codes and Linking
Source code is the text written by the programmer in assembly language
(or any other programming language)
Object code is the binary code obtained after running the assembler (
Or compiler if the source is in a high level language).
Modules of a program may be written separately and linked together to
form a executable program using a linker.
The linker joins the object code of the different modules into one large
object file which is executable. Most assemblers on IBM PCs produce
object files which must be linked ( even if there are no separate modules).
![Page 66: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/66.jpg)
66
Source Codes, Object Codes and Linking(Contd.,)
![Page 67: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/67.jpg)
67
Fields in Assembler
<label> <Mnemonic or directive> <operands> <;comment>
Comment field contains internal program documentation to improve
human readability -use meaningful comments
Operand field contains data or address used by the instruction.
The following conventions typically apply:
![Page 68: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/68.jpg)
68
Fields in Assembler (Contd.,)
<label> <Mnemonic or directive> <operands> <;comment>
Mnemonic/directive field contains the abbreviation for the processor instruction (eg. MOV) or an assembler DIRECTIVE. Adirective produces no object code but is used to control how the assembler operates.
Examples of directives include:
END -indicate the end of a program listing,
FRED LABEL NEAR - define “FRED” as a near label
TOM EQU 1000H -define “TOM” as the number 1000H
Label field contains a label which is assigned a value equal to the address where the label appears.
![Page 69: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/69.jpg)
69
Why Program in Assembler?
Assembler language instruction has a one-to-one correspondence with the binary machine code: the programmer controls precisely all the operations performed by the processor (a high level language relies on a compiler or interpreter to generate the instructions).
Assembler can generate faster and more compact programs
Assembler language allows direct access and full control of input/output operations
However, high-level language programs are easier to write and develop than assembler language programs
![Page 70: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/70.jpg)
70
Advantages of High-level languages
Block structure code: programs are most readable when they are
broken into “logical blocks” that perform specific function.
Productivity: easier to program
Level of complexity: no need to know the hardware details
Simple mathematics formula statement
Portability: only need to change the compiler when it is ported to other machine
Abstract data types: different data types like floating-point value,
record and array, and high precision value.
Readability
![Page 71: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/71.jpg)
71
Intel 8086 Instruction Set Overview
Intel 8088 has ninety basic ( ie not counting addressing mode
variants) instructions
Instructions belong to one of the following groups: data
transfer, arithmetic, logic, string manipulation, control
transfer and processor control.
![Page 72: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/72.jpg)
72
Converting Assembly Language Instructions to Machine Code
• An instruction can be coded with 1 to 6 bytes
• Byte 1 contains three kinds of information– Opcode field (6 bits) specifies the operation (add, subtract, move)
– Register Direction Bit (D bit) Tells the register operand in REG field in byte 2 is source or destination operand
1: destination 0: source
-Data Size Bit (W bit) Specifies whether the operation will be performed on 8-bit or 16-bit data
0: 8 bits 1: 16 bits
![Page 73: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/73.jpg)
73
• Byte 2 has three fields– Mode field (MOD)
– Register field (REG) used to identify the register for the first operand
– Register/memory field (R/M field)
![Page 74: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/74.jpg)
74
2-bit MOD field and 3-bit R/M field together specify the second operand
Mode Field encoding
Register/memory (R/M) Field Encoding
![Page 75: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/75.jpg)
75
Examples
MOV BL,AL (88C316)Opcode for MOV = 100010D = 0 (AL source operand)W bit = 0 (8-bits)
Therefore byte 1 is 100010002=8816
• MOD = 11 (register mode)• REG = 000 (code for AL)• R/M = 011 (destination is BL)
Therefore Byte 2 is 110000112=C316
![Page 76: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/76.jpg)
76
Examples:MOV BL, AL = 10001000 11000011 = 88 C3h
ADD AX, [SI] = 00000011 00000100 = 03 04 h
ADD [BX] [DI] + 1234h, AX = 00000001 10000001 __ __ h = 01 81 34 12 h
![Page 77: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/77.jpg)
77
Intel 8086 Instruction Set Overview
![Page 78: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/78.jpg)
78
(abbreviations below: d=destination, s=source)
General Data Movement Instructions
MOV d,s - moves byte or word; most commonly used instruction
PUSH s - stores a word (register or memory) onto the stack
POP d - removes a word from the stack
XCHG d,s - exchanges data, reg.-reg. Or memory to register
XLAT - translates a byte using a lookup table (has no operands)
IN d,s - moves data (byte or word) from I/O port to AX or AL
OUT d,s - moves data (byte or word) from AX or AL to I/O port
LEA d,s - loads effective address (not data at address) into register
LDS d,s - loads 4 bytes (starting at s) to pointer (d) and DS
LES d,s - loads 4 bytes (starting at s) to pointer (d) and ES
LAHF - loads the low-order bytes of the FLAGS register to AH
SAHF - stores AH into the low-order byte of FLAGS
PUSHF - copies the FLAGS register to the stack
POPF - copies a word from the stack to the FLAGS register
I. Data Movement Instructions (14)
![Page 79: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/79.jpg)
79
Instructions for moving strings
String instructions are repeated when prefixed by the REP mnemonic (CX contains the repetition count)
MOVS d,s - (MOVSB, MOVSW) memory to memory data transfer
LODS s - (LODSB and LODSW) copies data into AX or AH
STOS d - (STOSB, STOSW) stores data from AH or AX
![Page 80: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/80.jpg)
80
Data movement using MOV
MOV d, s
d=destination (register or effective memory address),
s=source (immediate data, register or memory address)
MOV can transfer data from:
any register to any register (except CS register)
memory to any register (except CS)
immediate operand to any register (except CS)
any register to a memory location
immediate operand to memory
MOV cannot perform memory to memory transfers (must use a register as an intermediate storage).
MOV moves a word or byte depending on the operand bit-lengths; the source
and destination operands must have the same bit length.
MOV cannot be used to transfer data directly into the CS register.
![Page 81: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/81.jpg)
81
The stackThe stack
The stack is a block of memory reserved for temporary storage of data and registers. Access is LAST-IN, FIRST OUT (LIFO)
The last memory location used in the stack is given by the effective
address calculated from the SP register and the SS register:
Example:
![Page 82: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/82.jpg)
82
The stack
Data may be stored onto the stack using the PUSH instruction –this automatically decrements SP by 2 (all stack operations involve words).
The POP instruction removes data from the stack (and increments SP by 2).
The stack may be up to 64K-bytes in length.
![Page 83: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/83.jpg)
83
PUSH and POP instructions
Examples:
PUSH AX ;stores AX onto the stack
POP AX ;removes a word from the stack and loads it into AX
PUSHF ;stores the FLAGS register onto the stack
POPF ; removes a word from the stack and loads it into FLAGS
PUSH may be used with any register to save a word (the register contents) onto the stack. The usual order (e.g. as with MOV) of storing the lower order byte in the lower memory location is used.
PUSH may also be used with immediate data, or data in memory.
POP is the inverse of the PUSH instruction; it removes a word from the top of the stack. Any memory location or 16-bit register (except CS) may be used as the destination of a POP instruction.
PUSHF and POPF saves and loads the FLAGS register to/from the stack,respectively.
![Page 84: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/84.jpg)
84
Exchange Instruction (XCHG)
XCHG exchanges the contents of two registers or a register and memory. Both byte and word sized exchanges are possible.
Examples:
XCHG AX,BX; exchange the contents of AX and BX
XCHG CL,BL; exchange CL and BL contents
XCHG DX,FRED; exchanges content of DX and memory
DS:FRED
Memory to Memory exchanges using XCHG are NOT allowed.
![Page 85: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/85.jpg)
85
Translate Instruction (XLAT)
Many applications need to quickly convert byte sized codes to other values mapping one byte value to another (e.g. mapping keyboard binary codes to ASCII code)
XLAT can perform a byte translation using a look-up table containing up to 256 elements
XLAT assumes that the 256-byte table starts at the address given by DS:BX (i.e. effective address formed by the DS and BX registers). AL is used as an index to point to the required element in the table prior to the execution of XLAT. The result of XLAT instruction is returned in the same register (AL). Address Data TableAddress Data Table
![Page 86: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/86.jpg)
86
LEA &LDS
LEA loads the offset of a memory address into a 16-bit register. The offset address may be specified by any of the addressing modes.
Examples (with BP=1000H):
LEA AX,[BP+40H];=>SS:[1000H+40H] =SS:[1040H];load 1040H into AX
LEA BX,FRED; load the offset of FRED (in data segment) to BX
LEA CX,ES:FRED; loads the offset of FRED (in extra segment) to CX
LDS -Load data and DS
LDS reads two words from the consecutive memory locations and loads them into the specified register and the DS segment registers.
Examples (DS=1000H initially)
LDS BX,[2222H]; copies content of 12222H to BL, 12223H to BH, and 12224 and 12225 to DS register
LDS is useful for initializing the SI and DS registers before a string operation. E.g. LDS SI, sting_pointer
The source for LDS can be displacement, index or pointer register (except SP).
![Page 87: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/87.jpg)
87
LES -Load data and ES
LES reads two words from memory and is very similar to LDS except that the second word is stored in ES instead of DS.
LES is useful for initializing that DI and ES registers for strings operation.
Example (with DS=1000H):
LES DI, [2222H]; loads DI with contents stored at 12222H and 12223H and loads ES with contents at 12224 and 12225H
![Page 88: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/88.jpg)
88
LAHF, SAHF
LAHF (load AH with the low-order byte of the FLAGS register) and SAHF (Store AH into the low-order byte of the FLAG register)
very rarely used instructions -originally present to allow translation of 8085 programs to 8086.
![Page 89: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/89.jpg)
89
IN, OUT
Examples:
IN AX, 0C8h ;reads port address at C8h (8 bit address) and loads into AX
IN AL, DX ;reads the port address given by DX and loads into AL
OUT p8 ,AX ;sends the data in AX to port p8
OUT DL, AX ; sends the data in AX to port given by DL
IN reads data from the specified IO port (8-bit or 16-bit wide) to the accumulator (
AL or AX).
The IO port can be an immediate address (8-bit only) or specified by a variable
or register (8 or 16-bit address). (Seems only DX can be used.)
OUT sends data from the accumulator register to the specified I/O port. Both byte and word sized data may be sent using IN and OUT.
![Page 90: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/90.jpg)
90
II. Arithmetic Instructions(20)II. Arithmetic Instructions(20)
Intel 8088 has 20 instructions for performing integer addition,Intel 8088 has 20 instructions for performing integer addition,Subtraction , multiplication, division, and conversions from binary coded decimal to binary.Subtraction , multiplication, division, and conversions from binary coded decimal to binary.
![Page 91: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/91.jpg)
91
Arithmetic Instructions (cont.)Arithmetic Instructions (cont.)
![Page 92: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/92.jpg)
92
AdditionAddition
Binary addition of two bytes or two words are performed using:Binary addition of two bytes or two words are performed using:ADD d,sADD d,s
ADD adds bytes or words in d and s and stores ADD adds bytes or words in d and s and stores result in d.result in d.The operands d and s can use the same addressing modes as in MOV.The operands d and s can use the same addressing modes as in MOV. Addition of double-word is achieved by using the carry bit in the FLAGS register. The Addition of double-word is achieved by using the carry bit in the FLAGS register. The instructioninstruction
ADC d,sADC d,sautomatically includes the carry flag, and is used to add the more significant word in a automatically includes the carry flag, and is used to add the more significant word in a
double-word addition.double-word addition.
AdditionExample: addition of two double words stored at [x] and [y]MOV AX, [x] ; Loads AX with the word stored at location [x]MOV DX, [x+2] ; Loads the high order wordADD AX, [y] ; Adds the low order word at [y]ADC DX, [y+2] ; Add including the carry from the low order words
![Page 93: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/93.jpg)
93
Addition (cont.)Addition (cont.)
Example: addition of two double words stored at [x] and [y]Example: addition of two double words stored at [x] and [y]
Addition of binary coded decimal numbers (BCD) can be performed by using ADD Addition of binary coded decimal numbers (BCD) can be performed by using ADD or ADC followed by the DAA instruction to convert theor ADC followed by the DAA instruction to convert thenumber in register AL to a BCD representation. (see example)number in register AL to a BCD representation. (see example)
Addition of numbers in their ASCII form is achieved by using AAA (ascii adjust Addition of numbers in their ASCII form is achieved by using AAA (ascii adjust after addition).after addition).
![Page 94: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/94.jpg)
94
ASCII adjust for Addition (AAA)
ASCII codes for the numbers 0 to 9 are 30H to 39H respectively. The ascii adjust instructions convert the sum stored in AL to two-byte unpack BCD number which are placed in AX. When 30H is added to each byte, the result is the ASCII codes of the digits representing the decimal for the original number in AL.Example: Register AL contains 31H (the ASCII code for 1), BL contains 39H (the ASCII code for 9).ADD AL, BL ; produces the result 6AH which is kept in AL.AAA ; converts 6AH in AL to 0100H in AXAddition of 30H to each byte of AX produces the result 3130H (the ASCII codefor 10 which is the result of 1+9)
![Page 95: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/95.jpg)
95
Subtraction
![Page 96: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/96.jpg)
96
Multiplication
![Page 97: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/97.jpg)
97
Division
![Page 98: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/98.jpg)
98
SIGN EXTENDED INSTRUCTIONS
![Page 99: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/99.jpg)
99
Other Arithmetic Instructions
![Page 100: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/100.jpg)
100
III. Logic and bit MANIPULATION Instructions (12)
![Page 101: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/101.jpg)
101
III. Logic and bit MANIPULATION Instructions (12) (Contd)
![Page 102: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/102.jpg)
102
Shift and Rotate
![Page 103: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/103.jpg)
103
Shift and Rotate(Contd)
![Page 104: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/104.jpg)
104
List file of 8086 assembly language program to produce packed BCD from two ASCII characters
![Page 105: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/105.jpg)
105
IV. Strings Instruction (6)
![Page 106: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/106.jpg)
107
IV. Instruction for moving strings(Contd)
![Page 107: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/107.jpg)
108
REP prefix
![Page 108: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/108.jpg)
109
LODS and STOS string instructions
![Page 109: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/109.jpg)
110
LODS and STOS string instructions(Contd)
![Page 110: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/110.jpg)
111
CMPS and SCAS string instructions
![Page 111: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/111.jpg)
112
V. Program Flow Instruction
![Page 112: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/112.jpg)
113
Program Flow Instruction
![Page 113: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/113.jpg)
114
Unconditional JUMP
![Page 114: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/114.jpg)
115
Unconditional JUMP (cont.)
![Page 115: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/115.jpg)
116
List file of program Demonstrating “backward” JMP
![Page 116: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/116.jpg)
117
List file of program demonstrating “forward” JMP
![Page 117: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/117.jpg)
118
Conditional Jumps
![Page 118: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/118.jpg)
119
8086 Conditional Jump Instructions
![Page 119: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/119.jpg)
120
Ex.: Reading ASCII code when a strobe is present
![Page 120: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/120.jpg)
121
Assembly language for Reading ASCII code when a strobe is present
![Page 121: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/121.jpg)
122
Loops
![Page 122: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/122.jpg)
123
Procedures and modular Programming
![Page 123: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/123.jpg)
124
![Page 124: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/124.jpg)
125
![Page 125: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/125.jpg)
126
Procedures and modular Programming (Contd)
![Page 126: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/126.jpg)
127
Procedures
![Page 127: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/127.jpg)
128
Stack Diagram
![Page 128: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/128.jpg)
129
Using PUSH and POP instructions
![Page 129: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/129.jpg)
130
Interrupt Instructions
![Page 130: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/130.jpg)
131
Interrupt Instructions
![Page 131: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/131.jpg)
132
![Page 132: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/132.jpg)
133
• Assembler directives for data storage– DB - byte(s)– DW - word(s)– DD - doubleword(s)– DQ - quadword(s)– DT - tenbyte(s)
Program Data and Storage
![Page 133: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/133.jpg)
134
Arrays• Any consecutive storage locations of the
same size can be called an arrayX DW 40CH,10B,-13,0
Y DB 'This is an array'
Z DD -109236, FFFFFFFFH, -1, 100B• Components of X are at X, X+2, X+4, X+8• Components of Y are at Y, Y+1, …, Y+15• Components of Z are at Z, Z+4, Z+8, Z+12
![Page 134: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/134.jpg)
135
DUP• Allows a sequence of storage locations to
be defined or reserved• Only used as an operand of a define
directiveDB 40 DUP (?)
DW 10h DUP (0)
DB 3 dup ("ABC")
db 4 dup(3 dup (0,1), 2 dup('$'))
![Page 135: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/135.jpg)
136
Word Storage• Word, doubleword, and quadword data are
stored in reverse byte order (in memory)Directive Bytes in Storage
DW 256 00 01
DD 1234567H 67 45 23 01
DQ 10 0A 00 00 00 00 00 00 00
X DW 35DAh DA 35Low byte of X is at X, high byte of X is at X+1
![Page 136: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/136.jpg)
137
EQU Directive• name EQU expression
– expression can be string or numeric– Use < and > to specify a string EQU– these symbols cannot be redefined later in the
programsample EQU 7Fh
aString EQU <1.234>
message EQU <This is a message>
![Page 137: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/137.jpg)
138
![Page 138: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/138.jpg)
139
![Page 139: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/139.jpg)
140
![Page 140: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/140.jpg)
141
![Page 141: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/141.jpg)
142
![Page 142: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/142.jpg)
143
![Page 143: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/143.jpg)
144
![Page 144: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/144.jpg)
145
![Page 145: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/145.jpg)
146
![Page 146: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/146.jpg)
147
![Page 147: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/147.jpg)
148
![Page 148: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/148.jpg)
149
![Page 149: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/149.jpg)
150
![Page 150: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/150.jpg)
151
![Page 151: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/151.jpg)
152
![Page 152: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/152.jpg)
153
![Page 153: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/153.jpg)
154
Macro definition: name MACRO [parameters,...] <instructions> ENDM
MyMacro MACRO p1, p2, p3 MOV AX, p1 MOV BX, p2 MOV CX, p3 ENDM ORG 100h MyMacro 1, 2, 3 MyMacro 4, 5, DX RET
![Page 154: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/154.jpg)
155
The syntax for procedure declaration: name PROC
; here goes the code ; of the procedure ...
RETname ENDP
![Page 155: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/155.jpg)
156
ORG 100h CALL m1 MOV AX, 2 RET ; return to Main Program. m1 PROCMOV BX, 5RET ; return to caller.m1 ENDP END
![Page 156: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/156.jpg)
157
ORG 100h MOV AL, 1MOV BL, 2 CALL m2CALL m2CALL m2CALL m2 RET ; return to operating system. m2 PROCMUL BL ; AX = AL * BL.RET ; return to caller.m2 ENDP END
![Page 157: MPMC Unit-1](https://reader033.fdocuments.in/reader033/viewer/2022061502/55783e29d8b42a1f5b8b4d4f/html5/thumbnails/157.jpg)
158