Motorola Semiconductor Data - MC14510B

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MOTOROLA CMOS LOGIC DATAMC14510B

352

Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î




ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

V – 55 C 25 C 125 C

Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

Output Voltage “0” Level

Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

0.05

0.05

0.05

Vdc

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.95

9.95

14.95

—

—

—

Vdc

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

1.5

3.0

4.0

Vdc

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3.5

7.0

11

—

—

—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1.7

– 0.36

– 0.9

– 2.4

—

—

—

—

mAdc

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.36

0.9

2.4

—

—

—

mAdc

Input Current Iin 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—

150

300

600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,

Per Package)

(CL

= 50 pF on all outputs, all

buffers switching)

IT 5.0

10

15

IT = (0.58 µA/kHz) f + IDDIT = (1.20 µA/kHz) f + IDDIT = (1.70 µA/kHz) f + IDD

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

**The formulas given are for the typical characteristics only at 25 C.

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

P2

P3

Q3

C

VDD

R

U/D

Q2

P1

P4

Q4

PE

VSS

CARRY OUT

Q1

CARRY IN



MOTOROLA CMOS LOGIC DATA

353

MC14510B





SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25 C, See Figure 2)

All Types

Characteristic Symbol VDD Min Typ # Max Unit

Output Rise and Fall TimetTLH, tTHL = (1.5 ns/pF) CL + 25 nstTLH, tTHL = (0.75 ns/pF) CL + 12.5 nstTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH,tTHL 5.0

1015

— — —

1005040

20010080

ns

Propagation Delay TimeClock to Q

tPLH, tPHL = (1.7 ns/pF) CL + 230 ns

tPLH, tPHL = (0.66 ns/pF) CL + 97 nstPLH, tPHL = (0.5 ns/pF) CL + 75 ns

tPLH,tPHL

5.0

1015

—

— —

315

130100

630

260200

ns

Clock to Carry OuttPLH, tPHL = (1.7 ns/pF) CL + 230 nstPLH, tPHL = (0.66 ns/pF) CL + 97 nstPLH, tPHL = (0.5 ns/pF) CL + 75 ns

tPLH,tPHL 5.0

1015

— — —

315130100

630260200

ns

Carry In to Carry OuttPLH, tPHL = (1.7 ns/pF) CL + 230 nstPLH, tPHL = (0.66 ns/pF) CL + 47 nstPLH, tPHL = (0.5 ns/pF) CL + 35 ns

tPLH,tPHL 5.0

1015

— — —

1808060

360160120

ns

Preset or Reset to QtPLH, tPHL = (1.7 ns/pF) CL + 230 nstPLH, tPHL = (0.66 ns/pF) CL + 97 nstPLH, tPHL = (0.5 ns/pF) CL + 75 ns

tPLH,tPHL 5.0

1015

— — —

315130100

630260200

ns

Preset or Reset to Carry OuttPLH, tPHL = (1.7 ns/pF) CL + 465 nstPLH, tPHL = (0.66 ns/pF) CL + 192 nstPLH, tPHL = (0.5 ns/pF) CL + 125 ns

tPLH

,tPHL 5.0

1015

— — —

550225150

1100450300

ns

Reset Pulse Width tw(H) 5.01015

360210160

18010580

— — —

ns

Clock Pulse Width tw(H) 5.01015

350170140

20010075

— — —

ns

Clock Pulse Frequency fcl 5.01015

— — —

3.06.08.0

1.53.04.0

MHz

Preset or Reset Removal TimeThe Preset or Reset Signal must be low prior to a

positive–going transition of the clock.

trem 5.010

15

650230

180

325115

90

— —

—

ns

Clock Rise and Fall Time tTLH,tTHL

5.01015

— — —

— — —

1554

µs

Setup TimeCarry In to Clock

tsu 5.01015

260120100

1306050

— — —

ns

Hold TimeClock to Carry In

th 5.01015

01010

– 50 – 15 – 5

— — —

ns

Setup TimeUp/Down to Clock

tsu 5.01015

500200175

25010075

— — —

ns

Hold TimeClock to Up/Down

th 5.010

15

– 70 – 30

– 20

– 140 – 80

– 50

— —

—

ns

Setup TimePn to PE

tsu 5.01015

– 50 – 30 – 25

– 100 – 65 – 55

— — —

ns

Hold TimePE to Pn

th 5.01015

480410410

240205205

— — —

ns

Preset Enable Pulse Width tWH 5.01015

20010080

1005040

— — —

ns

* The formulas given are for the typical characteristics only at 25 C.#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.




354

Figure 1. Power Dissipation Test Circuit and Waveform

Figure 2. Switching Time Test Circuit and Waveforms

PULSE

GENERATOR

0.01 µF

CERAMIC

VDD

ID500 pF

PE

CARRY IN

R

UP/DOWN

CLOCK

P1

P2

P3

P4

Q1

Q2

Q3

Q4

CARRYOUT

CL

CL

CL

CL

CL

20 ns 20 nsVDD

VSS

90%50%

10%CLOCK

VARIABLE

WIDTH

PROGRAMMABLE

PULSE

GENERATOR

VDD

CL

CLCL

CLCL

VSS

PE

CARRY IN

R

UP/DOWN

CLOCK

P1

P2

P3

P4

Q1

Q2

Q3

Q4

CARRYOUT

tsu trem

50%

50%

VDD

VSS

VDD

VSS

VDD

VSS

VOH

VOL

VSS

VDD

1fcl

tw(H) tw(H)

tTLH

tPLH

tPHL

tPLHtTHL

90%10%

CARRY OUT ONLY

tw(H)

trem

20 ns

90%10%

CARRY IN OR

UP/DOWN

CLOCK

PRESET ENABLE

Q1 OR CARRY OUT

RESET




355

MC14510B

LOGIC DIAGRAM

RESET

PRESET ENABLE

CLOCK

CARRY OUT

CARRY IN

UP/DOWN

P1

4

Q1

6

P2

12

Q2

11

P3

13

Q3

14

P4

3

Q4

2

P P P PPE

D

C

PE

D

C

PE

D

C

PE

D

C

Q

Q

Q

Q

Q

Q

Q

Q

STATE DIAGRAM FOR UP COUNTING STATE DIAGRAM FOR DOWN COUNTING

15

14

13

12 11 10 9 8

7

6

5

43210 43210

15

14

13

12 11 10 9 8

7

6

5




356

PIN DESCRIPTIONS

INPUTS

P1, P2, P3, P4, Preset Inputs (Pins 4, 12, 13, 3) — Data

on these inputs is loaded into the counter when PE is taken

high.

Carry In, (Pin 5) — Active–low input used when cascading

stages. Usually connected to Carry Out of the previous

stage. While high, clock is inhibited.

Clock, (Pin 15) — BCD data is incremented or de-cremented, depending on the direction of count, on the posi-

tive transition of this signal.

OUTPUTS

Q1, Q2, Q3, Q4, BCD outputs (Pins 6, 11, 14, 2) — BCD

data is present on these outputs with Q1 corresponding to

the least significant bit.

Carry Out, (Pin 7) — Used when cascading stages, this

pin is usually connected to Carry In of the next stage. This

synchronous output is active low and may also be used to

indicate terminal count.

CONTROLS

PE, Preset Enable (Pin 1) — Asynchronously loads data

on the Preset Inputs. This pin is active high and will inhibit the

clock when high.

R, Reset, (Pin 9) — Asynchronously resets the Q outputs

to a low state. This pin is active high and will inhibit the clock

when high.

Up/Down, (Pin 10) — Controls the direction of count: high

for up count, low for down count.

SUPPLY PINS

VSS, Negative Supply Voltage, (Pin 8) — This pin is

usually connected to ground.

VDD, Positive Supply Voltage, (Pin 16) — This pin is con-

nected to a positive supply voltage ranging from 3.0 Vdc to

18.0 Vdc.

Figure 3. Presettable Cascaded 8–Bit Up/Down Counter

Note: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant

Digit (M.S.D.) does not change while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 9

(count up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one

count. The L.S.D. now counts through another cycle (10 clock pulses) and the above cycle is repeated.

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4PE

Cin

CLOCK

U/D

R

PE

CinCLOCK

U/D

RP1 P2 P3 P4 P1 P2 P3 P4

Cout CoutL.S.D.

MC14510B

M.S.D.

MC14510B

TERMINAL

COUNT

INDICATOR

0 = COUNT

PRESET

ENABLE

1 = PRESET

1 = UP

0 = DOWN

P1 P2 P3 P4 P5 P6 P7 P8

+ VDD+ VDD

THUMBWHEEL SWITCHES

(OPEN FOR “0”)RESISTORS = 10 kΩ

CLOCK

+ VDD

RESET

OPEN = COUNT




357

MC14510B

TIMING DIAGRAM FOR THE PRESETTABLE

CASCADED 8–BIT UP/DOWN COUNTER

CLOCK

UP/DOWN

CARRY IN

(MSD)

PE

P8

P7

P6

P5

P4

P3

P2

P1

CARRY OUT

(MSD)Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

CARRY OUT

(LSD)

RESET

COUNT MSD

COUNT LSD

6 6 6 7 7 7 7 7 7 7 6 6 6 6 9 9 9 9 9 0 0 0 0 00 0 0

7 8 9 0 1 2 3 2 1 0 9 8 7 6 6 6 7 8 9 0 1 2 1 00 1 0

PRESET ENABLE DOWN

COUNTUP COUNT DOWN COUNT UP COUNT UP COUNT

RESETPRESET

ENABLE




358

Figure 4. Programmable Cascaded Frequency Divider

Note: The programmable frequency divider can be set by applying the desired divide ratio, in BCD, to the preset inputs. For

example, the maximum divide ratio of 99 may be obtained by applying a 10011001 to the preset inputs P0 to P7. For this divide

operation, both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and

should be avoided.

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

PE

Cin

CLOCK

U/D

P1 P2 P3

CoutL.S.D.

MC14510B

P1 P2 P3

P4 P5 P6 P7

THUMBWHEEL SWITCHES

(OPEN FOR “0”) RESISTORS = 10 kΩCLOCK (fin)

+ VDD

RESET

OPEN = COUNT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

M.S.D.

MC14510B

PE

CinCLOCK

U/D

RR

BUFFER

fout

P0

+ VDD + VDD

fout =finn

Cout

P4 P1 P2 P3 P4




359

MC14510B

OUTLINE DIMENSIONS

P SUFFIXPLASTIC DIP PACKAGE

CASE 648–08ISSUE R

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

–A–

B

F C

S

HG

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE –T–

MAM0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55

B 0.250 0.270 6.35 6.85C 0.145 0.175 3.69 4.44D 0.015 0.021 0.39 0.53F 0.040 0.70 1.02 1.77G 0.100 BSC 2.54 BSC

H 0.050 BSC 1.27 BSCJ 0.008 0.015 0.21 0.38K 0.110 0.130 2.80 3.30L 0.295 0.305 7.50 7.74M 0 10 0 10S 0.020 0.040 0.51 1.01

L SUFFIXCERAMIC DIP PACKAGE

CASE 620–10ISSUE V

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)WHERE THE LEAD ENTERS THE CERAMICBODY.

–A–

–B–

–T–

F

E

G

N K

C

SEATING

PLANE

16 PLD

SAM0.25 (0.010) T

16 PLJSBM0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93B 0.240 0.295 6.10 7.49C ––– 0.200 ––– 5.08D 0.015 0.020 0.39 0.50E 0.050 BSC 1.27 BSCF 0.055 0.065 1.40 1.65G 0.100 BSC 2.54 BSCH 0.008 0.015 0.21 0.38K 0.125 0.170 3.18 4.31L 0.300 BSC 7.62 BSCM 0 15 0 15

N 0.020 0.040 0.51 1.01

16 9

1 8

Motorola Semiconductor Data - MC14510B

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