IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-26, NO. 7, JULY 1979 1047

RAOSFET‘s with Polysilicon Gates Self-Aligned to the Field Isolation and to the Source anld

Drain Reg’ions v. LEO RIDEOUT, MEMBER, IEEE, AND VICTOR J. SILVESTRI

Abstract-The fabrication procedure and device characteristics of MOSFETs having a unique gate electrode structure are described. The polysilicon gate electrode of the structure is self-aligned on its ends with respect to the conductive source and drain regions, and is also self- aligned on its sides with respect to the nonconductive field oxide isola- tion regions. This double self-alignment feature results in a polysilicon gate electrode area that matches the channel region of the FET. An- other nawel feature of this “recessed-gate” device is a self-registering electrical connection between the gate and the metallic interconnection pattern. Compared to MOSFET’s fabricated using more conventional methods, smaller FET’s with increased packing density result from this misregisbation-tolerant contacting technique and the doubly self- aligned gate electrode structure. The new FET structure may be ap- plied to various integrated circuits such as ROM’s, PLA’s, and dynamic RAM’S. The use of a second layer of polysilicon and the addition of a fifth masking operation yields a dynamic RAM cell of small area with a diffused lrtorage region.

INTRODUCTION

I N THE FABRICATION of MOSFET integrated circuits, the minimum feature size and the mask-to-mask registra-

tion capability are determined by the available lithographic patterning technique. For any given lithographic technique, it is desira.ble to minimize the device area, and thereby increase the device packing density, without increasing the number of masking operations and without significantly complicating the fabrication process. It is also desirable that conventional fabri- cation steps and well-known material layers be utilized. Ex- amples of successful “device cleverness” techniques that have led to increased packing density include buried contacts [ l ] and recessed-oxide isolation [2]. The development of such techniques are partially responsible for the continuing increase in the number of active components per chip [3].

Fig. 1 illustrates top views of four polysilicon-gate MOSFET’s that utilize different gate patterns and different metal-to- polysilicon contacting approaches. This paper describes the fabrication procedure [4] and device characteristics [SI of a new MOSFET structure called a “recessed-gate” FET [6] which is shown in Fig. l(d). The polysilicon gate electrode of this device utilizes two unique features that lead to smaller device a;rea and higher array packing density. Like the FET of Fig. 1 (c), the recessed-gate FET has a self-registering gate to metal line contact, however, unlike the three polysilicon-gate

Manuscript received November 9, 1978;revised February 13, 1979. The authors are with IBM Thomas J . Watson Research Center, York-

town Heights, NY 10598.

LY SI

Fig. 1. Polysilicon-gate MOSFET structures with various metal line to polysilicon gate contacting approaches.

FET’s of Fig. I(a)-(c), the gate of the new structure does not overlap onto the field isolation oxide.

In all four of the FET’s shown in Fig. 1, the source and drain regions are self-aligned with respect to the ends of the gate electrode. Fig. l(a) and (b) illustrates polysilicon gate FET’s that utilize a conventional etched contact hole or “via” through an insulation layer of silicon dioxide which exists over the polysilicon material. The silicon dioxide layer may be thermally grown, chemically vapor-deposited, or formed by a combination of both techniques [7].

Because of etching tolerances and mask-to-mask misregistra- tion, an alignment border must be provided around the poly- silicion contact hole as shown in Fig. l(a) and (b). If an FET with a minimal channel length is desired, the metal contact must be made at the side of the channel, and this consumes a large area (see Fig. l(a)). If the contact is located over the channel [8], the overall area of the FET can be reduced (see Fig. 1 (b)), but the channel length is increased and the resultant channel current and device speed are compromised.

A smaller area FET with a short-channel length can be ob- tained if a self-registering contact technique [9], [lo] is used to connect the polysilicon gate to a metallic: interconnection line as shown in Fig. l(c). With the self-registering contact technique, the gate area is defined by use of ;an oxidation bar- rier layer of silicon nitride over the polysilicon. After diffus- ing or implanting the source and drain regions, an insulation layer of silicon dioxide is thermally grown over the entire structure, except on the polysilicon regions; which are still covered with silicon nitride. When the silicon nitride regions

0018-9383/79/0700-1047$00.75 0 1979 IEEE

1048 IEEE TRtiNSACTIONS ON ELECTRON DEVICES, VOL. ED-26, NO. 7 , JULY 1979

are dissolved away, the entire polysilicon area is exposed :or contacting by a metal line. This misregistration-tolerant fea- ture relieves the required alignment precision between litho- graphic masking patterns. For the conventional FET’s sho un in Fig. l(a) and (b), the contact hole pattern must be aligr ed to the polysilicon gate pattern, and the metallization pattlxn in turn must be aligned to the contact hole pattern. In con- trast, the FET’s with self-registering contacts of Fig. l(c) 2nd (d) require only that the metallization pattern be aligned1 LO

the polysilicon pattern. The three MOSFET’s shown in Fig. l(a)-(c) all exhibit In-

other area-consuming feature which is due to the requi vd polysilicon gate overlap onto the thick field isolation oxide. In these three cases, the polysilicon gate electrode must mer- lap onto the field isolation regions in order to insure complete coverage of the channel (i.e., to accommodate the allowable mask-to-mask misregistration between the recessed field oxide and the polysilicon gate patterns). The gate overlap of b e field isolation increases the required separation betw1:en adjacent FET’s, and hence the overall device area, excepl in certain cases [ l 11 where transistors in an array share a cc:jm- mon gate electrode.

The polysilicon gate electrode of the recessed-gate FEI’ of Fig. l(d) is self-aligned not only on its ends with respect to the n+ source and drain regions as in present-day MOSFET’s, ‘9ut also on its sides with respect to the field oxide isolation re- gions. It is the combination of the doubly aligned recessed- gate electrode and the self-registering gate contact that yields smaller FET’s with increased array packing density.

FABRICATION

In order to best appreciate the masking sequence and the process for the doubly self-aligned gate FET, it is helpful to first review the basic fabrication approach for the more con- ventional MOSFET’s of Fig. l(a) and (b). Fig. 2 illustrat’x; a conventional four-mask n-channel polysilicon gate pro1r:ess [ 7 ] . The starting wafer is typically (100)-oriented p-i:ipe silicon of 2- to 2 0 4 cm resistivity. The first masking .I’:%t- tern (Fig. 2(a)) is used to distinguish the device regions from the field isolation regions. Commonly, a recessed oxide (also called local or dielectric isolation) with an implanted boron channel stopper is used for field isolation between devces [2]. A pattern is defined in a silicon dioxide pad, a sili2on nitride oxidation barrier, and an implantation blocking layer (usually photoresist) over the future device regions. A3er implanting the boron ions, the resist pattern is dissolved md a thick, recessed, thermal oxide is grown in the field regi~wis. Then the nitride layer is removed by dissolving it in a suithle etchant such as phosphoric acid. The pad oxide is dissolved away in buffered hydrofluoric acid.

The next step in the conventional process is to grow the {:ate oxide in the device regions, and then to deposit a po1ysil:t:on layer. Various techniques exist for doping the polysilxon layer n-type either during or after deposition. The secmd masking pattern (Fig. 2(b)) delineates the polysilicion p t e which must overlap onto the field isolation oxide. Then the n+ source and drain regions are diffused or implanted, an’tl an insulation oxide layer is deposited or grown over the er:tire

CONVENTIONAL WLYSILICON-GATE MOSFET RECESSED POLYSILICON-GATE MOSFET M r--r yo-

DEVICE AREA I FIELD PATTERN DEVICE AREA

m 2 GATE PATTERN /jqJ GATE

(c) 3 CONTACT HOLE

PATTERN

MWW -CONTACT HOLES M U :CONTACT HOLES 2

4 METAL PATTERN

Fig. 2. Masking pattern sequences for conventional (a)-(d) and re- cessed-gate (e)-(h) MOSFET’s.

structure. The third masking step (Fig. 2(c)) defines the con- tact holes or “vias” to the n+ source and drain regions and to the polysilicon gate regions. During etching, the contact holes enlarge and, consequently, an alignment border must be pro- vided to accommodate the etching tolerances and mask-to- mask misregistration. The fourth basic masking operation (Fig. 2(d)) delineates the metallization pattern.

Now let us consider the masking sequence for the recessed- gate FET. The first masking pattern which defines the field isolation (Fig. 2(e)) is similar for both processes. Differences begin to appear with the second masking pattern. In the con- ventional approach, the second mask delineated the polysili- con gate electrode and interconnection pattern (Fig. 2(b)). With the recessed-gate approach, however, a polysilicon gate electrode and its contact area will be formed only wherever the first and second masking patterns cross each other (Fig. 2(f)). In the area of overlap, a stack of layers containing the entire gate structure is preserved. In order to self-align the gate to the field isolation oxide, the polysilicon gate structure must be fabricated prior to implanting the field doping and thermally growing the field isolation oxide. This is in contrast to the conventional approach in which the field isolation is implanted and grown prior to fabricating the gate structure. The third masking step of the new process (Fig. 2(g)) provides conventional etched contact holes to the n-type source and drain regions. The fourth mask (Fig. 2(h)) determines the metal interconnection line pattern.

Fig. 3 shows a cross-sectional view of the recessed-gate MOSFET at various stages in the fabrication process. The stack of layers delineated in the first masking step (Fig. 2(e)) is shown in Fig. 3(a). Basically, the stack consists of the SiOz gate insulator, the n-type polysilicon-gate electrode, and the nitride oxidation barrier. Thin oxide layers may be used on either side of the nitride layer to aid in its delineation and sub- sequent removal. After etching through the stack of layers to the substrate, a blanket B” implant of 2 X 1013-cm-2 dose

RIDEOUT AND SILVESTRI: MOSFET’s WITH POLYSILICON GATES 1049

OXIDE NITRID OXIDE

L \

Fig. 3. Cross-sectional view of the recessed-gate MOSFET at various stages in the fabrication process.

at 75-kr:V energy is performed to provide a parasitic channel in the field regions (see Fig. 3(a)). The range of the field im- plantatilon is small enough that it does not penetrate through the polysilicon gate to the channel region. Then the field isolation oxide is grown by a wet thermal oxidation. Oxida- tion is prevented on top of the polysilicon region due to the presence of the nitride layer. At this stage in the process, the polysilic,on region corresponds to the entire device area con- sisting of source, gate, and drain.

The gate electrode is defined using the second masking step (Fig. 20’)) as shown in Fig. 3(b). The stack of layers is again etched through to the substrate and self-aligned n-type source and drain regions are formed by diffusion or implantation, as shown in Fig. 3(c). Then a thick insulation oxide is grown over the source and drain regions by a second wet thermal oxidation. Again, the remaining portion of the nitride layer serves as an oxidation barrier, this time to prevent oxidation over the polysilicon gate electrode which now corresponds directly to the dimensions of the channel region. Now the remaining nitride region is dissolved away. The third masking step (not shown in Fig. 3) is used to define conventional etched contact holes to the source and drain regions, and the fourth masking step is used to define the metal pattern shown in Fig. 3(d). Wherever the rnetal line crosses a polysilicon gate, an electrical connection is made.

Fig. 4 compares the top view of a recessed-gate FET with cross-sectional views taken across and along the channel. The topography of the surface upon which the metallization pat- tern is formed is highly planarized because the polysilicon gate is completely surrounded by thick thermal oxide, hence the name “~recessed-gate FET.” Microstructural features num- bered a)-@ in Figs. 3 and 4 will be discussed in the following section. As shown in Fig. 4, wherever the metal line and poly- silicon gate patterns overlap, a self-registering or “misregistra- tion-tolerant’’ electrical contact is formed. The FET structure

Fig. 4. Top view and cross-sectional views taken across and along the channel of a recessed-gate FET.

is restricted in that the polysilicon region only serves as the gate electrode material and cannot be used for interconnection lines.

The recessed-gate fabrication process incorporates several novel steps. Contrary to conventional practice, the thin gate insulator and the gate structure are formed at the first stage of the process, prior to forming the field isolation oxide regions. Patterns are delineated twice in the nitride layer, and the nitride layer twice serves as an oxidation barrier; initially dur- ing growth of the field oxide, and later during growth of the insulation oxide over the source and drain. This multiple us- age of the nitride layer is essential to the doubly self-aligning feature of the gate electrode, and also helps to reduce the number of layers and fabrication steps.

MICROSTRUCTURE The fabrication procedure of the recessed-gate FET can lead

to the formation of undesirable microstructural features that nevertheless can be adequately controlled by proper choice of processing variables [4] . Nonplanar microstructures result from the two thick oxide growth steps which produce lateral oxide growth under the edges of the nitride. This lateral growth distorts the nitride oxidation barrier upward at its edges and leaves oxide ridges. The field oxidation step causes ridges (0 in Figs. 3 and 4) at the edges of the source and drain regions, while the insulation oxide causes ridges (0 in Figs. 3 and 4) at the ends of the gate electrode. Both oxidation steps contribute to a ridge (@ in Fig. 4) at the sides of the gate conductor. A metal interconnection line pattern or a second layer of polysilicon must be able to cross ‘over these ridges without experiencing line breakage or excessive thinning [ 121 .

Fig. 5 is a scanning-electron microscope photograph of a recessed-gate MOSFET. The outline in the field oxide of the second masking pattern (see Fig. 2(b)) can barely be distin- guished as a faint shadow on either side of the gate. In this example, the polysilicon gate area is approximately 3 pm long by 4 pm wide and the metal line that makels a self-registered contact to the gate is about 2 p m wide, hence, the contact area is 2 pm by 3 pm. A minimum lithographic feature size of about 2.5 pm was used. The three microstructural ridges illustrated in Figs. 3 and 4 are clearly visible in Fig. 5; the ridge at the end of the n-type doped region is less than 0.1 pm high

1050 IEEE TR.4NS ACTIONS ON ELECTRON DEVICES, VOL. ED-26, NO. 7 , JULY 1979

Fig. 5 . Scanning-electron microscope photograph of a recessed-!;ate MOSFET.

while .the ridges at the ends and sides of the gate are less tllan 0.2 pm high. The metal line of 1-pm thickness easily croses these ridges without difficulty.

A study of the microstructural formation [4] was ; [ ) ( x -

formed to determine the combination of film thicknesses that give an acceptably planar device structure. Typical layer thic:k- nesses for the recessed-gate devices were: gate oxide, 0.035 ban; polysilicon, 0.2 pm; nitride, 0.05 pm; thermal field oxide, 0.45 pm; and thermal insulation oxide over source and dr:lin, 0.4 pm. With this combination of parameters a tolerable ridge height of less than 0.2 pm was obtained.

Ridge coverage is not a serious problem for metal lines, ?ri- marily because the second thermal oxidation step (Le., the insulation oxide growth) diminshes the ridge height. If a : m - ond polysilicon layer is employed, for example, to fabricate the storage capacitor electrode of a dynamic memory t:~ll, then the ridge height at the n-type diffusion region boundary (0 in Fig. 3) is relatively higher. This results because a thin storage capacitor oxide, rather than a thick insulation ox:de, is grown over the diffused region and thus the ridge mii:ro- structure is not significantly smoothed out by the oxidali'on process. Fig. 6 shows a second polysilicon layer 0.35 pm t l ick crossing a 0.25-pm high ridge at the n-type diffusion bound- ary. Because it is formed by chemical vapor deposition, the polysilicon layer adequately covers the ridge without d ffi- culty. A double-polysilicon dynamic RAM cell which uses the recessed-gate FET as the switch of the one-device cell will be discussed later.

DEVICE CHARACTERISTICS

The experimental electrical characteristics of the recesired- gate FET are not significantly different from those of la:.ger area MOSFET's fabricated using more conventional meth80ds. It was expected that the extended high-temperature treatn:e:nt of the two wet thermal oxidations required for the recessed- gate FET fabrication would influence the electrical de,rice characteristics because a p-type channel implantation for threshold adjustment of B' at 30-keV energy and 1.5 X 1C1:"- cm-' dose is performed at the first stage of the process. 'The implanted boron profile diffuses downward into the subst .ate during the 1000°C growth of the thick field oxide, the Ihin

I

Fig. 6 . Cross section of a polysilicon storage capacitor electrode cross- ing a ridge at the diffusion boundary.

05

i 0 1 2 3 4 5 6 7 8

vsx (VI-

Fig. 7. Gate threshold voltage versus source-to-substrate bias for the recessed-gate FET (A), a conventional FET (B), and FET's without channel implant (C).

gate oxide, and the thick insulation oxide over the source and drain. An initial concern was that the channel profile would become so diffuse that the gate threshold voltage versus source-to-substrate bias characteristic or "substrate sensitivity" E131 would be significantly increased. As shown in Fig. 7, however, the substrate sensitivity of the recessed-gate MOSFET is somewhat increased over that of the minimum heat-treat- ment case, but not to an impractical degree. Fig. 7 compares the substrate sensitivity for the recessed-gate FET (Case A) with that of a more conventional polysilicon-gate FET (Case B) which employs minimum heat treatments. In the more con- ventional case, the channel implant was performed after grow- ing the field and the gate oxides and, in addition, the insula- tion oxide was chemically vapor-deposited at the relatively much lower temperature of 800°C. For reference, the unim- planted substrate sensitivity is also shown in the figure.

Another initial concern with the recessed-gate structure was the possible occurance of source-to-drain leakage current paths along the sidewalls of the channel at the field oxide boundary (i.e., beneath ridge @ in Fig. 4). Prior to fabrication of the devices, it was hypothesized that excessive boron segregation in the field oxide could lead to a region of locally low thresh- old along the edge of the gate. As the experimental subthresh- old conduction characteristic of Fig. 8 shows, however, the recessed-gate FET turns off to below lo-'' A which is con- sidered acceptable even for dynamic memory applications.

APPLICATIONS The basic form of the recessed-gate process is the four-mask

approach shown in Fig. 2. As mentioned earlier, because the polysilicon gate is self-aligned to the field oxide, the gate ma- terial cannot pass over the field oxide to be used as an inter- connection line. Consequently, with a four-mask process, all

RIDEOUT AND SILVESTRI: MOSFET’s WITH POLYSILICON GATES 1051

IO -12 0 I 2 3

v p (VI-

Fig. 8. Source-to-drain current versus gate voltage below a recessed-gate MOSFET.

RECESSED G A T 9

threshold for

n + DIFFUSED LINES-’

Fig. 9. SEM photograph of a fragment of an ROM or PLA using re- cessed-gate FET’s

META

M BIT LINE,

BIT LINEZ

Fig. 10. One-device dynamic RAM cell layout using the basic four- mask process.

of the wiring is provided by metal or n-type diffused lines. This approach is directly applicable to a read-only memory (ROM) or a programmable-logic array (PLA), and to dynamic one-device cell memories E141 . Fig. 9 is an SEM photograph of a fragment of a ROM or PLA using recessed-gate FET’s. The orthogonal array wiring is provided by n-type diffused lines and metal lines. One of the attractions of the recessed-gate FET is the ability to closely space many gates in an array as shown here. Furthermore, since the gate contact area corre- sponds, to the entire channel area, a suitable electrical connec- tion is, made to the gates even though the metal pattern is serioudy misaligned with respect to the gate pattern (cf. Figs. 4 and !?).

Fig. 10 illustrates the areal layout of a one-device dynamic RAM cell [ 141 using the four-mask recessed-gate process. Re-

DIFFUSED BIT LiNE

ULATONIFIELD IDE

V s ~ L ? ~ O N & - S T o R A G E CAPACITOR +sii&+&?iON+

Fig. 11. Top and side views of a one-device dynamic RAM cell made using five masking operations and a second layer of polysilicon.

cessed gates are used to provide both the FET switch and the electrode of the charge storage capacitor. Four polysilicon storage capacitor electrodes share a common metal plate line which is biased positively to create inversion storage regions under the capacitor electrodes.

A fifth masking operation can be added to the recessed- gate process to define a charge storage electrode using a sec- ond layer of polysilicon [6] . Fig. 11 shows top and side views of such a cell. No nitride oxidation barrier layer is used to define the second polysilicon (capacitor) pattern. Con- sequently, when the insulation oxide is grown over the ex- posed source and drain regions, an insulation oxide also grows over the polysilicon storage capacitor electrode.

Electrical connection can be made to the storage electrode using the same etched contact hole step that provides vias to the n-type diffused regions. The memory cell of Fig. 11 exhibits several interesting features. First, because the FET gate and polysilicon plate are delineated i n separate masking operations, they may be separated by less than one litho- graphic spacing which leads to some reduction in cell length [ lo ] . Second, because the gate does not overlap onto the field oxide, cells may be closely spaced, which also saves area. Third, because the FET gate pattern is defined prior to defin- ing the storage capacitor electrode, the source and drain can be formed before depositing the second polysilicon layer. Then, the n-type drain diffusion can extend under the capac- itor electrode, as shown in Fig. 11. Unlike inversion storage, with diffused storage the capacitor electrode can be main- tained at substrate potential, thereby simlplifying operation. Finally, the second polysilicon layer may be used for inter- connection wiring. Fig. 12 is an SEM photograph of a double- polysilicon recessed-gate memory cell.

SUMMARY

A polysilicon-gate MOSFET having a unique gate structure has been described. In this recessed-gate FET, the gate elec- trode is self-aligned on its ends to the source and drain regions, and on its sides to the field oxide isolation regions, Further- more, the gate structure is characterized by a self-registering or misregistration-tolerant contact to a metal interconnection line which relieves mask-to-mask alignment requirements. The

1052 IEEE TRAP+ YACTIONS ON ELECTRON DEVICES, VOL. ED-26, NO. 7, JULY 1979

Fig. 12. SEM photograph of double-polysilicon dynamic RAM cells..

topography of the final structure is highly planar and facil tates metal line coverage.

Contrary to conventional practice, the gate structure is f a b ricated prior to forming the field isolation oxide to allow t!he self-alignment between the polysilicon gate and the fiel.3 oxide. This eliminates the conventional gate overlap onto the field oxide and leads to a smaller FET structure. The recessetl. gate MOSFET offers a means for reducing the device area without increasing the number of masking steps, without n r -

ducing the minimum lithographic feature size, and witho1:Z significantly complicating the fabrication process. Colr~.. ventional materials and four basic masking operations a:ie employed. The devices demonstrate satisfactory e1ectric:d performance. The recessed-gate concept may be applied t o ’ various integrated circuits such as ROM’s, PLA’s, and dynamic RAM’S. The use of a second layer of polysilicon and the addi., tion of a fifth masking operation leads to a dynamic RAM cell of small area with a diffused storage region.

ACKNOWLEDGMENT

The authors wish to acknowledge the processing support (A‘

the silicon technology group at the T. J. Watson ResearchL Center, and valuable discussions with C. M. Osburn and R. I.[.

Dennard. The fabrication assistance of A. Cramer and the layout support of V. DiLonardo were particularly helpful.

REFERENCES

[ 11 L. L. Vadasz, “Integrated circuit structure and method for mak- ing integrated circuit structure,” U.S. Patent 3 699 646, Oct. 24, 1972.

[ 2 ] P. Richman, MOS Field-Effect Transistors and Integrated Cir- cuits. New York: Wiley, 1973. ch. 7.

[ 3 ] G. E. Moore, “Progress in digital integrated circuits,” in ZEEE Znt. Electron Devices Meet. Tech. Dip. (Washington, DC, Dec.

[ 4 ] V. J. Silvestri, V. L. Rideout, and V. Maniscalco, “Microstruc- tural studies of MOS field effect transistors (MOSFETs) with recessed polysilicon gates,” presented at the Electro-Chem. SOC. Spring Meeting, Philadelphia, PA, May 8-13, 1977.

[5] V. L. Rideout and V. J. Silvestri, “MOSFETs with polysilicon gates self-aligned to the field isolation and to the source/drain regions,” in IEEE Znt. Electron Devices Meet. Tech. Dig. (Wash- ington, DC, Dec. 1976), pp. 593-597.

[ 6 ] R. H. Dennard and V. L. Rideout, “Field effect transistors with polycrystalline silicon gate self-aligned to both conductive and nonconductive regions,” U.S. Patent Serial No. 686 969, filed May 14,1976.

[7] J. T. Clemens, R. H. Doklan, and J. J. Nolen, “An n-channel Si- gate integrated circuit technology,” in IEEE Znt. Electron Devices Meet. Tech. Dig. (Washington, DC, Dec. 1975), pp. 399-402.

[ 8 ] W. K. Hoffman and H. L. Kalter, “An 8K bit random-access memory chip using the one-device FET cell,” IEEE J. Solid-State Circuits, vol. SC-8, no. 5, pp. 298-305, Oct. 1973.

[ 9 ] V. L. Rideout, “Method for fabricating one-device memory cells with two layers of polycrystalline silicon,” U.S. Patent 4 075 045,

1975), pp. 11-13.

- . .

Feb. 28, 1978. 1101 V. L. Rideout. J. J. Walker, and A. Cramer, “A one-device mem- L .

ory cell using.a single layer of polysilicon.and a self-registering metal-to-polysilicon contact,” ZEEE Int. Electron Devices Meet. Tech. Dig. (Washington, DC, Dec. 1977). pp. 258-261.

[ 111 K. U. Stein and H. Friedrich, “A 1-mi12 single-transistor memory cell in silicon-gate technology,” ZEEE J. Solid-state Circuits, vol. SC-8, no. 5, p. 330, Oct. 1973, Fig. 2(c).

[ 121 V. J. Silvestri, V. L. Rideout, and V. Maniscalco, “A1 coverage of surface steps at Si03 insulated Si boundaries: A1 evaporation in vacuum and low pressure,” accepted for publication in J. Elec- trochem. SOC.

[13] V. L. Rideout, F. H. Gaensslen, and A. LeBlanc, “Device design consideration for ion implanted n-channel MOSFETs,” ZBM J . Res. Develop., vol. 19, no. 1, pp. 50-59, Jan. 1975.

[14] V. L. Rideout, “One-device memory cells made using the re- cessed-gate FET and four basic masking steps,” IBM Tech. Discl. Bull., vol. 30, pp. 418-425, June 1977.