MOSFET LAB 2

Robert Leonard

I. INTRODUCTION

The purpose of this lab is to become familiar with theprocess flow of a MOSFET. The steps used in making thisdevice are simplified versions of the process that go intofabricating devices with hundreds of steps. In this labwe also obtain data and compare the measured results vsthe theory behind the MOS capacitor and MOSFET. Thedifference between this lab and last lab is the difficultythat arose from photo-lithography steps that had verylittle room for error

II. PROCESSING AND PHYSICAL DEVICECHARACTERIZATION

A. Process Flow diagram

FIG. 1: Cut and clean waferw

FIG. 2: Grow field oxidew

FIG. 3: Photolithography I after photo resist removalw

FIG. 4: Dopant diffusion post etchw

FIG. 5: Photolithography II post etchw

FIG. 6: Grow gate oxidew

FIG. 7: Photolith IIIw

FIG. 8: Photolith IV and Al depositionw

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FIG. 9: Deposit gold, liftoff and back contact

B. Process description

Two batches of wafers were processed in order to op-timize the steps required to fabricate a MOSFET. Thetables in the Appendix are labeled using the scheme # L,were # will correspond to the batch the wafer belongedto and L corresponds to the ID of the wafer.

Cut and clean: Cut 12 1.2cm by 1.2cm wafers using adiamond scribe. Placed wafer in SC-1 50ml:10ml:10mlof H2O:H2O2:NH4OH at 70oC for 10 minutes. HFetch (20:1 Buffered) for 15 seconds, then placed in SC-2,60ml:10ml:10ml ofH2O:H2O2:HCl at 70oC, for 10 min-utes. Wiped surface with khemwipe after cleaning. Mea-sured sheet resistance of another silicon wafer that wasRCA cleaned.Measured the sheet resistance of wafer tobe 40.5 Ω

(used a correction factor in 4.45 in calculation)using the 4-point probe and the thickness of the wafer is650µm giving a resistivity of

ρ = 40.5 ∗ .0650 = 2Ωcm

.

Field oxide growth: Placed wafer along with 5 otherwafers into a tube furnace for wet oxide growth. Thetemperature was set to 1100oC for 21 minutes with .13H2O liquid flow rate. Used filmetrics and measured anoxide thickness of 3916 nm.

FIG. 10: Wafer after FOX growth

Photolith I: Placed wafer on hot plates at 200oC for10 minutes for dehydration. Wiped wafer with khemwipeand blew nitrogen gun across the surface of the wafer.Placed 3 drops of AZ1512 photoresist onto surface ofwafer then immediately spun at 3000rpm for 30 seconds.Put wafer on a hot plate at 90oC-100oC for 90 seconds.Exposed wafer for 7.74 seconds under a lamp emitting

10.98 mJcm2 . Immersed wafer in AZ-400 developer for 1

minute and rinsed with water and dried with nitrogengun.

(a)Large feature after devel-opment

(b)Small feature after devel-opment

The features are a couple of microns smaller than themask. Baked wafer at 120oC for 5 minutes.

(c)Large feature after hard-bake

(d)Small feature after hard-bake

Etched wafer for 15 minutes and 40 seconds to remove

the field oxide(IMAGE). Etch rate of 250 Amin was

determined using a test wafer.

Dopant diffusion Placed wafer in acetone bath andultrasonicated container for 3 minutes,then placed waferin piranha solution (7:3 Sulfuric acid:peroxide) for 30 sec-onds(IMAGE). Rinsed in DI water and dried with nitro-gen gun. The piranha clean was to ensure no photo-resistremained on the wafer. The wafer was then dehydratedon a hot plate for 5 minutes at 300oC. 2 drops of P505dopant were spread over surface of wafer. The waferwas then spun at 5000rpm for 20 seconds. After micro-scope imaging to ensure dopant film was properly appliedthe wafer was baked for 10 minutes at 100oC and thenramped to 130oC for 5 minutes. The dopant was thendriven in using a tube furnace at 1100oC for 1 hour. Atest wafer with no field oxide was also doped in order todetermine the time we needed to etch the dopant film,and to measure the sheet resistance of the devices. Thewafer was etched by submerging in HF (20:1 buffered)for 4 minutes and 30 seconds.

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(e)Large feature on wafer af-ter doping

(f)Small feature on wafer afterdoping

Photolith II Placed wafer on hot plates at 350oC for10 minutes for dehydration. Wiped wafer with khemwipeand blew nitrogen gun across the surface of the wafer.Placed 3 drops of AZ1512 photoresist onto surface ofwafer then immediately spun at 3000rpm for 30 seconds.Put wafer on a hot plate at 90oC-100oC for 90 seconds.Exposed wafer for 7.5 seconds under a lamp emitting11.33 mJ

cm2 . Immersed wafer in AZ-400 developer for 1minute and rinsed with water and dried with nitrogengun.

(g)Large feature on wafer af-ter photolithII

(h)Small feature on wafer af-ter photolithII

Baked wafer at 100oC for 10 minutes.

(i)Large feature on wafer af-ter bake

(j)Small feature on wafer afterbake

Etched wafer for 14 minutes and 30 seconds to removethe field oxide.

(k)Large feature on wafer af-ter dopant etching

(l)Small feature on wafer afterdopant etching

The etch time was reduced due to the fact that a thin

layer of oxide was etched during the etching of the dopantfilm. The photoresist was then lifted off by ultrasonica-tion in acetone, followed by a piranha rinse.

Gate oxide growth Wafer was put in tube furnace fordry oxide growth for 13 minutes and 42 at 1000oC floowedby a 5 minute nitrogen anneal. A wafer was cut andcleaned (piranha and ultrasonication) then placed intothe tube furnace with batch 1. Used filometrics and el-lipsometer to measure gate oxide thickness of 436A.

FIG. 11: Wafer after GOX growth

Photolith III: Placed wafer on hot plates at 350oC for10 minutes for dehydration. Wiped wafer with khemwipeand blew nitrogen gun across the surface of the wafer.Placed 3 drops of AZ1512 photoresist onto surface ofwafer then immediately spun at 3000rpm for 30 seconds.Put wafer on a hot plate at 90oC-100oC for 90 seconds.Exposed wafer for 7.74 seconds under a lamp emitting10.98 mJ

cm2 . Immersed wafer in AZ-400 developer for 1minute and rinsed with water and dried with nitrogengun.

(a)Large feature on wafer af-ter PLIII develop

(b)Small feature on wafer af-ter PLIII develop

Hard baked for 5 minutes.

(c)Large feature on wafer af-ter PLIII hardbake

(d)Small feature on wafer af-ter PLIII hardbake

Etched gate oxide for 3 minutes and 30 seconds. Usedtest wafer to determine time for etching. After etching

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there is a thin 50A oxide layer left over that was measuredusing the ellipsometer. Wafer was then ultrasonicated inacetone and rinsed in pirhana for 2 minutes to removephotoresist.

Photolith IV Placed wafer on hot plates at 350oC for10 minutes for dehydration. Wiped wafer with khemwipeand blew nitrogen gun across the surface of the wafer.Placed 3 drops of AZ1512 photoresist onto surface ofwafer then immediately spun at 3000rpm for 30 seconds.Put wafer on a hot plate at 90oC-100oC for 90 seconds.Exposed wafer for 7.74 seconds under a lamp emitting10.98 mJ

cm2 . Immersed wafer in AZ-400 developer for 1minute and rinsed with water and dried with nitrogengun.

(e)Large feature on wafer af-ter PLIV dev

(f)Small feature on wafer afterPLIV dev

Hard baked for 5 minutes.

(g)Large feature on wafer af-ter PLIV hard bake

(h)Small feature on wafer af-ter PLIV dev

Aluminum deposition Deposited 500A layer of Alonto features and then lifted off with ultrasonication (ace-tone bath) for 3 minutes.

FIG. 12: Wafer after aluminum lift off

Gold deposition Deposited 250A gold layer onto back-side of wafer.

Final contact Coiled copper wire into a spiral andplaced on gold surface of wafer. Coated the wire/goldinterface with silver paint and baked in furnace for 10minutes at 80oC. Apoxy was then applied between thecopper wire and a glass slide so that the wafer could beeasily manipulated. The wafer was then baked again for10 minutes at 90o.

FIG. 13: Final device

Process changes/ things we noticed: During photolithI many of the groups reduced their development timeto 20 seconds. We experiments with the developmenttime by processing 6 wafers in the exact same way except3 were developed for 20 seconds and 3 were developedfor 60 seconds. The development of 20 seconds wouldhave been chosen if we had to redo the experiment dueto some undercutting that was observed after multiplephoto-liths.

During photolith II we noted how hydrophylic thedopant film was. 5 minutes of the wafer sitting out wasenough time for water to condense onto its surface andform a thin layer. This caused us to increase our de-hydration time both before applying dopant, and duringphotolith II in order to ensure there was no water on thewafer. During liftoff of one of our batches we used thesmaller ultrasonicator and noted poorer adhesion thanwith the larger ultrasonication which could be an expla-nation for some of the trends in our data. If we had achance to redo the lab we would experiment with differ-ent methods of ultrasonication to assure good adhesion.We started with 12 total wafers and only ended up with6 that became finished device. The yield of our processcould definitely have been improved by being more care-ful with handling the wafers.

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MOSFET Characterization

The micro-probing station was used to character-ize this device. To insure the device is functioning aimpedance vs theta plot is taken over the MOS capacitorusing an LCR at multiple frequencies. An IV curve ofthe MOS capacitor was then taken. The quality of the n-type regions were measured by taking IV data from eachn-type region individually. The drain current vs drainvoltage curve of the MOSFET is then taken for multiplegate voltages.

CV Characterization

The area of the MOSCAP is .0003cm2. In order to findthe capacitance the impedance at each frequency overa voltage range was taken. Assuming a large parallelresistance the impedance can be found from:

Zim =R2p

R2pωC + 1

ωC

≈ 1

ωC

the capacitance is then

C =1

Zsin(θ)ω

F

cm2

Below the capacitance is plotted for three different fre-quencies:

(a)Capacitance vs Gate voltage at 1MHz

(b)Capacitance vs Gate voltage at 500kHz

(c)Capacitance vs Gate voltage at 100kHz

The range of gate voltages was barley enough to seethe MOSCAP behavior in the three operating regimes.For all data analysis I will be using the 1Mhz data.The oxide thickness can be found by using the expression:

Caccumilation =ε

l

where Caccumilation can be read of the CV curve in ac-cumulation and ε = 3.9εo = 3.9 * 8.854 * 10−14 F

cm =

3.45*10−13 Fm . Looking at the 1Mhz plot at -4V the de-

vice is reaching accumulation and Cacc = 200 nFcm2 result-

ing in an oxide thickness of:

3.9 ∗ 8.854 ∗ 10−14 Fcm

200 ∗ 10−9 Fcm2

giving a calculated oxide thickness of 200A comparedto the measured 460 µm.In order to find the dopant density I look at the capaci-tance in inversion and use the expression:

C

Co=

1√1 +

2ε2oxVqNAεsd2

(Sze 5.16) which can be rearranged to:

NA =2ε2oxV

(C2

o

C2 − 1)qεsd2

where Co is the capacitance in accumulation (ie ca-pacitance of the oxide), C is the capacitance valueat a certain point in inversion, and d is the ox-ide thickness. Solving for NA using εo = 3.9 ∗8.854 ∗ 10−14 F

cm , V = -3V, Co = 200nF, C =

110nF (inversion),εs = 11.68 ∗ 8.854 ∗ 10−14 Fcm , d =

200*10−8cm gives: NA = 4.682 ∗ 1017 atoms

cm−3. If in-

stead I used the measured oxide thickness (d = 460A)

NA = 8.85 ∗ 1016 atoms

cm−3

The maximum depletion region can me found using theexpression:

Wm = 2

√εskT ln(NA

ni)

q2NA

(Sze 5.11b) where ni ≈ 1010 for silicon, T = 300K and k= 1.38*10−23 J

K . Plugging in the values gives a maximum

depletion width of: Wmax = 5.01µm .

The thresh hold voltage can be found using:

VT =qNAWm

Co+

2kT

qln(

NAni

)

(Sze 5.10 and 5.17) plugging in the values listed above:

VT = −2.79V , I added the minus sign because the equa-

tion used does not take into account the sign of thresh

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hold voltage. Looking at the 1Mhz capacitance vs gatevoltage the thresh hold voltage on the graph reads around-2.8V. The capacitance of the MOSCAP can be drawn astwo capacitors in series Cox and Cs where Cs is the ca-pacitance of the semiconductor. At equilibrium:

1

Ceq=

1

Cox+

1

Cdep=

1

Cox+W

εs

resulting in

W = (1

Ceq− 1

Cox)εs

Where Ceq is the capacitance at zero volts on the gate.I arrive at W = .39 *10−7µm. Now (Sze 5.9)

Ψs =qNAW

2

2εs= .104V

IV Characterization

The IV data only spans -2V to 4V for two reasons.Firstly this voltage range was sufficient for the impedancedata so we assumed it would work for the IV data. Lastlybeyond the extremes of the voltage the SMU was hit-ting a compliance voltage of 1mA and we didn’t want tobreak the device by applying more than 1mA across thechannel. Below is the IDvs.VD data for multiple gatevoltages:

FIG. 14: IDvs.VG for multiple gate voltages

The saturation voltage is never reached either becausethe drain voltage was never turned high enough or thereis some small parallel resistance the leaks current. Thelinear channel conductance was taken to be the slope ofthe IDvs.VG from 0V to 1V.

FIG. 15: IDvs.VD in the linear regime

FIG. 16: IDvs.VG in the linear regime

The channel conductance of 5 different gate voltagesin the linear regime is listed below.

Vg(V) gm(Ω−1)

0 .00031 .0003-1 .00022 .0004-2 .0002

Saturation channel conductance could not be found fromthe data we have collected due to not going to a highenough drain voltage. There is possibly a shunting pathin the channel that has a small impedance because at 2Vthe device is in strong inversion so any small impedanceis due to some parallel resistance. In the ideal MOSFETthe channel conductance in this region should be zero.ID vs VG in ”saturation” is plotted below.

FIG. 17: IDvs.VG in the ”saturation” regime

Making a linear fit to the IDvs.VG in the ”saturation”regime I found gm = 1*10−4Ω−1 with an R2 =.90 at VD

7

= 4 and gmΩ−1 = 9*10−5 with an R2 = .91 at VD = 3.5. The drain current in saturation is given by:

IDsat=ZµCo

2L(Vg − VT )2

(Sze 5.41)rearrange to find:

VG =√IDsat

2L

ZµCo+ VT

where L is the oxide thickness, Co is the capacitance inthe oxide, Z is the charge of the carriers and µ is the mo-bility of the carriers (electrons in this case). The thresh

hold voltage is therefore y-intercept of the VG vs√IDsat

.I attempted to plot VG vs IDsat

but due to not reachingsaturation the thresh hold voltage that is found doesn’tcome close to what is found form the CV data and isnot accurate. A drain voltage of 4V was used and thecalculated y-intercept is -13V.

FIG. 18: VG vs√

IDsat in the ”saturation” regime

Using the thresh hold voltage calculated from the CVdata (VT = 2.79V) at ID = 6.42 ∗ 10−4 and VG = -1Vthen:

µn =ZCo

2LIDsat

(VG − VT )2 = 1008cm2

V − s

As the depletion region gets larger the electron mobilityshould increase until the depletion region reaches a max-imum value and the electron mobility becomes constant.

Appendices

FIG. 19: Field oxide data for both batches of wafers. Mea-sured using filometrics.

FIG. 20: Sheet resistance of batched