MOSFET Carrier Velocity in the Quasi-Ballistic Regime:

Insights for Nanoscale MOSFET Design

Nuo Xu and Tsu-Jae King LiuEECS Department

University of California at Berkeley

IMPACT Project Webinar

October 6, 2010

Outline

• Introduction

• Predictive Modeling of Strained Nano -scale MOSFETs

• Study of Carrier Transport in Multi-Gate FETs

• Summary

MOSFET Scaling Challenges• Improvements in IC performance and

cost have been enabled by the steady miniaturization of the transistor:

Better Performance/Cost

Market Growth

Transistor Scaling

Investment

• Power density now limits transistor scaling.� Advanced materials and structures that improve

performance and/or reduce variability are needed to facilitate voltage (V DD) scaling. 3

Po

we

r D

en

sity

(W

/cm

2)

1E-05

1E-04

1E-03

1E-02

1E-01

1E+00

1E+01

1E+02

1E+03

0.01 0.1 1

Gate Length (μm)

Passive Power Density

Active Power Density

Source: B. Meyerson (IBM)

Semico Conf., January 2004

Power Density vs. CMOS Scaling

MOSFET Basics• Current flowing between the Source and Drain is

controlled by the voltage applied to the Gate.

log I D

VG

IOFF

VDD

ION

Electron Energy Band Profile

incr

easi

ng E

distance

n(E) ∝∝∝∝ exp (-E/kT)

Substrate

Gate

Source Drain

• The greater the capacitive coupling between the Gat e and the channel, the better control the gate has over the channel po tential.

� higher I ON/IOFF for a given V DD, or lower V DD to achieve target I ON/IOFF

� reduced short-channel effect (SCE) & drain-induced barrier lowering (DIBL)� less VT variation due to random dopant fluctuations (RDF), gate line-edge-roughness (LER)

VTVT

improved gate control

4

Performance Boosters

P. Packan et al., IEDM Technical Digest, pp. 659-662, 2009

• High-permittivity gate dielectric and metal gate el ectrodes for improved capacitive coupling between gate and chann el

• Strained channel regions for carrier mobility enhan cement

Cross-sectional TEM views of Intel’s 32nm CMOS devi ces

5

planar bulk structure

G

S D

Si

high-k gate dielectric

metallic gate

strained Si

Lg (nm): 50 40 30 20 10

MOSFET Scaling Scenario

multi-gate structureG

S DSi

G

• Advanced MOSFET structures are anticipated to be needed to scale L g below ~20nm.

6

Why Multi-Gate FETs ?• SCE and DIBL are suppressed by using an adequately

thin body, so channel/body doping can be eliminated .� higher I ON due to higher carrier mobility & improved gate cont rol,

reduced RDF-induced V T variation

Fin Height h Si

Source

DrainGate

Lg

Fin Width wSi

7

J. Fossum et al., IEDM Tech. Dig., pp. 613-616, 2004

Body dimensions needed to suppress SCE

Tri-Gate :

FinFET:

Carrier Transport in a MOSFETWhat limits I ON?

Drift + Diffusion

At low field: Mobility

At high field:

Saturation

Velocity

Leff >> λQuasi-Ballistic Transport

Injection Velocity

(at source end)

Leff ~ λ (20nm for Si)

Source Drain

CESL

Lg

l

Channel Potential

8

Outline

• Introduction

• Predictive Modeling of Strained Nano -scale MOSFETs

– Acknowledgements: Xin Sun, Lynn Wang and Andrew Neureuther

• Study of Carrier Transport in Multi-Gate FETs

• Summary

N. Xu et al., SISPAD 2008

Quasi-Ballistic Transport Model

Critical Length:

Backscattering Rate:

Total Current:

A. Rahman et al., IEEE-TED Vol. 49, p.481, 2002

��= �����������

������

× ������−1 ��������

�������

��=

��

��+ λ0

Mean Free Path: ��= �2��

����

������

��� ℑ0

2(����)

ℑ1′ (����) × ℑ1

2

(����)

��=�����2�����

��������

�3

2

2ℏ2�1 − ���[ℑ1

2

�����1�− ℑ12

�����2�]

10

Modeling of Effective Channel Stress

1. Analytical model for stress distribution is calibrated using TCAD simulations

• l is dependent on drain bias. � Effective channel stress is

dependent on drain bias.

2. Average stress within the critical length region is calculated.

•Stress is modeled by a Gaussian function:

11

Modeling of Strain Effects

Energy QuantizationComparison of analytical model vs.

Poisson-Schrodinger solution

(The 5 lowest conduction sub-bands hold 99% of the electrons.)

MobilityComparison of analytical model vs.

piezoresistance model and exp. data

Effective Mass

• Analytical model accounts for carrier redistribution and reduced inter-valley scattering.

12

Compact Modeling Flow

Average stress in critical-length region

Energy sub-band shifts,Effective mass changes

Calculate I D

Drain bias

Stress profiles

Gate bias Charge density,Surface Fermi level,Sub-band energies

Low-field mobilityBackscattering rate

Critical Length

Self-consistent solution

13

Model Verification

0.0 0.2 0.4 0.6 0.8 1.0 1.21E-8

1E-7

1E-6

1E-5

1E-4

1E-3

Vds = 0.05 V

Id (

A)

Vgs (V)

Exp. Data in [11] Model

Vds = 1.0 V

Fitting Parameters:Gate Control Para. 0.85Drain Control Para. 0.06Low-field Mobility 250 cm 2/V.sSeries Resistance 180 Ohm.um

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.40

400

800

1200

1600

2000

Exp. Data in [11] Model

Id (

uA/u

m)

Vds (V)

1.2V

1.1V

1.0V

0.9V

0.8V

0.7V

0.6V

0.5V

0.4V

40nm CESL-strained nMOSFETS. Mayuzumi et al., IEDM Tech. Dig., p.293, 2007

Output Characteristics Transfer Characteristics

• A good match to measured I-V data is achieved.Only 4 fitting parameters are needed.

14

Channel-Length Dependence

• The model well predicts the L g dependence of current enhancement

[11] S. Mayuzumi et al., IEDM Tech. Dig. , p.293, 2007

20 40 60 80 1000

5

10

15

20

25

30

35

40

ModelPrediction

Vds = 1.0V

Id G

ain

(%

)

Channel Length (nm)

Vds = 0.05V

Vgs - Vth = 0.7VExpr. Data from [11]

15

Future -Generation Devices

15 20 25 30 35 40 45 50

12

15

18

Poly gateMetal gate

Work in [11]

Channel Length (nm)

Inje

ctio

n V

eloc

ity (

106

cm/s

)

Ballistic velocity w/o strain Injection velocity w/o strain Injection velocity with strain

15 20 25 30 35 40 45 500.4

0.5

0.6

0.7

0.8

0.9

1.0

Work in [11]

Poly gate

Metal gate

Channel Length (nm)

Intr

insi

c D

elay

(ps

)

W/O Strain With Strain ITRS

HP Tech Node 90nm 68nm 52nm 40nm

Lg (nm) 32 25 20 16

Tinv(nm) 1.93 1.84 1.04 0.82

Body Doping (cm-3)

3.3e18 4.8e18 4.1e18 6.6e18

S/D Series Resistance (Ohm.um)

180 200 200 180

Vdd (V) 1.1 1.1 1 1

��=

������− ����ℎ +����������

������������

�3 − ���������

4− ����ℎ

����

��������

Injection Velocity vs. Channel Length

Intrinsic Delay vs. Channel Length

• Nanoscale MOSFETs will operate far below the ballistic limit.

• The benefit of stress diminishes with gate-length scaling.

16

Outline

• Introduction

• Predictive Modeling of Strained Nano-scale MOSFETs

• Study of Carrier Transport in Multi-Gate FETs

– Acknowledgements: Xin Sun; Wade Xiong and Rinn Cleavelin (TI)

• Summary

N. Xu et al., IEDM 2010

MuGFET Design Variations

a) Uniaxial Stress(CESL)

b) Biaxial Stress c) Transverse Stress(Metal Gate)

PolyCESL

Si

Poly

SOI

Si

Metal

Gate

Si

Poly

y

Z(100)

x <110> or <100>

Sxx : Szz = 1 : -1 Sxx : Syy = 1 : 1 Syy : Szz = 1 : 1Only transverse direction Compressive

NMOS: TensilePMOS: Compressive

NMOS: TensilePMOS: Tens. & Comp.

Fin Orientations Stress Configurations

[110]

[001]

[110]

S D

[110]

S

D

[010][100]

A:

B:

• Fin aspect ratio, orientation, and stress configura tion should be co-optimized for peak performance.

18

Inducing Strain in MuGFETs

0 5 10 15 20 25 30 350

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18strain vs micrometer knob

micrometer knob

stra

in

bi-axile tensile

bi-axile compressive

0.11%

Micrometer Knob

Str

ain

[%]

20 30 40 50 60-300M

-200M

-100M

0

100M

200M

300M

Str

ess

(Pa)

Channel Length (nm)

Sxx sidewall Sxx top Syy sidewall Syy top Szz sidewall Szz top

HSi

= 58nm

WSi = 20nm

20nm-Thick CESLInitial Stress: 2GPa

Contact Etch Stop Liner (CESL)TCAD simulations

Sxx

Szz

Stress in CESL-FinFET

K. Uchida et al., IEDM Tech. Dig., 2004

Biaxial wafer bending

19

Simulation Approach• To simulate the effect of transverse field and stre ss on carrier mobility,

a 2-D Poisson-Schrödinger solver was developed to c alculate the change in energy-band structure, accounting for qua ntum confinement.– For electrons, the effective mass approximation (EMA) is used, and non-

parabolic E-k and stress effect on band structure are taken into account. – For holes, the 6×6 k•p approach is used, and the Pikus-Bir Hamiltonian is

adopted for modeling stress effects.

• The Kubo-Greenwood formula is used to calculate low -field channel mobility, considering phonon and surface-roughness scattering.

From bulkinversion to surface inversion

20

Carrier density profile with increasing gate bias:

Model Verification

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.0

0.1

0.2

0.3

0.4

0.5

n-FinFET

Gat

e C

apac

itanc

e (p

F)

Gate Bias (V)

WSi=35nm

WSi=20nm

Simulation

p-FinFET

HSi =58nm

Lg =10um

20 Fins

f = 100KHz

Electron Phonon Hole PhononDac (eV)

14.7 8.6

DtK(eV/m)

LO (g) TO (f) LA (f) 1.32e111.1e11 0.2e11 0.2e11

(meV)64 60 48 61.2

Surface Roughness(100) top (100) sidewall (110) sidewall

∆ (Å) 4.8(e) 3.6(h) 6.6(e) 4.2(h) 5.7(e) 5.4(h)L(Å) 10(e) 26(h) 10(e) 22(h) 10(e) 28(h)

Electron Deform. Potential Hole Deform. Potential9.2 0.53 av (eV) 2.10.87 0.0189 b (eV) -2.33

7 -0.809 d (eV) -4.75

Ξu (eV)

Ξd (eV)

Ξu’ (eV)

∆bs (eV)

η

κ

ℏ��

Calibrated Deformation and Scattering Parameters

21

Measured vs. simulated MuGFET Gate Capacitance

• A good match to measured C-V data is achieved.

MuGFET Effective Mobility• Good agreement is seen between experiment and simul ation:

3x1012 6x1012 9x1012 1.2x1013100

150

200

250

300

350

400<100> Fin

n-MuGFET(100) Wafer

Ele

ctro

n M

obili

ty (

cm2 /V

s)

Ninv

(cm -2)

FinFET <100> WSi=20nm

FinFET <110> WSi=35nm

FinFET <110> WSi=20nm

Simulated FinFET Simulated TriGate

<110> Fin

3x1012 6x1012 9x1012 1.2x1013

100

150

200

250

300<110> Fin

FinFET <110> WSi=20nm

FinFET <110> WSi=35nm

FinFET <100> WSi=20nm

Simulated FinFET Simulated TriGate

p-MuGFET(100) Wafer

Hol

e M

obili

ty (

cm2 /V

s)

Pinv

(cm-2)

<100> Fin

Electron Mobility Hole Mobility

• In FinFET: sidewall surfaces dominate• In Tri-Gate FET: top surface dominates, and is of h igher quality

22

Mobility Change with Biaxial Stress

4.0x1012 6.0x1012 8.0x1012 1.0x1013 1.2x10130.00

0.03

0.06

0.09

0.12

0.15

0.18

0.21

Ele

ctro

n M

obili

ty C

hang

e (

∆µ/µ

∆µ/µ

∆µ/µ

∆µ/µ

)

Ninv

(cm -2)

<110> Fin<100> Fin Simulation

WSi=20nm H

Si=58nm

Biaxial Tensile BendingIn-plane-strain 0.11%

4.0x1012 6.0x1012 8.0x1012 1.0x1013 1.2x1013-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

WSi=20nm H

Si=58nm

Biaxial Tensile BendingIn-plane-strain 0.11%

Pinv

(cm -2)

Hol

e M

obili

ty C

hang

e (

∆µ/µ

∆µ/µ

∆µ/µ

∆µ/µ

)

<100> Fin <110> Fin Simulation

23

FinFET Electron Mobility FinFET Hole Mobility

• NMOS: Enhancement decreases due to carrier redistri bution.• PMOS: Reduction in enhancement is less remarkable.

Comparison of Stress ConfigurationsFinFET Electron Mobility

0 200 400 600 800 1000 1200 14000

20

40

60

80

100

120

140

Ninv

= 9x1012cm -2

HSi = 58nm, W

Si = 20nm

<110> CESL <110> Bi. Tens. <110> Gate <100> CESL <100> Bi. Tens. <100> Gate

Ele

ctro

n M

obili

ty C

hang

e (%

)

Stress (MPa)

0.000 0.025 0.050 0.075 0.100

2.0x1013

4.0x1013

6.0x1013

8.0x1013

1.0x10142.0x1013

4.0x1013

6.0x1013

8.0x1013

1.0x10140.000 0.025 0.050 0.075 0.100

Sca

tterin

g R

ates

(S

-1)

Energy (eV)

unstrained Biaxial Tens. CESL Gate

unstrained: 0.325m0

CESL: 0.260m0

<100> Fin1400MPa

unstrained Biaxial Tens. CESL Gate

<110> Fin1400MPa

unstrained: 0.448m0

CESL: 0.166m0

24

• µn is more sensitive to stress for a <110>-oriented fin.

• CESL provides the most enhancement, via a reduction in effective mass.

0 200 400 600 800 1000 1200 1400

-20

0

20

40

60

80

100

120

140

Hol

e M

obili

ty C

hang

e (%

)

Stress (MPa)

<100> CESL <100> Bi. Comp. <100> Gate <100> Bi. Tens. <110> CESL <110> Gate <110> Bi. Comp. <110> Bi. Tens.

Pinv

= 1x1013cm-2

HSi= 58nm, W

Si= 20nm

0.000 0.025 0.050 0.075 0.100

3.0x1013

6.0x1013

9.0x1013

1.2x1014

1.5x1014

1.8x1014

3.0x1013

6.0x1013

9.0x1013

1.2x1014

1.5x1014

1.8x10140.000 0.025 0.050 0.075 0.100

<100> Fin1400MPa

Energy (eV)

unstrained Biaxial Tens. CESL Gate

unstrained: 0.793m0

CESL: 0.466m0

unstrained: 0.392m0

CESL: 0.149m0

Sca

tterin

g R

ates

(S

-1)

unstrained Biaxial Tens. CESL Gate

<110> Fin1400MPa

25

Comparison of Stress ConfigurationsFinFET Hole Mobility

• µp is more sensitive to stress for a <110>-oriented fin.

• CESL provides the most enhancement, via reductions in effective mass and scattering rate.

FinFET vs. Tri-Gate FET Comparison

0 200 400 600 800 1000 1200 1400100

200

300

400

Ele

ctro

n M

obili

ty (

cm2 /V

s)

Stress (MPa)

<100> CESL Tensile <100> Biaxial Tensile <110> CESL Tensile <110> Biaxial Tensile

Open: FinFETFilled: Tri-Gate

Ninv

= 9x1012cm -2

0 200 400 600 800 1000 1200 1400100

200

300

400

500Open: FinFETFilled: Tri-Gate

Hol

e M

obili

ty (

cm2 /V

s)

Stress (MPa)

CESL Compressive Biaxial Compressive Biaxial Tensile

<110> Fin

Pinv

=1x1013cm -2

• NMOS: <100> Tri-Gate FET is the best• PMOS: <110> Tri-Gate FET is the best for high stres s levels

>600MPa26

Electron Mobility Hole Mobility

Simulated Carrier Thermal Velocity(FinFET)

1012 10130.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

CESL <100> pFET

CESL <110> pFET

CESL <100> nFET

Car

rier

The

rmal

Vel

ocity

(x1

07 c

m/s

)

Inversion Charge Concentration (cm -2)

nFET <100> nFET <110> pFET <100> pFET <110>

T = 300K

CESL <110> nFET

HSi=58nm, W

Si=20nm

5x1012

27

• CESL-induced stress can provide for large enhanceme nts

Extraction of Short-Channel MuGFETMobility and Injection Velocity

28

� Linear region mobility extraction-Y-function approach → Vth and RS/D- split-CV measurement → Leff

→ Impact of ballistic transport on µ

�ON-state injection velocity extraction- DIBL measurement → dV th

- Inversion charge:

- Injection velocity:

→ Dependence of v inj on µ

��������′

= � Cgsd dVgs’

������′ +������ℎ

0

vinj=Ion/WQ’inv

V ’gs = Vgs – IdsRs ;

Extracted Short-Channel FinFET Mobility

20 40 60 80 100100

120

140

160

180

200

220

240

App

aren

t Ele

ctro

n M

obili

ty (

cm2 /V

.s)

Ninv

=1x1013cm -2

HSi=58nm, W

Si=20nm

T =300K

Effective Channel Length (nm)

Extracted <100> Fin Extracted <110> Fin Calculated <100> Fin Calculated <110> Fin

10 20 40 60 80 100

80

100

120

140

160

180

200

220

App

aren

t Hol

e M

obili

ty (

cm2 /V

.s)

Effective Channel Length (nm)

Extracted <110> Fin Extracted <100> Fin Calculated <110> Fin Calculated <100> Fin

Pinv

=1x1013cm-2

HSi=58nm, W

Si=20nm

T =300K

10

• Degradation seen with decreasing L eff, due to ballistic transport• Extracted values are much lower than simulated, due to strong

Coulomb scattering from defects.29

Electron Mobility Hole Mobility

Extracted Short-Channel FinFET Injection Velocity

1.6 2.0 2.4 2.8 3.2

0.51

0.54

0.57

0.60

vinj

/vbal

= 47.71%v

inj/v

bal= 57.68% L

eff= 56.6nm

Ele

ctro

n In

ject

ion

Vel

ocity

(10

7 cm/s

)

µµµµeff

/Leff

(107 cm/V.s)

Extracted <100> Fin Extracted <110> Fin

T = 300KH

Si= 58nm, W

Si= 20nm

Ninv

= 1x1013 cm -2

Vds

= 1.2V

Leff

= 56.6nm

1.0 1.5 2.0 2.5 3.00.35

0.40

0.45

0.50

0.55

vinj

/vbal

= 54.35%

µµµµeff

/Leff

(107 cm/V.s)

Hol

e In

ject

ion

Vel

ocity

(10

7 cm/s

)

T = 300KH

Si= 58nm, W

Si= 20nm

Pinv

= 1x1013 cm-2

Vds

= 1.5V

Extracted <110> Fin Extracted <100> Fin

Leff

= 56.6nm

Leff

= 56.6nm

vinj

/vbal

= 40.16%

• Injection velocity depends largely on apparent mobi lity. (40% to 50% ballistic, similar as for bulk MOSFETs)

30

NMOS PMOS

Outline

• Introduction

• Predictive Modeling of Strained Nano -scale MOSFETs

• Study of Carrier Transport in Multi-Gate FETs

• Summary

Summary

• ION in nano-scale MOSFETs is limited by the carrier injection velocity, which can be predicted by a physically-based compact model.� Enables projections of performance/delay at future nodes

• To maximize MuGFET I ON, fin orientation and aspect ratio should be co-optimized for the chosen stresso r.- CESL will be the most effective stressor for MuGFE Ts.

• Defect-induced Coulomb scattering has a strong impact on apparent mobility and injection velocity.� A new challenge to realizing the full benefit of strain

32

Acknowledgements

• IMPACT corporate sponsors

• UC Discovery Grants Program

• Texas Instruments Inc. for MuGFET test chips

33