MOS Model 11
description
Transcript of MOS Model 11
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MOS Model 11MOS Model 11
R. van Langevelde, A.J. Scholten
and D.B.M. Klaassen
Philips Research, The Netherlands
MOS-AK Group Meeting’02
XFAB, Erfurt
October 21, 2002
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suitable for digital, analog and RF
suitable for modern/future CMOS processes
physics based
simulation time comparable to MM9
number of parameters comparable to MM9
simple parameter extraction
Introduction: MOS Model 11
Goals for MOS Model 11 (MM11):
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Introduction: MOS Model 11
surface-potential-based model
accurate transition weak strong inversion
symmetrical
distortion
accurate description of third-order derivatives (i.e. 3I/V3)
Model developed for accurate distortion analysis in circuit design:
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Introduction: MOS Model 11
mobility reduction
bias-dependent series resistance
velocity saturation
conductance effects (CLM, DIBL, etc.)
gate leakage current
gate-induced drain leakage
gate depletion
quantum-mechanical effects
bias-dependent overlap capacitances
implemented physical effects:
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Introduction: availability of MM11
public domain• source code in C (including solver)
• documentation of model and parameter extraction
• http://www.semiconductors.philips.com/Philips_Models
circuit simulators• Pstar (Philips in-house)
• Spectre (Cadence)
• Hspice (Avant!)
• ADS (Agilent)
• Eldo (Mentor Graphics)
• HSIM (NASSDA)
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Introduction: structure of MOS Model 11
Junction diodes modelled by
JUNCAP-modelGeometry Scaling
Temperature Scaling
Model Equations
W, L
T
DS
GS
SB
V
V
V
Noise
Charges
Currents
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MOS Model 11: outline
Introduction
DC-Model
AC-Model
Noise Model
Model Parameters & Extraction
Summary
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DC-Model: VT -based model
TV
interpolation needed between subthreshold and superthreshold (e.g. BSIM4 and MM9)
Smoothing function
T
TGSDS exp
m
VVI
VT -based model:
2TGSDS VVI
0 1 210 -10
10 -9
10 -8
10 -7
10 -6
10 -5
10 -4
10 -3
VSB = 0 V
VDS = 1 V
VVGSGS (V) (V)
II DS
DS
(A)
(A
)
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DC-Model: surface-potential-based model
Idrift = f(VGB ,s0 ,sL)
Idiff = g(VGB ,s0 ,sL)
IDS = Idrift + Idiff
s-based model:
single equation for whole operation range:
0 1 210 -11
10 -10
10 -9
10 -8
10 -7
10 -6
10 -5
10 -4
Idiff
I drift
IDS = Idrift + Idiff
VSB = 0 V
VDS = 1 V
VGS (V)
II DS
DS
(A)
(A
)
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DC-Model: surface potential s
Quasi-Fermi Potential V:
Substrate
VGB
Gate
EV
Oxide
EC
Ei EF
Fq
sq
V
V = VSB at Source
V = VDB at Drain
0
1
2
0 1 2 3
V GB - V FB (V)
s
(V)
t ox = 3.2 nm
N A= 2*1017 cm-3V = 1 V
V = 0 V
s=2F+V
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11 T
s
T
s
T
B
TTs
2
sFBGB
eee
k
VVV
O
-0.4
0
0.4
0.8
1.2
-1 0 1 2V GB - V FB (V)
s
(V)
V = 0 V-0.4
0
0.4
0.8
1.2
-1 0 1 2V GB - V FB (V)
s
(V)
V = 0 V
AccumulationApproximation
iterative solution
time consuming
approximation used:
s = s(VGB ,V )
(Solid-State Electron. 44, 2000)-0.4
0
0.4
0.8
1.2
-1 0 1 2V GB - V FB (V)
s
(V)
Weak-inversionApproximation
V = 0 V-0.4
0
0.4
0.8
1.2
-1 0 1 2V GB - V FB (V)
s
(V) Strong-inversion
Approximation
V = 0 V
DC-Model: surface potential approximation
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DC-Model: surface-potential-based model
Description of ideal long-channel MOSFET
For real devices several physical effects have to be taken into account:mobility effects
conductance effects
Special attention to:distortion
drain-source symmetry
new models}
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DC-Model: distortion behavior
• 2nd-order distortion: cancels out in balanced circuit
• 3rd-order distortion: limits dynamic range
I OU
T
VIN
12
34
Harmonic
Am
plit
ud
e accurate description of 3rd-order derivatives
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DC-Model: gate-bias induced distortion
Gate-bias induced distortion for NMOS, W/L=10/1m
1 2 3 4
VGS (V)
10 -11
10 -10
10 -9
10 -8
10 -7
10 -6
10 -5
Har
mon
ic A
mpl
itud
e (A
)
VSB
= 0 V
VDS
= 0.1 V
HD2
HD3
HD1
VT
Mobility Reductionand
Series-Resistance
Symbols Measurements
Lines MOS Model 11
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DC-Model: conductance modeling
VelocitySaturation
Static Feedbackand
Self-Heating
Weak-Avalanche
Drain-bias induced distortion for NMOS W/L=10/1m
0 1 2 3 4
VDS (V)
10 -8
10 -7
10 -6
10 -5
10 -4
10 -3H
arm
onic
Am
plit
ude
(A)
VSB = 0 VVGS = 2.5 V
HD2
HD3
HD1
ChannelLength
Modulation
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-60
-50
-40
-30
-20
-10
0 1 2 3V GS (V)
Har
mo
nic
Po
wer
(dB
m)
HD2
HD3
MM11Measurements
MM9BSIM3v3-60
-50
-40
-30
-20
-10
0 1 2 3V GS (V)
Har
mo
nic
Po
wer
(d
Bm
)
HD2
HD3
MM11Measurements
MM9BSIM3v3
RF-distortion determined by DC model
f=16 MHz f=1 GHzNMOS, W/L=160/0.35m, VDS=3.3 V, PIN=-5dBm
DC-Model: RF-distortion modeling
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Outline: DC-Model
VT vs. s-based models
Distortion modeling
Symmetry
Gate leakage current
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ideal current equation velocity saturation DIBL/static feedback smoothing function (linear/saturation region)
Care has to be taken with the implementation of:
DC-Model : drain-source symmetry
Symmetry w.r.t. source and drain at VDS= 0
MOS models developed for VDS 0 for VDS < 0, source & drain are interchanged
In order to preserve symmetry:IDS( VGS , VDS , VSB ) = -IDS( VGD , VSD , VDB )
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DC-Model : drain-source symmetry
Not valid for threshold-voltage-based models
10
100
-0.6 -0.3 0 0.3 0.6
V DS (V)
gd
s
(mA
/V)
MOS Model 9
10
100
-0.6 -0.3 0 0.3 0.6
V DS (V)
dg
ds /d
VD
S (
mA
/V2 )
MOS Model 9
IDS( VGS , VDS , VSB ) = -IDS( VGD , VSD , VDB )
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DC-Model : drain-source symmetry
10
100
-0.6 -0.3 0 0.3 0.6
V DS (V)
gd
s
(mA
/V)
MOS Model 9
MOS Model 11
10
100
-0.6 -0.3 0 0.3 0.6
V DS (V)
dg
ds /d
VD
S (
mA
/V2 )
MOS Model 9
MOS Model 11
Care has to be taken to preserve symmetry
IDS( VGS , VDS , VSB ) = -IDS( VGD , VSD , VDB )
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Outline: DC-Model
VT vs. s-based models
Distortion modeling
Symmetry
Gate leakage current
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Gate
Source Drain
bulk
VGSpotentialpotential
DC-Model: gate leakage current
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Gate
Source Drain
bulk
VGS
{
tox JG
GSOG VBJJ exp oxox
Ott
Jexp
2
1where:
Simplified relation:
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
0 0.5 1 1.5
V GS (V)
JG
(A
/cm
2)
MeasurementModel
t ox = 2.2nm
t ox = 1.7nm
t ox = 1.4nm
NMOS, VDS=0V
DC-Model: gate leakage current
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NMOS (in inversion):
oxinvG VPQJ
Gate EV
OxideOxide
EC
Ei EF
Substrate
oxVq
-
Bq
Gate current density:
tunnelling probability
parameters
oxVinvoxG eQVI OB
OI
Approximation (at VDS=0 V):
electron charge density
DC-Model: gate leakage model
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1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
-1.5 -1 -0.5 0 0.5 1 1.5
V GS (V)
I G
(A)
MeasurementsMM11
I GS + I GD
NMOS, tox=2 nm, Area=6 m2
VGS>0
SS
DD
IIGG
IGDIGS
DC-Model: gate current components
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1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
-1.5 -1 -0.5 0 0.5 1 1.5
V GS (V)
I G
(A
)
Measurements
MM11
I GS + I GD
I GOV
VGS>0
SS
DD
IIGG
NMOS, tox=2 nm, Area=6 m2
IGOV
IGDIGS
DC-Model: gate current components
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1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
-1.5 -1 -0.5 0 0.5 1 1.5
V GS (V)
I G
(A)
MeasurementsMM11
I GS + I GD
I GOV
NMOS, tox=2 nm, Area=6 m2SS
DD
IIGG
IGDIGS
IGOV
VGS<0
DC-Model: gate current components
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1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
-1.5 -1 -0.5 0 0.5 1 1.5
V GS (V)
I G
(A)
MeasurementsMM11
I GB I GS + I GD
I GOV
NMOS, tox=2 nm, Area=6 m2
VGS<<0
SS
DD
IIGG
IGDIGS IGB
IGOV
DC-Model: gate current components
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1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
-1.5 -1 -0.5 0 0.5 1 1.5
V GS (V)
I G
(A)
MeasurementsMM11
I G
NMOS, tox=2 nm, Area=6 m2
VGS<<0
SS
DD
IIGG
IGDIGS IGB
IGOV
DC-Model: gate current components
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1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
-1.5 -1 -0.5 0 0.5 1 1.5
V GS (V)
I G
(A)
VDS = 1.5 V
Measurements MM11
VDS = 0 V
NMOS, tox=2 nm, Area=6 m2
determined by overlap region
determined by
intrinsic region
DC-Model: gate leakage model
L
xVeQVI dinvoxOGC
oxOBI
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MOS Model 11: outline
Introduction
DC-Model
AC-Model
Noise Model
Model Parameters & Extraction
Summary
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AC-Model: intrinsic charges
- --
+ + + + + +
n+
p
n+
- - - - - - - -
+ + +
n+
--
- --
- -- -
- -- -- -
- -- -
- -
-
L
xQWQ0
depB d
L
xQL
xWQ
0
invD d
L
xQL
xWQ
0
invS d1 BSDG QQQQ
Intrinsic Capacitances::
ji
V
Q
jiV
Q
Cfor
for
j
i
j
i
ij
where i, j =G, S, D or B
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0
0.4
0.8
1.2
-3 -2 -1 0 1 2 3
V GS (V)C
GG
(n
F)
Measurements
MOS Model 11tox=3.6nm
gate depletion effect
0
0.4
0.8
1.2
-3 -2 -1 0 1 2 3
V GS (V)C
GG
(n
F)
Measurements
MOS Model 11tox=3.6nm
quantum-mechanicaleffects
0
0.4
0.8
1.2
-3 -2 -1 0 1 2 3
V GS (V)C
GG
(n
F)
Measurements
MOS Model 11tox=3.2nm
charge model includes:
accumulation
PMOS, VDS=0 V,
W/L=80*612/2.5m
AC-Model: input capacitance CGG
physical tox=3.2nm
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AC-Model: symmetry and reciprocity of capacitances
VDS=0V
CBD-CBS vs. VG
symmetry (CiD=CiS) reciprocity (Cij=Cji)
CDS-CSD vs. VG
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AC-Model: bias-dependent overlap capacitance
- - -++++++
- - -
n+ p
n+
Source
Gate
Bulk
n+
n+
Source/DrainTwo-terminal MOS-capacitance:
accumulation and depletion region includedintroducing two parameters: kov and VFBov
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AC-Model: bias-dependent overlap capacitance
0
50
100
150
-2 -1 0 1 2
V GS (V)
CD
G
(p
F)
MeasurementsMOS Model 11
intrinsic
C DG
total C DG
overlap capacitance
PMOS , VDS=0 V , W/L=152*612/0.18m
Short-channel MOSFET, 0.18m CMOS
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MOS Model 11: outline
Introduction
DC-Model
AC-Model
Noise Model
Model Parameters & Extraction
Summary
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1/f noise
thermal noise
induced gate noise
Noise Model: noise types in MOS transistor
induced induced gate noisegate noise
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unified 1/f noise model: BSIM4, MM9 & MM11 bias dependence verified geometrical scaling verified
Noise Model: 1/f-noise
/Hz)(V
WL
WL
S
2
RR
Vgate
10-11
10-10
10-9
10-8
0 1 2 3 4
Vgs [Volt]
NMOS
0 1 2 3 4
Vgs [Volt]
PMOS
model
(Kwok K. Hung et al.,
IEEE TED-37 (3), p.654, 1990; ibid. (5), p.1323, 1990)
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VD(SAT)
dV(V)gLI
TkS
0
22
D
BID
4
Noise Model: thermal noise
||1 Evsat
eff
eff
New expression (MM11)Old expression (BSIM,MM9)
2
||1
Evsat
eff
eff
• thermal noise:
(F.M. Klaassen & J. Prins , Philips Res. Repts. 22, p.504, 1967)
(V)Qμ(V)Wg(V) invwhere:where:
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Noise Model: thermal noise (II)
0
5
10
15
0 1 2 3V GS (V)
F5
0
(dB
)
Measurement
Old model0
5
10
15
0 1 2 3V GS (V)
F5
0
(dB
)
New model
Measurement
Old model
50 Noise Figure (NMOS, W/L=160/0.35m, VDS=3.3V)
(A.J. Scholten et al., IEDM Tech. Dig., pp.155-158, 1999)
no hot electron effect needed
to describe noise behaviour
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Noise Model: thermal noise (III)
50 noise figure (no noise parameters needed)
verified on 0.35m, 0.25m and 0.18m CMOS(A.J. Scholten et al., IEDM Tech. Dig., pp.155-158, 1999)
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MOS Model 11: outline
Introduction
DC-Model
AC-Model
Noise Model
Model Parameters & Extraction
Summary
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Geometry Geometry
ScalingScaling Temperature Temperature
ScalingScaling Model Model
EquationsEquations WL
T
39 miniset
parameters
13 temperature
scaling parameters
37 geometry scaling
parameters
Parameters: model structure
OWWWLLLLLLOR kssskRERERE 111111
222
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extract miniset for each dut
determine geometry scaling
parameter set
ko
determine temperature scaling
measurements
0.1
0.15
0.2
0.25
0 5 10 15
MinisetScaling
1/LE (1/m)k o
(V
1/2)
example: 0.12m CMOS
Parameters: extraction strategy
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ID - VGS - curve for various VSB in linear region1
2
3
4
ID - VDS - and gDS - VDS - curves for various VGS
IG - VGS - and IB - VGS - curves for various VDS
CGG - VGS - curve at VSB=VDS=0V (optional)
required measurements per device
Parameters: measurements
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Measurements
Miniset extraction
Temperature scaling
Geometry scaling
Parameters: extraction outline
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effect parameters
threshold
IGINV , BINV , IGACC , BACC , IGOV
kO , B
subthreshold slope
flat-band voltage
mobility reduction
series resistance
conductance
impact ionization
gate current
velocity saturation
poly depletion
mO
VFB
kP
, sr , ph , mob
, R
sat
, DIBL , sf , Th
a1 , a2 , a3
Parameters: DC miniset
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flat-band voltage/poly depletion
mobility/series-resistance
velocity saturation/conductance
(sub)threshold parameters
1st-order estimation
gate current
impact ionization
extraction strategy:
(optional)
somewhat different strategy for long-channel and short-channel devices
start with long-channel device
Parameters: miniset extraction strategy
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}}
1st-order
parameter
estimate
Step 1: 1st-order estimation
tox
L
NP
W miniset parameters{
doping concentration in polysilicon gate
Parameters: miniset extraction of long-channel device
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NMOS W/L=10/10m
optimize ID and gm on absolute error: B, ko, and sr Step 1: 1st-order estimation
threshold mobility
VGS (V) VGS (V)
I D (A
)
gm (A
/V)
Parameters: miniset extraction of long-channel device
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NMOS W/L=10/10m
optimize ID and gm on absolute error: B, ko, and sr Step 1: 1st-order estimation
threshold mobility
VGS (V) VGS (V)
I D (A
)
gm (A
/V)
Parameters: miniset extraction of long-channel device
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optimize CGG on relative error: VFB, B, ko and 1/kP Step 2: VFB/poly-depletion (optional)
poly-depletion
NMOS W/L=100/10m
CG
G
(p
F)
VGS (V)
optimization region
measurement error due to gate current
Parameters: miniset extraction of long-channel device
MO
S-A
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rou
p M
eeti
ng
: M
OS
Mo
del
11
optimize CGG on relative error: VFB, B, ko and 1/kP Step 2: VFB/poly-depletion (optional)
poly-depletion
NMOS W/L=100/10m
CG
G
(p
F)
VGS (V)
Parameters: miniset extraction of long-channel device
MO
S-A
K G
rou
p M
eeti
ng
: M
OS
Mo
del
11
optimize ID on relative error: B, ko and mo Step 3: subthreshold parameters
NMOS W/L=10/10m
VGS (V)
I D
(A) optimization
region
measurement 1
Parameters: miniset extraction of long-channel device
MO
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K G
rou
p M
eeti
ng
: M
OS
Mo
del
11
optimize ID on relative error: B, ko and mo Step 3: subthreshold parameters
NMOS W/L=10/10m
VGS (V)
I D
(A)
measurement 1
Parameters: miniset extraction of long-channel device
MO
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p M
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ng
: M
OS
Mo
del
11
NMOS W/L=10/10m
optimize ID and gm on relative error: , sr, ph and mob
Step 4: mobility parameters
VGS (V) VGS (V)
I D (A
)
gm (A
/V)optimization
region
mobility reduction
Parameters: miniset extraction of long-channel device
MO
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ng
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OS
Mo
del
11
NMOS W/L=10/10m
Step 4: mobility parameters
VGS (V) VGS (V)
I D (A
)
gm (A
/V)
optimize ID and gm on relative error: , sr, ph and mob
mobility reduction
Parameters: miniset extraction of long-channel device
MO
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rou
p M
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ng
: M
OS
Mo
del
11
NMOS W/L=10/10m
Step 5: velocity saturation/conductance
VDS (V) VDS (V)
I D (A
)
gD
S (
A/V
)
optimize ID on absolute error: sat
optimize gDS on relative error: , sf and Th
velocity saturationconductance
Parameters: miniset extraction of long-channel device
MO
S-A
K G
rou
p M
eeti
ng
: M
OS
Mo
del
11
NMOS W/L=10/10mVDS (V) VDS (V)
I D (A
)
gD
S (
A/V
)
Step 5: velocity saturation/conductanceoptimize ID on absolute error: sat
optimize gDS on relative error: , sf and Th
velocity saturationconductance
Parameters: miniset extraction of long-channel device
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
NMOS W/L=10/10m
Step 6: gate current parameters
VGS (V) VGS (V)
I G (A
)
I G
(A
)
optimize IG on absolute error: Binv and IGINV
gate-to-channel current
Parameters: miniset extraction of long-channel device
MO
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rou
p M
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ng
: M
OS
Mo
del
11
NMOS W/L=10/10m
gate-to-channel current
Step 6: gate current parameters
VGS (V) VGS (V)
I G (A
)
I G
(A
)
optimize IG on absolute error: Binv and IGINVoptimize IG on relative error: IGACC and IGOV
gate-bulk & overlap current
Parameters: miniset extraction of long-channel device
MO
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rou
p M
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ng
: M
OS
Mo
del
11
NMOS W/L=10/10m
Step 6: gate current parameters
VGS (V) VGS (V)
I G (A
)
I G
(A
)
optimize IG on absolute error: Binv and IGINVoptimize IG on relative error: IGACC and IGOV
gate-bulk & overlap current
Parameters: miniset extraction of long-channel device
MO
S-A
K G
rou
p M
eeti
ng
: M
OS
Mo
del
11
NMOS W/L=10/10m
optimize ID and gm on relative error: , sr, ph and mob
Repeat steps 3 through 6, e.g. step 4:
VGS (V) VGS (V)
I D (A
)
gm (A
/V)optimization
region
error due to gate current
Parameters: miniset extraction of long-channel device
MO
S-A
K G
rou
p M
eeti
ng
: M
OS
Mo
del
11
NMOS W/L=10/10m
optimize ID and gm on relative error: , sr, ph and mob
Repeat steps 3 through 6, e.g. step 4:
VGS (V) VGS (V)
I D (A
)
gm (A
/V)
Parameters: miniset extraction of long-channel device
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
Measurements
Miniset extraction
Temperature scaling
Geometry scaling
Parameters: extraction outline
MO
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rou
p M
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ng
: M
OS
Mo
del
11
binning scaling rules fast and easy, however not physical
reproduces minisets
use 170 parameters per bin
physical scaling rules somewhat more elaborate, but physical
gives insight in technology
use 90 parameters per technology
two types of geometry scaling rules can be used:
Parameters: geometry scaling rules
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
E
kW;2
E
k;L
E
kL;oRo
oo2
o 11 WS
L
SL
Skk
E
E
P
E
E
Pβ
sq
exp11 L
W
LL
LLf
physical scaling rules have different forms per miniset parameter, e.g.:
scaling parameters determined from miniset values
or: geometry scaling
parameters
Parameters: physical geometry-scaling rules
MO
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rou
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ng
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OS
Mo
del
11
0.2
0.3
0.4
0.1 1 10 100
L drawn (m)
ko
(V
1/2)
MM11 scaling rule
scaling of body factor ko
NMOSW = 10m
miniset values
Parameters: geometry scaling of body factor ko
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
0
10
20
0 10 20 30 40 50
L drawn (m)1/
(kV
2 /A) MM11 scaling rule
conventional scaling rule
conventional scaling:
E
Esq L
W
scaling of gain factor
0
0.1
0.2
0 0.4 0.8
PMOSW = 10m
Parameters: geometry scaling of gain factor
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
physical geometry scaling fits of linear region (PMOS)
W/L = 10/10m
VGS (V) VGS (V)VGS (V)
I D
(A
)
I D
(A
)
I D
(m
A)
W/L = 10/0.8m W/L = 10/0.12m
Parameters: geometry scaling: ID-VGS-curves
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
physical geometry scaling fits of linear region (PMOS)
VGS (V) VGS (V)VGS (V)
g m
(A
/V)
g m
(A
/V)
g m
(m
A/V
)
Parameters: geometry scaling: gm-VGS-curves
W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
physical geometry scaling fits of subthreshold region (PMOS)
VGS (V)
I D
(A
)
I D
(A
)
VGS (V)VGS (V)
I D
(A
) Parameters: geometry scaling: subthreshold curves
W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m
MO
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rou
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eeti
ng
: M
OS
Mo
del
11
physical geometry scaling fits of output curves (PMOS)
VDS (V) VDS (V)VDS (V)
I D
(m
A)
I D
(A
)
I D
(m
A)
Parameters: geometry scaling: ID-VDS-curves
W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m
MO
S-A
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rou
p M
eeti
ng
: M
OS
Mo
del
11
physical geometry scaling fits of output curves (PMOS)
g DS
(A
/V)
g DS
(A
/V)
VDS (V)
g DS
(A
/V)
VDS (V)VDS (V)
Parameters: geometry scaling: gDS-VDS-curves
W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
physical geometry scaling fits of gate current (PMOS)
VGS (V)
|I G|
(A
)
|I G|
(A
)
VGS (V)VGS (V)
|I G|
(A
) Parameters: geometry scaling: IG-VGS-curves
W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m
MO
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ng
: M
OS
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Summary
use of s-formulations results in accurate description of
moderate inversion region improved description of several physical effects results in
accurate and symmetrical description of currents, charges, noise and distortion
fulfills Compact Model Council benchmark tests parameters determined from I-V and C-V measurements no increase in number of parameters no increase in simulation time
MOS Model 11, fulfills demands for advanced compact MOS modelling:
Excellent description of RF distortionExcellent description of RF distortion
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OS
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• Why is MM11 in the public domain?• Surface-potential-based model
• Accuracy of s-approximation
• Linear/saturation region transition
• Drain/source partitioning of IG
• Poly-depletion effect• Quantum-mechanical effects• Temperature scaling• Binning geometry-scaling rules• Literature
Appendices
MO
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ng
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OS
Mo
del
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W Semiconductors is a manufacturer with over 85% of sales to external customers
Appendix: Why is MM11 in the public domain?
Hence it makes sense to have MM11 available for the outside world:
• customers can use it
• vendors of EDA & extraction tools implement model
• facilitates communication about processes and wafer
• model is open for discussion and improvements
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OS
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- --++++++
n+
p
n+
- - - - - - - -+++
n+ - -
- - -- -
- - - -- -- -
- -- -
- -
-
depQinvQ
DIGI
SI
BI sOsFBGBoxinv kVVCQ
Appendix: surface-potential-based model
xQWI
s
invdrift
IDS x
QWI
inv
Tdiff
diffdriftDS III
sOoxdep kCQ
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
Surface Potential Drain Current
ID-VGS at VDS=1 V
0
1
2
0.5 1 1.5 2
VGB - VFB (V)
s (V)
s0 (V=0)
sL (V=1)
1.E-12
1.E-10
1.E-08
1.E-06
1.E-04
0.5 1 1.5 2
VGB - VFB (V)ID
(A)
Idrift
IdiffID
0
1
2
0.5 1 1.5 2
VGB - VFB (V)
s (V)
s0 (V=0)
sL (V=1)
1.E-12
1.E-10
1.E-08
1.E-06
1.E-04
0.5 1 1.5 2
VGB - VFB (V)ID
(A)
Idrift
IdiffID
0
1
2
0.5 1 1.5 2
VGB - VFB (V)
s (V)
s0 (V=0)
sL (V=1)
1.E-12
1.E-10
1.E-08
1.E-06
1.E-04
0.5 1 1.5 2
VGB - VFB (V)ID
(A)
Idrift
IdiffID
Appendix: surface-potential-based model (II)
MO
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ng
: M
OS
Mo
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0
20
40
0 1 2
V DS (V)
I D
(A
)
I drift
I diff
I D
0
1
2
3
0 1 2 3
V GB - V FB (V)
s
(V)
s0
0
1
2
3
0 1 2 3
VGB - VFB (V)
s
(V)
s0
VDS=0.5 V
0
1
2
3
0 1 2 3
VGB - VFB (V)
s (V
)
s0
VDS=1.0 V
0
1
2
3
0 1 2 3
VGB - VFB (V)
s (V
)
s0
VDS=1.5 V
Surface Potential Drain Current
ID-VDS at VGB - VFB =2 V
VDS=0 V
Appendix: surface-potential-based model (III)
MO
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ng
: M
OS
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del
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Appendix: accuracy of surface potential approximation
-3
-2
-1
0
1
2
3
0 0.5 1 1.5
V GS (V)
D
s
(mV
)
N A = 5*1017cm-3
t ox = 2 nm
V = 0 V
error w.r.t. implicit s
absolute error in s relative error in IDS
error in IDS due to Ds error is negligible
-4
-2
0
2
4
0 0.5 1 1.5
V GS (V)re
lati
ve e
rro
r I D
S (
%)
0
10
20
30
40
I DS
(A
)
W /L = 10/10mV DS = 0.1V
V SB = 0.0V
MO
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ng
: M
OS
Mo
del
11
Appendix: linear/saturation transition
VDS
VD
Sx
V DS
m =2
V DSATm =100
Model incorporates linear/saturation region for long-channel case:
longDSATDSAT VV
longDSATDSAT VV Short-channel devices:
Approximation used:
s = s(VGB,VDSx + VSB)
(K. Joardar et al, IEEE TED-45, pp. 134-148, 1998)
mmDSAT
mDS
DSATDSDSx
VV
VVV
21
22
where:
MO
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ng
: M
OS
Mo
del
11
Appendix: gate current partitioning
S IGDIGS D
IG
xJI Lx dGGD W
GDGGS III NMOS, tox=2 nm, W/L=10/0.6m
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5
V DS (V)
I GD
/IG
, I G
S/I
G
(-)
I GS /I G
MM11
V GS = 0.5 V
V GS = 1.5 V
I GD /I G
Segmentation
MO
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ng
: M
OS
Mo
del
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Appendix: poly-depletion effect
body factor of poly-silicon:
ox
PSiP
2
C
Nqk
depletion layer formed in Gate resulting in effective Gate potential:
psFBGB VV
Gate OxideOxide Substrate
Fq
sq pq
VGB > VFB
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
Appendix: poly-depletion effect
0
0.5
1
0 0.6 1.2 1.8VGS (V)
CG
G
(pF
)
W/L= 10/10m
kP =2
0
5
10
15
0 0.6 1.2 1.8VGS (V)
I D
(A
)
W/L= 10/10m
kP =2
drain current gate capacitance
influence of poly-depletion (VDS=50mV , VSB=0V)
pkpk
MO
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eeti
ng
: M
OS
Mo
del
11
0
0.4
0.8
1.2
-3 -2 -1 0 1 2 3
V GS (V)
Cg
g
(nF
)
MeasurementsModel
0
0.4
0.8
1.2
-3 -2 -1 0 1 2 3V GS (V)
Cg
g
(nF
)
MeasurementsModel
Appendix: poly-depletion effect
NMOS PMOS 0.18m CMOSW/L=80*612/2.5m
using electrical tox=3.6nm physical tox=3.2nm
MO
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ng
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OS
Mo
del
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Appendix: quantum-mechanical effects
Gate
EV
Oxide
EC
E i
EF
Substrate
DE
energy quantization
results in DVT
Distance from InterfaceC
arr
ier
Co
nc
en
tra
tio
n
Classical
Quantum-Mechanical
charge centroid
results in Dtox
MO
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ng
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OS
Mo
del
11
Appendix: quantum-mechanical effects
Distance from Interface
Ca
rrie
r C
on
ce
ntr
ati
on
Classical
Quantum-Mechanical
inversion-layer is formed at distance Dy from interface
31
effD Ey
effective oxide thickness:
ytt DSi
oxoxoxeff
(F. Stern, CRC Crit. Rev. Solid State Sci., pp.499-514, 1974)
MO
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ng
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OS
Mo
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11
0
0.4
0.8
1.2
-3 -2 -1 0 1 2 3
V GS (V)
Cg
g
(nF
)
MeasurementsModel
0
0.4
0.8
1.2
-3 -2 -1 0 1 2 3
V GS (V)
Cg
g
(nF
)
MeasurementsModel
Appendix: quantum-mechanical effects
using physical tox=3.2nm
NMOS PMOS 0.18m CMOSW/L=80*612/2.5m
MO
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eeti
ng
: M
OS
Mo
del
11
temperature scaling rules of the form:
miniset parameters at room temperature are exactly reproduced
where TR is room temperature
β
RT
TT or RT;BBT B
TTS
temperature scaling
parameters
Appendix: temperature scaling
MO
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eeti
ng
: M
OS
Mo
del
11
mobility/series-resistance
velocity saturation
(sub)threshold parameters
1st-order estimation
impact ionization
extraction strategy:
somewhat different strategy for long-channel and short-channel devices
start extraction for long-channel device(use default values of temperature parameters as 1st-order estimation)
Appendix: temperature-scaling extraction
MO
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eeti
ng
: M
OS
Mo
del
11
optimize ID on relative error:Step 1: subthreshold parameters
NMOS W/L=10/10mVGS (V)
I D
(A)
BTS ;
I D
(A)
VGS (V)
T=125ºC T=-40ºC
Appendix: temperature scaling long-channel device
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
optimize ID on relative error:Step 1: subthreshold parameters
NMOS W/L=10/10mVGS (V)
I D
(A)
BTS ;
I D
(A)
VGS (V)
T=125ºC T=-40ºC
Appendix: temperature scaling long-channel device
MO
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rou
p M
eeti
ng
: M
OS
Mo
del
11
optimize ID on relative error: , sr and ph
Step 2: mobility parameters
NMOS W/L=10/10mVGS (V) VGS (V)
I D (A
)
I D (A
)
T=125ºC T=-40ºC
Appendix: temperature scaling long-channel device
MO
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eeti
ng
: M
OS
Mo
del
11
Step 2: mobility parameters
NMOS W/L=10/10mVGS (V) VGS (V)
I D (A
)
I D (A
)
T=125ºC T=-40ºC
optimize ID on relative error: , sr and ph
Appendix: temperature scaling long-channel device
MO
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eeti
ng
: M
OS
Mo
del
11
optimize ID on relative error: sat
Step 3: velocity saturation
NMOS W/L=10/10mVDS (V) VDS (V)
I D (A
)
I D (A
)
T=125ºC T=-40ºC
Appendix: temperature scaling long-channel device
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ng
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OS
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Step 3: velocity saturation
NMOS W/L=10/10mVDS (V) VDS (V)
I D (A
)
I D (A
)
T=125ºC T=-40ºC
optimize ID on relative error: sat
Appendix: temperature scaling long-channel device
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ng
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OS
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maxL
maxW
minW
minL
1
2
3
4 12
11
10
9
8
7
6
5
16
15
14
13
W
L
minisets
binning rules based on
physical scaling
no parameter jumps at
bin borders
minisets are exactly
reproduced at corners
binning parameter set is calculated from minisets
no extra extraction or optimization needed
Appendix: binning geometry-scaling rules
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OS
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Appendix: literature
“Effect of gate-field dependent mobility degradation on distortion analysis
in MOSFET’s”, R. v. Langevelde and F.M. Klaassen,
IEEE Trans. El. Dev., Vol.44, p.2044, 1997
“Accurate drain conductance modeling for distortion analysis in MOSFETs”,
R. v. Langevelde and F.M. Klaassen, IEDM’97 Technical Digest, p.313, 1997
“A compact MOSFET model for distortion analysis in analog circuit design”,
R. v. Langevelde, Ph.D. Thesis, University of Technology Eindhoven, 1998
“Accurate thermal noise model for deep sub-micron CMOS”,
A.J. Scholten et al., IEDM’99 Technical Digest, p.155, 1999
“An explicit surface-potential-based MOSFET model for circuit simulation”,
R. v. Langevelde and F.M. Klaassen, Solid-State Electron., Vol.44, p.409, 2000
CMC benchmark tests
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OS
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Appendix: literature
“RF-Distortion characterisation of sub-micron CMOS”,
L.F. Tiemeijer et al., Proc. ESSDERC’00, p.464, 2000
“RF-Distortion in deep sub-micron CMOS technologies”,
R. v. Langevelde et al., IEDM’00 Technical Digest, p.807, 2000
“BSIM4 and MOS Model 11 benchmarks for MOSFET capacitances”,
A.J. Scholten et al., CMC meeting, March 2001, http://www.eigroup.org/cmc
“MOS Model 11, Level 1100’’, R. v. Langevelde,
Nat.Lab. Unclassified Report NL-UR 2001/813, April 2001, see website
“Compact MOS modelling for RF circuit simulation”,
A.J. Scholten et al., Proc. SISPAD’01, p.194, 2001
“Advanced compact MOS modelling”,
R. v. Langevelde et al., Proc. ESSDERC’01, p.81, 2001
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OS
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Appendix: literature
“Compact modelling of pocket-implanted MOSFETs”,
A.J. Scholten et al., Proc. ESSDERC’01, p.311, 2001
“Gate current: Modeling, DL extraction and impact on RF performance”,
R. v. Langevelde et al., IEDM’01 Technical Digest, p.289, 2001
“Parameter extraction for surface-potential based compact MOS Model 11”,
R. v. Langevelde, Agilent World-Wide IC-CAP Users’ Conference, Dec. 2001
“MOS Model 11, Level 1101’’, R. v. Langevelde et al.,
Nat.Lab. Unclassified Report NL-UR 2002/802, June 2002, see website