MOS Memory

8/11/2019 MOS Memory

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VLSI Technology and Applications


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Contents

MOS Memory-RAM

Static RAM

Dynamic RAM

ROMSense Amplifier

Address Decoder


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Introduction

Storage of large information.

Low Power Memory requirement.

Advanced fabrication technologies and compact design.

On chip memories in VLSI.


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Equivalent Circuits of Memory Cells

a) DRAM, b) SRAM, c) Mask (Fuse) ROM, d) EPROM, e) FRAM


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Memory Organization


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DRAM Cell Design

The four-transistor DRAM cell.

For write: WLenabled & complement data written from bit lines.

Data stored as charge at parasitic & gate capacitors.

For read: Voltage of bit line discharged.


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Two transistor DRAM cell

For write: Wbl driven with data, then raise wl(write line) allowdata to store node.

For read: precharge rbl & allow read transistor to turn on bypulling rllow.

Logic 1: pull rbllow, Logic 0: rbl unchanged.

Vrbl compared with Vrefto complete readout.


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One-transistor DRAM cell

Industry standard DRAM.

Separate capacitor for each storage cell.

Write operation: WL enable, data stored at C throughtransistor.

Read operation: destructive.


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DRAM cell Capacitor

a) DRAM cell with cylindrical stacked capacitor

b) DRAM cell with a trench capacitor.


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SRAM cell

Storage: Cross coupled inverters


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Full CMOS SRAM cell


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SRAM Cell Design

Basic SRAM Cell

Two cross coupled invertorsand access transistor.

WL: Select line, BL R/W line.

WL=0: Hold state,

WL=1 R/W operation.

Voltage Transfer Characteristics

Store valve at two stable states

Cell state change with Vth.

SNM: Separation in two curve.


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Six Transistor (6T) SRAM Read Operation

& pre-charged to high.

When WL high: current flowM3& M1to ground.

Current discharge Cbit.

Diff. b/w & sensed.

Read operation waveform

V: voltage diff. b/w & .

Target delay.

Problem:Current through M3& M1

rise voltage at q.

bb

b bbb


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Six Transistor (6T) SRAM Contd

Write Operation

To write 1, forcedto low.

To write 0 forcedto low.

Write 1 operation.

Voltage Transfer Characteristics

Pull low before WL high.

Regeneration action when WL high.

b

b

b


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Four Transistor (4T) SRAM

Large R, lower current & high power consumption. LargeRnoisy.

Adv: Small area, High packing density.

Disadv: Extra processing steps, high power consumption,lower SNM.


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Leakage Currents in SRAM

Sub-threshold leakage current

Gate tunneling current


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Leakage Currents in SRAM Cell

1. Subthreshold Current

The drain-source current of a transistorwhen the gate-source voltage is lessthan the threshold voltage.

Equation suggests two ways to reduce

Isub

-

Turn off supply voltage (V=0)

Increase threshold voltage

The problem with the first approach is

loss of state; with the second approach

is the loss of performance!


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Leakage in SRAM Cell

2. Gate Tunneling Leakage

Electrons (holes) tunneling fromthe bulk silicon through the gateoxide into the gate results in gatetunneling current in an NMOS(PMOS) transistor

Increasing Tox reduces gateleakage but degrades transistorseffectiveness as Tox must decreaseproportionally with process scalingto avoid short channel effects.


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Static Noise Margin (SNM)

SNM quantifies the amount of voltage noise required at the internal

nodes of a bitcell to flip the cells content.

Degraded SNM limits voltage scaling for SRAM designs.


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Low Power SRAM Design

Low power circuit technique: Memory cell, sense amplifier &precharging circuit.

Applications: Laptop, notebook, IC memory cards.

Power Dissipation in SRAM

Active power dissipation:

Decoder, memory cell, I/O ckt & write ckt.

Pmem-array= mPact+ (n - l) m Pleak+ m Idctf VDD. Reduce WL capacitance, DC current, supply voltage.

Standby Power Dissipation

Pstandby= m n Pleak Reduce supply voltage, leakage current increase due to Vth

reduction.


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Low Power Techniques

Banked Organization of SRAM

Reduce switching speed.

n = R x C, Total switching capacitance = R x C x Ccell

Splitting memory reduce switching capacitance.

(R x C x Ccell)/B


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Low Power Techniques Contd

Divided world line architecture

WL delay reduced by dividing WL in parts.

Global WL& Local WLs.

DWL technique for high density, high speed & low power.


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Hierarchical Word Decoding (HWD)

For SRAM more then 4Mb, no. of blocks increased In DWL.

Capacitance of global WL increases, delay & power increase.

Word select line divided into more levels.


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Bit-Line Capacitance Reduction

Reducing no. of cells per bit line by multidivided bit linetechnique.


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R d O l M C ll


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Read-Only Memory Cells

WL

BL

WL

BL

1WL

BL

WL

BL

WL

BL

0

VDD

WL

BL

GND

Diode ROM MOS ROM 1 MOS ROM 2

Diode ROM: Presence or absence of diode represent 1or 0

MOS ROM: Diode replaced with gate-source connection of an nMOS

Disadv: Additional power supply line required.

Different approaches to implement 1 and 0 ROM cell


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MOS ROM

WL [0]

VDD

BL [0]

WL [1]

WL [2]

WL [3]

Vbias

BL [1]

Pull-down loads

BL [2] BL [3]

VDD

4x4 Array: Overhead of supply lines reduced by sharing b/w cells. This

requires the mirroring of the odd cells around the horizontal axis.


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Non-Volatile Memories

The Floating-gate Avalanche-injection transistor (FAMOS)

Floating gate

Source

Substrate

Gate

Drain

n+ n+_p

tox

tox

Device cross-section Schematic symbol

G

S

D

An extra polysilicon strip is inserted b/w gate and channel.

Double the oxide thickness, Vthincreased.High Vdscreate high electric field and causes avalanche injection.

Hot electron effect.


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Floating-Gate Transistor Programming

20 V

10 V 5 V

20 V

DS

Avalanche injection


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A Programmable-Threshold Transistor

FLOTOX EEPROM


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FLOTOX EEPROM

Floating-gate Tunneling Oxide

Floating gate

Source

Substratep

Gate

Drain

n1 n1

FLOTOX transistor Fowler-NordheimI-V characteristic

2030 nm

10 nm

-10 V

10 V

I

VGD


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EEPROM Cell

WL

BL

VDD

Absolute threshold control

is hardUnprogrammed transistor

might be depletion

2 transistor cell


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Flash EEPROM

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n1 source n1 drainprogramming

Many other options


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Basic Operations in a NOR Flash Memory

Erase


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Write


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Read


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Memory Architecture: Decoders

Word 0

Word 1

Word 2

Word N2 2

Word N2 1

Storagecell

M bits M bits

Nwords

S0

S1

S2

SN2 2

A0

A1

AK2 1

K 5 log2N

SN2 1

Word 0

Word 1

Word 2

Word N2 2

Word N2 1

Storagecell

S0

Input-Output( M bits)

Intuitive architecture for N x M memory

Too many select signals:

N words == N select signalsK = log2N

Decoder reduces the number of select signals

Input-Output( M bits)

Decoder

Array Structured Memory Architecture


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Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword


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Row Decoders

Collection of 2Mcomplex logic gates

Organized in regular and dense fashion

(N)AND Decoder

NOR Decoder


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Hierarchical Decoders

A2A2

A2A3

WL 0

A2A3A2A3A2A3

A3 A3A 0A0

A0A1A0A1A0A1A0A1

A1 A1

WL 1

Multi-stage implementation improves performance

NAND decoder using

2-input pre-decoders


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Dynamic Decoders

Precharge devices

VDD f

GND

WL3

WL2

WL1

WL0

A0A0

GND

A1A1f

WL3

A0A0 A1A1

WL 2

WL 1

WL 0

VDD

VDD

VDD

VDD

2-input NOR decoder 2-input NAND decoder


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4-input pass-transistor based column decoder

Advantages: speed(tpddoes not add to overall memory access time)

Only one extra transistor in signal path

Disadvantage: Large transistor count

2-input NOR decoder

A 0S0

BL 0 BL 1 BL 2 BL 3

A 1

S1

S2

S3

D

4 t 1 t b d l d d


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4-to-1 tree based column decoder

Number of devices drastically reducedDelay increases quadratically with # of sections; prohibitive for large decoders

buffersprogressive sizingcombination of tree and pass transistor approaches

Solutions:

BL 0 BL 1 BL 2 BL 3

D

A 0

A 0

A1

A 1


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Decoder for circular shift-register

VDD

VDD

R

WL0

VDD

f

ff

f

VDD

R

WL1

VDD

f

ff

f

VDD

R

WL2

VDD

f

ff

f


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Sense Amp Operation

DV (1)

V (1)

V (0)

t

V

PRE

VBL

Sense amp activatedWord line activated


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Sense Amplifiers

tp

C DV

Iav

----------------=make DV as smallas possible

smalllarge

Idea: Use Sense Amplifer

outputinput

s.a.small

transition


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Differential Sense Amplifier

Directly applicable to

SRAMs

M 4

M 1

M5

M3

M2

VDD

bitbit

SE

Outy

Differential Sensing SRAM


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Differential Sensing SRAM

VDD

VDD

VDD

VDD

BL

EQ

Diff.

SenseAmp

(a) SRAM sensing scheme (b) two stage differential amplifier

SRAM cell i

WL i

2xx

VDD

Output

BL

PC

M3

M1

M5

M2

M4

x

SE

SE

SE

Output

SE

x2x 2x

y

y

2y

L t h B d S A lifi (DRAM)


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Latch-Based Sense Amplifier (DRAM)

Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.

EQ

VDD

BL BL

SE

SE

MOS Memory

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