mos inverter static - · PDF fileMOS Inverters ! Most fundamental circuit in MOS family !...
Transcript of mos inverter static - · PDF fileMOS Inverters ! Most fundamental circuit in MOS family !...
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Static (DC) Characteristics of MOS Inverters
Prof. MacDonald
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MOS Inverters
l Most fundamental circuit in MOS family l Represents the basic operation of all static gates l One input and one output
– Output = ~Input
l Inverter Threshold Voltage - Vth – input voltage where output equals input – not the same as transistor threshold Vt
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Voltage Transfer Characteristic (VTC) ideal
Vout
Vin
Vdd
Vdd Vth
infinite gain at threshold
zero gain at all other input voltages
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General Inverter Model
Vdd
Load
input
output
When Input high, NFET turns on and we have a voltage dividing resistor network consisting of the NFET (Low R) and Load (High R). Consequently, the output will be dropped down to RL/(RL + RH). Current will be constant (bad) and equal to Vdd/(RL + RH).
+ Vload -
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General Inverter Model
Vdd
Load
input
output
When Input Low, NFET turns off and capacitor is charged fully to Vdd. No current runs through the load and no voltage drop exists across the load.
Vdd
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Voltage Transfer Characteristic (VTC)
Vout
Vin
Vdd
Vdd=Voh Vth Vih Vil
Vout = Vin
gain = -1
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Noise Margin – low gain region
Vout
Vin
gain = -1
low gain region
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Noise Margin – high gain region
Vout
Vin
gain = -1
high gain region
Good design minimizes high gain region aka transition region.
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Noise Margin
Vin Vout
transition region indeterminate
Vih
Vil Vol
Voh NMH
NML
NMH=Voh-Vih
NML=VoL-ViL
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Single Source Noise Margin
Vn
Vol
Voh+Vn
? ? ? ?
Voh Vol Voh Voh Vol
+
If Vn is less than noise margin than the noise will be attenuated each stage and will quickly disappear. If Vn is greater than the noise margin, the noise will result in voltages at the input that will be in the high gain region and will be amplified through subsequent stages.
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Resistive Load Inverter
Vdd
input
output
Vdd RL
Voh=Vdd Vol Vout
I
Irl = Ids
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Resistive Load Inverter – Voh and Vol
[ ]RVVVVVVKII oldd
dsdstgsrds−
=−•−•••== 20)(2
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Voh Voh = Vdd because when the input voltage drops below Vt of the inverter, no current flows. No current flow in turn means no voltage drop across the load resistor and Vout = Vdd = Voh.
Vol If the input is driven to Voh=Vdd then the transistor is on and since Vgs > Vds it is also in linear mode. The drain will be at Vol and the gate will be at Voh.
( )tddltddol VVRKKR
VVV −•+−≈ +− 11
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Resistive Load Inverter – Vil
RVVVVKII outdd
tgsrds−
=−••== 20)(
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Vil To determine noise margin we need Vil which is one of two points where we have unity gain. When input low, output high and NFET in saturation.
ltilKR
VV 1+=
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Resistive Load Inverter – Vih
[ ]RVVVVVVKII oldd
dsdstgsrds−
=−•−•••== 20)(2
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Vih When Vin = Vih, the output is at Vol and the NFET is in the linear region.
l
ddtih
kRkRVVV 138
−+=14
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Resistive Load Inverter – Vth
RVVVVK
VVVRVVVVKII
thddth
thoutin
outddtrds
−=−••
==
−=−••==
20t
20in
)(21
)(21
Solve for Vth in quadratic equation. Correct root should be between 0 and Vdd
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Resistive Load Inverter – Static Power
RVVVddP
RVVII
IVP
outdd
outddrds
−••=
−==
•=
%)50(
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Resistive Load Inverter VTC
Vout
Vin
kR=2V-1
kR=4V-1
kR=8V-1
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Enhancement NFET Load Inverter
Vdd
input
output
Voh=Vdd Vol Vout
I
Il = Id Vgg
Two power supplies needed to keep load conducting while Vout = Vdd.
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Depletion NFET Load Inverter
Vdd
input
output
Voh=Vdd Vol Vout
I
Il = Id Vdd
Load NFET is always on and acts like a non-linear resistor. Requires two types of NFETs.
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[ ])(
0
0 outtloadddoutd
ltil
ol
ddoh
VVVVKKVV
VVV
+−•⎟⎠
⎞⎜⎝
⎛+=
≈
=
Solve for Vth in quadratic equation. Correct root should be between 0 and Vdd
Depletion NFET Load Inverter
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CMOS Inverter
Vout
Vin
Vout=Vin-Vtp
Vout=Vin-Vtn
Vout=Vtn Vout=Vdd+Vtp
A B
C
D
E
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CMOS Inverter
Vout
Vin
Vdd
Ids
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CMOS Inverter – Noise Margin
( )
r
tpddr
tn
th
r
tnrddtpout
r
tnouttoddih
k
VVk
VV
kVkVVVVil
kVVkrVVV
gndVolVddVoh
11
)(11
21
2
+
++=
+
+−+=
+
+••++=
=
=
•
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Layout of inverter – top view
n-well
W
W
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Layout of inverter – top view
n-well
drain
drain
source
source
gate
vdd
gnd
input
I1
I2 out in
I1
I2
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CMOS Tri-state Inverter
~en
en
input output
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CMOS Inverters - Summary
l At normal input levels, little static power l What happens if input is floated? l Dynamic Power only during transitions l In transition region, short circuit current exists l Very good noise properties l Body effect is irrelevant as no stacked transistors l transconductance ratio determines Vth
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