mos 2014 v2 - unice.frusers.polytech.unice.fr/~lorenz/mos_2014_v2.pdf · energy level, ie the Fermi...
Transcript of mos 2014 v2 - unice.frusers.polytech.unice.fr/~lorenz/mos_2014_v2.pdf · energy level, ie the Fermi...
MOS CAPACITOR –MOSFET TRANSISTOR –MOS INVERTERSProf. Philippe LORENZINIPolytech-Nice Sophia
Pr. Ph.Lorenzini 2
Outline
• Metal Oxyde Semiconductor Structure • MOS Transistor• MOS Inverters
• NMOS • CMOS
From MOS Capacitor to CMOS inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 3
• Two definitions (only 2!)• Work Function (Travail de sortie) : this is the energy we
have to give to an electron to extract it of metal without kinetic energy. It reaches the "vacuum level". Work function is the energy difference between the vacuum level and the highest occupied energy level, ie the Fermi level.
• Electron Affinity (Affinité électronique ) : it’s the difference between the vacuum level and the bottom of the conduction band. It’s only defined for SC and not for Metal.
• Unity for both of them: eV (electron volt)
Me
SCe
Pr. Ph.Lorenzini 4
Metal Oxyde Semiconductor Structure
MOS capacitor
Energy band diagram of the three components of a MOS system
fig
SCSC eE
2 fi
gSCSC e
E
2
From MOS Capacitor to CMOS inverter
• The field effect is the variation of the conductance of a channel in a semiconductor by the application of an electric field
Field Effect Transistor
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 5
Pr. Ph.Lorenzini 6
Equilibrium of MOS structure
MeSCeSCe
EFEF
Metal SC(n)
EV
EC
SCSCMbi
xdx
VddxdVEV
)(, 2
2
,
Independant system
MeSCeSCe
EFEF
Metal SC(n)
EV
EC
eVbi
Equilibrium statedx
From MOS Capacitor to CMOS inverter
Pr. Ph.Lorenzini 7
The five regimes : a functionof workfunction
(a) Accumulation
(b) Flat band
(c) Desertion / depletion
(d) Weak inversion
(e) Strong inversion
From MOS Capacitor to CMOS inverter
Ox
Pr. Ph.Lorenzini 8
Energyband diagramfor ideal n and p type MOS capacitors underdifferentbiasconditions
From MOS Capacitor to CMOS inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 9
Pr. Ph.Lorenzini 10
We suppose we deal with a p type semiconductor:
0 FiFFi EEe
VgVsxVxV ,)0( ,0)(
warning: in few books, absolute value is not present!!!!
Field, potential and charges in Silicon
From MOS Capacitor to CMOS inverter
Pr. Ph.Lorenzini 11
Poisson’s Equation:
Charge density )()()()()( xNxNxnxpex AD
DA NNnp 00 )exp(0 kTe
nn Fii
)exp(0 kT
enp Fi
i
)))((exp())(exp()( 0 kTxVen
kTxeVnxn Fi
i
kTxeVp
kTxVenxp Fi
i)(exp)))((exp()( 0
From MOS Capacitor to CMOS inverter
Field, potential and charges in Silicon
SC
xdx
Vd )(
2
2
Pr. Ph.Lorenzini 12
kT
xeVkT
xeV
eneppnex)(
0
)(
000)(
)1()1()( )(
0
)(
02
2kT
xeVkT
xeV
SC
enepedx
xVd
dxxdV
dxxdV
dVd
dxxdV
dxd
dxxVd )()()()(
2
2
)()1()1()()( )(
0
)(
0 xdVenepedx
xdVddx
xdV kTxeV
kTxeV
SC
From MOS Capacitor to CMOS inverter
Field, potential and charges in Silicon
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 13
• We compute the integral from bulk to a point x in SC
)(
0
)(
0
)(
0
)(
0)()1()1()()( xV
kTxeV
kTxeV
SC
dxxdV
xdVenepedx
xdVddx
xdV
V(x=« bulk »)=0 et 0)(
bulkdxxdV
dxxdVxE )()( And the Electric Field is given by:
1)(1)(2)()()(
0
0)(
02
2
kTxeVe
pn
kTxeVe
kTpdx
xdVxE kTxeV
kTxeV
SC
Field, potential and charges in Silicon
MO SVg
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 14
1)(1)(2)()()(
0
0)(
2
222
kTxeVe
pn
kTxeVe
LekT
dxxdVxE kT
xeVkT
xeV
D
With the Debye length: o
SCD pe
kTL 2
If we use the Gauss’s theorem:SC
SCS
QExE
)0(
Field, potential and charges in Silicon
metalSkT
VeSkT
eV
D
SCSC Q
kTeV
pne
kTeVe
LekTQ
FISS
2
1
0
0)2(
112 metal
SkTVe
SkTeV
D
SCSC Q
kTeV
pne
kTeVe
LekTQ
FISS
2
1
0
0)2(
112
metalSkT
VeSkT
eV
D
SCSC Q
kTeV
pne
kTeVe
LekTQ
FISS
2
1
0
0)2(
112 metal
SkTVe
SkTeV
D
SCSC Q
kTeV
pne
kTeVe
LekTQ
FISS
2
1
0
0)2(
112
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 15
For Vs (and so Vg) negative(accumulation)
For Vs (and Vg) positive butless than 2fi
(depletion – weak inversion)
For Vs (and Vg) > 2fi(strong inversion)
Field, potential and charges in SiliconAllways negligible
(p type)
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 16
Weak / Strong Inversion
ns=p0=NA
i
AFiS n
NekTV ln22
i
AFiS n
NekTV ln22
This condition will define a veryimportant parameter of the struture: the threshold voltage or the required gate voltage to put the transistor in strong inversion regime
eFI
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 17
Measurement of capacitance in IdealMOS Structure
The C-V curve is usually measured with a CV meter:• We apply a DC bias voltage Vg + small sinusoidal signal (100 Hz to 10 MHz)• We measure the capacitive current with an AC meter (90 degree phase shift)
=> icap/vac =C
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 18
When a voltage Vg is applied to the MOS Gate, part of itappears as a potential drop across oxide and the rest ofit appears as a band bending Vs in silicon:
Sox
SCSCoxg V
CQVVV
S
ox
SCSCoxg V
CQVVV
MO SVg
Vox VSCOxide and Silicon have capacitor behavior
Measurement of capacitance in IdealMOS Structure
VG
VOX
VS
X
V(X)
-tOX 0
SC is grounded, so VSC=VS
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 19
• Oxide capacitance: as a parallel‐plate capacitor
• We can also write :
Measurement of capacitance in Ideal MOS Structure
2F/cm ox
oxox d
C
)()( SG
M
SG
M
OX
Mox VVd
dQVV
QVQC
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 20
• Semiconductor (silicon) capacitance
S
M
S
SCSC dV
QddV
Qdoltage
C )()(SC) across v(
SC)in (charge
S
M
S
SCSC dV
QddV
Qdoltage
C )()(SC) across v(
SC)in (charge
Measurement of capacitance in IdealMOS Structure
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 21
• Global capacitance of the structure:
• If we combine the 3 relations above :
G
SC
G
MMOS dV
dQdVdQC
G
SC
G
MMOS dV
dQdVdQC
seriesin connected escapacitanc 2 111
SCoxMOS CCCseriesin connected escapacitanc 2 111
SCoxMOS CCC
Measurement of capacitance in IdealMOS Structure
M O SVg
Vox VSC
Pr. Ph.Lorenzini 22
• Total charge in SC depends on different regimes 2 types of charges, fixed and mobile/free:
depSSC QQQ charges fixed charges carriers free depSSC QQQ charges fixed charges carriers free
S
dep
S
S
S
depS
S
scSC dV
dQdVdQ
dVdQdQ
dVdQC
)(
S
dep
S
S
S
depS
S
scSC dV
dQdVdQ
dVdQdQ
dVdQC
)(
Semiconductor capacitance can be written as:
Measurement of capacitance in IdealMOS Structure
From MOS Capacitor to CMOS inverter
Pr. Ph.Lorenzini 23
depSSC QQQ charges fixed charges carriers free depSSC QQQ charges fixed charges carriers free
depSS
scSC CC
dVdQC
depS
S
scSC CC
dVdQC
Semiconductor capacitance can be written as:
Measurement of capacitance in IdealMOS Structure
From MOS Capacitor to CMOS inverter
• Total charge in SC depends on different regimes 2 types of charges, fixed and mobile/free:
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 24
• Summary: MOS capacitor is equivalent :- of 2 capacitors series connected, COX and CSC- CSC is equivalent of two capacitors- the two are variable and be view as 2 capacitors in //
Cox
Csc
Cox
Cs Cdep
Measurement of capacitance in IdealMOS Structure
Conclusion: the whole capacitance of MOS structure isfunction of bias conditions or operating regime throughCSC
metalSkT
VeSkT
eV
D
SCSC Q
kTeV
pne
kTeVe
LekTQ
FISS
2
1
0
0)2(
112 metal
SkTVe
SkTeV
D
SCSC Q
kTeV
pne
kTeVe
LekTQ
FISS
2
1
0
0)2(
112
Pr. Ph.Lorenzini 25
Capacitance of MOS structure
• Accumulation Regime: VS<0 ie VG<0
02 2
kTeV
D
SCSC
S
eeL
kTQ 02 2
kTeV
D
SCSC
S
eeL
kTQ
SgoxSCs
SCSC VVC
kTeQ
kTe
dVdQC
22
From MOS Capacitor to CMOS inverter
Pr. Ph.Lorenzini 26
Capacitance of MOS structure
• Accumulation Regime: VS<0 ie VG<0
SgoxMOS
SgoxSCoxMOS
VVe
kT
CC
VVe
kT
CCCC
2111
21111
From MOS Capacitor to CMOS inverter
metalSkT
eVSkT
eV
D
SCSC Q
kTeVe
pn
kTeVe
LekTQ
SS
2
1
0
0 112
Cox
Csc
Pr. Ph.Lorenzini 27
Capacitance of MOS structure
• Accumulation Regime: VS<0 ie VG<0
kT=26 meV, in accumulation regime VS is around ‐0,3 V to ‐0,4 V, as soon as VG<‐1 to ‐2 V, so we can simplify to:
oxSgoxMOS CVVe
kT
CC12
111
oxSgoxMOS CVVe
kT
CC12
111
From MOS Capacitor to CMOS inverter
metalSkT
eVSkT
eV
D
SCSC Q
kTeVe
pn
kTeVe
LekTQ
SS
2
1
0
0 112
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 28
Capacitance of MOS structure
• Flat Band: VS =0 V ie VG=0 V(warning : ideal structure!!!!!)
Analytical computing:D
SCSC L
fbC
)(D
SCSC L
fbC
)(
A
SC
SC
oxox
ox
DSC
oxox
oxMOS
NekTdLd
fbC
)(
A
SC
SC
oxox
ox
DSC
oxox
oxMOS
NekTdLd
fbC
)(
Pr. Ph.Lorenzini 29
Capacitance of MOS structure
• Depletion regime and weak inversion
FiSV 20 FiSV 20
022212
1
depSSCA
S
D
SCSC QVeN
kTeV
eLkTQ 022
212
1
depSSCA
S
D
SCSC QVeN
kTeV
eLkTQ
dep
SC
S
SCA
S
SCSC WV
eNdVdQC
21
2 dep
SC
S
SCA
S
SCSC WV
eNdVdQC
21
2
From MOS Capacitor to CMOS inverter
Wdep
Insulator
Pr. Ph.Lorenzini 30
Capacitance of MOS structure
• Depletion regime and weak inversion
FiSV 20 FiSV 20
dep
SC
S
SCA
S
SCSC WV
eNdVdQC
21
2 dep
SC
S
SCA
S
SCSC WV
eNdVdQC
21
2
)/2(1)(
2ASCgox
ox
depSC
oxox
oxMOS
eNVCC
WddepletionC
)/2(1)(
2ASCgox
ox
depSC
oxox
oxMOS
eNVCC
WddepletionC
From MOS Capacitor to CMOS inverter
Pr. Ph.Lorenzini 31
Capacitance of MOS structure
• Strong inversion FiSV 2 FiSV 2
From MOS Capacitor to CMOS inverter
metalSkT
VeSkT
eV
D
SCSC Q
kTeV
pne
kTeVe
LekTQ
FISS
2
1
0
0)2(
112 metal
SkTVe
SkTeV
D
SCSC Q
kTeV
pne
kTeVe
LekTQ
FISS
2
1
0
0)2(
112
02 2)2(
kT
Ve
D
SCSC
FIS
eeL
kTQ 02 2
)2(
kT
Ve
D
SCSC
FIS
eeL
kTQ
kTVe
Ds
SCSC
FIs
eLdV
dQC 2)2(
2
oxSCoxMOS CCCC
1 111
p type SC
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 32
Capacitance of MOS structureaccumulation dep
???
p type SC
Strong inversion
DSC
oxox
oxMOS
LdfbC
)(
DSC
oxox
oxMOS
LdfbC
)(
SgoxMOS VVe
kT
CC
2111
depSC
oxox
oxMOS
WddepletionC
)(
depSC
oxox
oxMOS
WddepletionC
)(
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 33
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 34
Capacitance of MOS structure
• Strong inversion:
Which mechanism governs the onset of strong inversion layer?
P type SC : we must create electrons at oxide/SC interface. Where they come from? FromMetal : NO because oxide barrier From SC (neutral region) : NOminority carriers (e‐)
Only one solution: thermal (or optical) generation
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 35
Capacitance of MOS structure
• Strong inversion: • Thermal generation?
• N°1 :In the space charge + dissipation of charge by electric field
• N°2 : In the neutral region
First mechanism dominates but it’s a slow one.
recombination
+
+
+
++
p ++
EF
space charge zone
diffusion zone
0 W
n
p+SiO
2
n+
metal contactsemitransparent metal
(a)
(b)
(c)
Pr. Ph.Lorenzini 36
• Strong inversion• Which Delay time to create strong inversion layer ?
m
ith
ng2
m
ith
ng2
ASth Ng ASth Ng mi
AS n
N 2 mi
AS n
N 2
Strong inversion limit: nS = NA
More realistics mi
AS n
N 10 -1 mi
AS n
N 10 -1
From MOS Capacitor to CMOS inverter
Capacitance of MOS structure
Shockley-Read equation
Si: ni=1010 cm-3
NA=1015 cm-3 s=1s !!m=10-5 s
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 37
• When we measure C(V) , results depend on YES or NO, we give enough time to create this layer• YES: we measure capacitance du to inversion layer • NO : Depletion layer preserves the neutrality of the system with
an increase of its width . The limit is the breakdown of the semiconductor
Results are frequency dependant
Capacitance of MOS structure
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 38
3 cases :
Low frequency+
Slow ramp Vg
x
Q
x
Q
High frequency+
Slow ramp Vg
x
Q
High frequency+
High ramp Vg
Capacitance of MOS structure: strong inversion
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 39
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 40
• minimum capacitance (HF):
Asc
iA
ox NenNkT
CC 2min
)/ln(411
)/ln(4222max iA
A
scFi
A
sc nNNekT
eNW
BF
HF
Capacitance of MOS structure: strong inversion
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 41
MOS capacitor : parasitic effects• 2 factors modify « ideal » structure of MOS capacitor.
• The Charges in oxide and/or Charges at interface Oxide – SC.• The Difference between the work function of the Metal and the SC
Influence on the threshold voltage VT of the structure.
Pr. Ph.Lorenzini 42
• Distribution of charges in the oxide :• Mobile ionic charge• Oxide traped charge• Fixed oxide charge• Traped charge at Si-SiO2 interface
K+
Na+ Ionic mobiles
- - - - -+ + + + traped
+ + + + +x x x x
SiO2
SiOx
Si
Depending on their position in the oxide, the charges will influence more or less on the electron population below the gate.
From MOS Capacitor to CMOS inverter
MOS capacitor :oxide charge
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 43
MOS capacitor :oxide charge
• Effect of a sheet charge of areal density Q within the oxide layer of an MOS capacitor:
Oxyde
x
(x)Vg=0V
SiMetal
0 x1
Q
x
(x)Vg=Vfb
dox
-Q
Q
Oxide charges are compensated with charges in Metal AND SC.
If Vg=Vfb, charges in SC must be zero. Only Metal« DO the job »
ox
ox
oxox
oxg C
QdxxQ
V
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 44
• The effect is maximum when the charges are located at the interface oxide - SC, ie Qox=QSS (and no effect if Qox close to Metal)
oxdx ox
ssg C
QV
FBox
SoxSg V
CVQVV
)()( FBox
SoxSg V
CVQVV
)()(
It is a common practice to define an equivalentoxide charge per unit area Qox located at the oxide– silicon interface (ie QSS):
MOS capacitor :oxide charge
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 45
Work function difference
• Work function difference non zero oxide field.• Even when Vg = 0 V, structure show a band bending
e
Depletion zone
A gate voltage must be applied to restore the flat band condition VFB = M– S = MS : this voltage is called Flat Band voltage VFB
Pr. Ph.Lorenzini 46
• Work function difference.• Example: polysilicon n+ gate on p-MOS
siliciumpoly en
siliciumpoly e
n
fig
SiliciumSC eE
2 fi
gSiliciumSC e
E
2
)ln(56.02 i
afi
gpolyMS n
Ne
kTe
E )ln(56.0
2 i
afi
gpolyMS n
Ne
kTe
E
From MOS Capacitor to CMOS inverter
Work function difference
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 47
Non ideal MOS capacitor
• Taking into account both Oxide charges and work-function difference, the global flat band voltage can bewritten as:
ox
oxMSFB C
QV ox
oxMSFB C
QV
Warning: this is the voltage we have to applyon the gate to restore de flat band condition.
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 48
Threshold voltage
• Key parameter for behavior understanding of transistor
• Many definitions (same results!):• nS = NA
• Vs = 2 fi
• …
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 49
VT is simply the applied gate voltage when the surface potential or band bending reaches 2FI and the siliconcharge is equal to the bulk depletion charge for thatpotential
FBFiOX
FiASCFiSgT V
CeN
VVV
24
)2(
FBFiOX
FiASCFiSgT V
CeN
VVV
24
)2(
(we suppose here that no bias of bulk is present no body effect)
Threshold voltage
VT
VOX
VS=2FI
X
V(X)
-tOX 0
)0( FBV
(from slide 16)
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 50
• Substrate sensitivity - Body Effect
• In general the MOS devices have a common silicon substrate substrate voltage is equal for all transistor.
• BUT when multiple NFETs (or PFETs) are connected in series in a circuit, they share a common body (the silicon substrate) but their sources do not have the same voltage. We must introduce a coefficient that accounts for this effect :
Threshold voltage
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 51
=0
>0+++++++
<0
>0+++++++
+ + +- - -
++
One part of Gate voltage is no more used to create inversion layer but just to compensate the extra depletion width VT will increase
Threshold voltage
+
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 52
• The new threshold voltage taking account the body effect can be written as:
• The substrate sensitivity as:
• Of course substrate bias have to be reverse to preventcurrent flow
oxT
ox
SBFiasc
SBoxSB
T
CQV
CVeN
dVdQ
CdVdV
et )2(2/1
oxT
ox
SBFiasc
SBoxSB
T
CQV
CVeN
dVdQ
CdVdV
et )2(2/1
FiSBFiTT VVV 220 FiSBFiTT VVV 220 ox
SCA
CeN
2
ox
SCA
CeN
2
Threshold voltage
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 53
The effect of (reverse) substrate bias is to widen the bulkdepletion region and raise the threshold voltage:• The back contact acts as a back Gate• We can tune VT !
VVd
FB
ox
0A200
0 2 4 6 8 10
0,8
1,0
1,2
1,4
1,6
1,8 Na = 1E16 cm-3
Na = 3E15 cm-3
T
Substrate bias voltage VSB (V)
Thresholdvolta
ge (V
)
Threshold voltage
MOS-FET TRANSISTOR
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 55
MOS-FET transistor
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 56
Graphical summary of the major processing steps in the formation of a MOSFET Transistor
http://www.youtube.com/watch?v=dR-Qtv-7uWI
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 57
MOS-FET transistor
Stockage time ?
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 58
Linear regime
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 59
Saturation / linear limit
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 60
Saturation regime
Effective length of canal decreases from L to L’
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 61
Basic MOSFET IV Model
• L, canal length( y oriented)• W, canal width(z oriented)• V, voltage in the canal (f(y))
• V(y=0) = V(source) = Vs = 0 V• V(y=L) = V (drain) = Vds
• Vg, gate voltage• -VBS, body voltage
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 62
Schematic MOSFET cross section (Taur)
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 63
Charge sheet approximation
• Analytical solution we simplify the model:• Charge sheet approximation (xi=0):
• We assume all the inversion charges are located at the siliconinterface without any thickness
• No potentiel drop across this layer• No band bending across this layer
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 64
First step: calculation of inversion layer charge function of Vg
))(2(2)(2 yVeNyVeNWeNQ FiSCASSCAMAdep
))(2())(()()( yVVVCyVVVCyQyQ FiFBgoxSFBgoxmétalsc
))(2(2))(2( yVeNyVVVCQQQ FiSCAFiFBgoxdepscinv
21
))(2(2))(2()(
e
yVNe
yVVVCe
Q
eQ
eQ
yn FiSCAFiFBgoxdepscinvS
Charge sheet approximation
• Current density in the channel can be caused by diffusion and drift components
• Current is simply given (integration over channel section)
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 65
dydn
qkTqµ
dyydVqnμ=Jn 00)(
Charge sheet approximation
ii
ii
xx
DS
xWxW
DS
dxdydn
qkTqµWdx
dydVqnWI
dxdydn
qkTqµdzdx
dydVqndz=I
0 0
0 0
0 00
0 00
There is a sign change because we want IDS>0 in –y direction
• The previous relation can be rewritten
• If we remember that:
• Current expression can be found
• And so, by integrationg from y=0 to y=L and as current isindependant of y:
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 66
ii xx
DS qndxdyd
qkTWµqndx
dydV=WI
0000
ix
inv dxyxnqQ
0 ),(
dyVdQ
qkTWµ
dydVVQWμ=I n
invDS)()( 00
Charge sheet approximation
)(
)0(
)(
)0(00
LQ
Q inv
LV
V inv
L
DSinv
inv
dQq
kTdVQ=WdyI
conduction diffusion
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 67
• If we want to derive basic expressions for long channel currentin linear and saturation regions, we can neglect drift component
Charge sheet approximation
DS
V
inv
LV
V inv
L
DS dVVQWdVVQWdyI00
)(
)0(00)()(
)2()2(2
32
)2
2(
23
23
FiDSFiox
Asc
DSDS
FiFBgoxnDS
VC
eN
VVVVCL
WI
)2()2(2
32
)2
2(
23
23
FiDSFiox
Asc
DSDS
FiFBgoxnDS
VC
eN
VVVVCL
WI
After few simple steps:
!! Cox is the oxide capacitance per surface unit (Fm‐2 ou Fcm‐2)!!
))(2(2))(2( yVeNyVVVCQ FiSCAFiFBgoxinv with
DSTGSoxnDS
DSox
FiAscFifbGSoxnDS
VVVL
WCI
VCeN
VVL
WCI
)(
)4
2(
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 68
Characteristics in the linear (triode) region
When VDS is small (VDS << 2Fi) , one can expand the previousequation into power series in VDS and keep only first orderterm:
We recognize threshold voltage VT.
In the linear region, the MOSFET simply acts like a resistor modulated by the gate voltage
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 69
• For larger values of VDS we have to keep second order term(quadratic term) and a good approximation of current is:
2
2)( DSDSTgsoxnDS VmVVV
LWCI
Cdm is the bulk depletion capacitance in limit of strong inversion
13114/
1
m
ox
ox
dm
ox
FiAsc
Wd
CC
CeN
mwith
Characteristics in the linear (triode) region
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 70
• Previous equation is a parabole. Ids follows a parabolic curve with VDS until a maximun (or saturation) value is reached when VDS = Vdsat.
mVV
VV TgsDsatD
)(
mVV
LWCII Tgs
oxnDsatDS 2)( 2
In the case of thin oxide and lowdoping m can be reduced to 1 andyield the well known expression:
2)(2 TgsoxnDsatDS VV
LWCII 2)(2 TgsoxnDsatDS VV
LWCII
Dra
in c
urre
nt
VDS
Characteristics in the saturation region
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 71
• Without any approximation (series expand,…), completeexpressions for IDSAT can be expressed as:
)2
(2
2 222ox
AscFBgs
ox
Asc
ox
AscFiFBgsDsat C
eNVV
CeN
CeN
VVV
))(
34(12)222)(2(
6
21
ox
FiscAFiFbgsFiFBgsFiDsatFiDsatoxndsat C
eNVVVVVVCL
WµI
If we suppose high value for Cox (thin oxyde) and low doping level, threshold voltage can be simplified as , and at the same time we can rewrite
FBFiT VV 2
FBFigsTgsdsat VVVVV 2
22
2)(
2 DsatoxnTgsoxnDsat
TgsDsat
VCL
WµVVCL
WµI
VVV
Characteristics in the saturation region
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 72
Subthreshold characteristics– weak inversion region
• Three regimes:• Triode (Linear)• Saturation• OFF state (if Vg < VT for nMOS)
• Transition ON /OFF is not so sharp• Weak inversion for fi <Vs <2Fi
• Subthreshold behavior is of importance:• Low power• Low voltage digital logic and memory circuits
MOSFET basics• Subthreshold current : « OFF » is not totally « OFF »
• Previous analysis VGS<VT, NMOS (NFET) turns OFF• In reality, for VGS~VT, a « weak » inversion layer still exists and some
current (drift component) can flow between S and D.• This is the so called “subthreshold conduction”
∞
0
with , a ideality (or nonideality) factor (≥1)• Remember that changes by 10 for every x60 mV change in
VGS.• Typically, if IDS decreases for one decade , then VGS must decrease by
at least x60 mV (in fact around 80 mV, ) (at 300K!).
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 73
MOSFET basics• Subthreshold current :
(for VGS<VT)
VT1
Exponential Quadratic
1 decade
VT2
VT3 VGS
log IDS
IOFF
~80 mV
For example:
0
• If we suppose VT=0,3V
• 0,3V/80 mV=3,75
• ION/IOFF = 103,75 ~ 5600
• If VT=0,6V, ION/IOFF >107 !!
ION
OF COURSE WE WANT CLOSE TO UNITY
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 74
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 75
Short channel MOSFETs
• Threshold voltage reduction• Drain Induced Barrier Lowering (DIBL)• Channel length modulation• MOSFETs breakdown• …
76
Threshold voltage reduction: short channel effect (Kang et al)
• Origin: • Previous VT expression supposes
channel depletion region comes onlyfrom gate
• In fact one part is created by depletionregion associated by source/channeland drain/channel pn junctions
• Overestimation of charge induced by gate overestimation of VT
• This reduction more prominentfor MOSFET with shorter channellength
00 )()( TTT VllongchanneVelshortchannV 00 )()( TTT VllongchanneVelshortchannV
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter
77
• Origin: • Previous VT expression supposes
channel depletion region comes onlyfrom gate
• In fact one part is created by depletionregion associated by source/channeland drain/channel pn junctions
• Overestimation of charge induced by gate overestimation of VT
• This reduction more prominentfor MOSFET with shorter channellength
00 )()( TTT VllongchanneVelshortchannV 00 )()( TTT VllongchanneVelshortchannV
Threshold voltage reduction: short channel effect (Kang et al)
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 78
biA
SidS V
eNx 2
)(2DSbi
A
SidD VV
eNx
1
21. ,
,j
DdSjDS x
xxL
121121
241
0j
dD
j
dSjFiASi
oxT x
xxx
Lx
NeC
V
Threshold voltage reduction: short channel effect (Kang et al)
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 79
• Threshold voltage isfunction of:• Channel length• Drain –Source voltageVds
through xdD
0 1 2 3 4 5 60,3
0,4
0,5
0,6
0,7
0,8
0,9 VT0
Thresholdvolta
ge(V
)
Channel Length (µm)
Threshold voltage reduction: short channel effect (Kang et al)
Drain Induced Barrier Lowering (DIBL)
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 80
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 81
Channel length modulation (saturation operation)
• At the onset of pinch-off (VDS>VDSAT),the effective channel length (the length ofinversion layer) is reduced.
DsatDS
D IVLL
LI)(
DSV
LL
11
1 f DSVI
)1()(2
)( 2DSTGS
oxnD VVV
LWCµsatI
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 82
MOSFET Breakdown
• 2 main effects:• punchthrough breakdown
• Punch through in a MOSFET is an extreme case of channel length modulation where the depletion layers around the drain and source regions merge into a single depletion region.
• Punch through causes a rapidly increasing current with increasing drain‐source voltage• No current saturation
• Impact ionisation at the drain:• Electron acceleration in the channel• Impact ionisation holes electrons pairsgenerated
• Holes collected by substrate substrate current voltage drop in the channel• Reduction of VT ( body effect)• Increase of current and so on !• Permanent dammage
• Difficulties: • In general, capacitances associated with MOS circuits are a
complicated function of geometries and process• Not lumped capacitances but distributed capacitances
• In the following, first approximation model• Sufficiently accurate to represent main characteristics of MOSFET
charge voltage behavior• All the capacitances are lumped
• Three differents physical origins• Overlay capacitance• Oxyde capacitance• Junction capacitance
Important point : capacitances are dependent of bias voltage / working point.
MOSFET capacitances
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 83
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 84
• Overlay capacitances:• LD, gate – drain and gate – source overlay• LM, mask length
LM
LLD LD(n+) (n+)
gateL=LM ‐ 2.LD
ox
oxox
DoxGD
DoxGS
dε
C
LWCoverlapCLWCoverlapC
=
..=)(..=)(
ox
oxox
DoxGD
DoxGS
dε
C
LWCoverlapCLWCoverlapC
=
..=)(..=)(
MOSFET capacitances
W
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 85
Cd
b
MOSFET(DC Model)
Cgb
Cgd
Cgs
Cdb
Csb
S
D
G B
Lumped representation of parasistics capacitances
Equivalent model (with overlapcapacitances)
MOSFET capacitances
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 86
Gate – Channel capacitances
canal
canal
• Cut off mode:
• Linear mode
• Saturation mode
Cgs = Cgd = 0Cgb = CoxWL
substrate) shields (chanel 021
gb
oxgdgs
C
WLCCC
substrate) shields (chanel 0
0,32
gb
gdoxgs
C
CWLCC
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 87
Oxyde capacitance
Capacitance Cut off Linear saturation
Cgb(total)
Cgd(total)
Cgs(total)
CoxWL
CoxWLD
CoxWLD
0 0
Doxox WLCWLC 21
Doxox WLCWLC 21
DoxWLC
Doxox WLCWLC 32
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 88
Dynamic characteristics (1)• Conductance:
• Linear mode
• Saturation mode
FiDSox
ascDSFiFBgsoxn
cteVD
DD V
CN
VVVCL
WµVIg
g
22
2
)(= Tgsoxn
D VVCLWµ
glin
DTgsoxn
DD IVVL
WCµggsatsat
)²(2
ou 0
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 89
transconductance: device speed linear
« active region »
DSoxnm VL
WCµglin
)(22)(
Tgs
DsatDsatoxnTgsox
nmsat VV
IIL
WCµVVCLWµg
Dynamic characteristics (2)
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 90
HF Caracteristics• Cut off frequencycurrent gain = 1
)-( DGGDgGSin VVCjVCjI
0)-( GDGDgmL
D VVCjVgRV
If we neglect jwRLCgd (small) ( ) GLmGDGSin VRgCCωjI )+1(+=
( ) GMGSin VCCωjI +=
CM : Miller capacitance
GGDL
LmGDGSin V
CRjRgCCjI
1
1
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 91
HF Caracteristics
)+(2=
MGS
mT CCπ
gf
gsmDout VgII ==outin II =
If CM = 0 cut off frequency is maximum (saturation mode):
2max 2)-(
LVVµf TGn
T or (if short chanel and/or vsat ) Lπ
vf sT 2
=max
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 92
• An other figure of merit : power gain =1 oscillation frequency
)(4maxgdTdg
T
CgRff
Ref: (Tsividis)
Rg: gate resistanceRs : negligeable
HF Caracteristics
MOS TRANSISTORS INVERTERSStatics characteristics
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 94
ideal Inverter : definition
• Input voltage: Vin
• Output voltage: Vout
• Inverter thresholdvoltage:Vth=VDD/2
• Logic « 1 » output :• 0<Vin<Vth
• Logic « 0 » output:• Vth< Vin <VDD
Vertical drop in ideal case
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 95
NMOS Inverter: general circuit structure• Load: active (MOS) or passive (resistor)
• « driver »
• Cload :lumped capacitance • Input Voltage: Vin=Vgs• Output Voltage: Vout=Vds
• DC domain: no input current neither output current• Kirchoff’s current law: ILOAD(VL) = IDS(Vin, Vout)
)(),( LLoutinDS VIVVI )(),( LLoutinDS VIVVI
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 96
Inverter: voltage transfer characteristics• With analytical solving
IDS ( Vin ,Vout )=IL( VL ) we foundthe VTC characteristics:
Vout = f ( Vin )• Key voltages:
• VIL : maximum input voltage wich canbe interpreted as a « 0 » logic input
• VIH : minimum input voltage wich canbe interpreted as a « 1 » logic input
• VOL : minimun ouput voltage when the output level is logic « 0 »
• VOH : maximum ouput voltage whenthe output level is logic « 1 »
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 97
Inverters: noise margins
• Interconnexions and gate noise can add parasitics voltage logic faults . We introduce for quantify the noise immunity of the circuit the «noise margins ».
• The noise immunity increases with the noise margins
• Interconnexions and gate noise can add parasitics voltage logic faults . We introduce for quantify the noise immunity of the circuit the «noise margins ».
• The noise immunity increases with the noise margins
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 98
OLILL
IHOHH
VVNM
VVNM
OLILL
IHOHH
VVNM
VVNM
Uncertainty regionmust bereducewe must have VIL~VIH VTC close to ideal inverter
Uncertainty regionmust bereducewe must have VIL~VIH VTC close to ideal inverter
VOH’
VOL’
Inverters: noise margins
• Preceding discussions of inverter static (DC) characteristics show that shape of the VTC in general and noise immunity in particular are very important criteria for design priorities.
For any inverter circuit five critical points (VIL, VIH,…) fully determine the properties.
Accurate estimation of these voltage points have to be determined.
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 99
Inverters: brief summary
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 100
Resistive-load Inverter
• Vin=VGS• Vin=« 1 »: n-MOS is ON at
first order, Drain groundedVout = « 0 »
• Vin=« 0 »: n-MOS is OFF open circuit IL = IDS = 0 Vout= VDD= « 1 »
CL
RL
Input Voltage Range
Operating Mode
Vin<VT0 Cut offVT0<Vin<Vout+VT0 SaturationVin>Vout+VT0 Linear
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 101
-4 -3 -2 -1 0 10
2
4
6
8
10
RL=36 k RL=50 k
DSL
outDDL I
RVVI
DS
L
outDDL I
RVVI
Resistive-load Inverter : VTC
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 102
LnLn
DDTnIH
LnTnIL
Ln
DD
LnTnDD
LnTnDDOL
DDOH
RkRkVVV
RkVV
RkV
RkVV
RkVVV
VV
138
1
2)1(1 2
LnLn
DDTnIH
LnTnIL
Ln
DD
LnTnDD
LnTnDDOL
DDOH
RkRkVVV
RkVV
RkV
RkVV
RkVVV
VV
138
1
2)1(1 2
( good exercise ! )
Resistive-load Inverter : VTC
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 103
• VGS = VDS VGS ‐VT < VDS saturation mode
• Warning : if Vout>VDD‐VTcut‐off VOH=VDD‐VT
Saturated enhancement-type nMOS Inverters :
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 104
The representative points of the load line are given by :
VGS = VDS
The load NMOS isequivalent to a non linearresistance
VDS
VGS
Saturated enhancement-type nMOS Inverters : graphic analysis
Non linear resistance
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 105
VDS1=VDD - VDS2 = 6 - VDS2
VDS1 = 6 – 4 = 2 VID2 = 75 µA = ID1
ID2, µA
VDS2
4
75
75
2
Load
Driver
Saturated enhancement-type nMOS Inverters : graphic analysis
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 106
NMH = VOH ‐VIH = ‐0.2 V <0By changing the ratio W/L, we can improve NM.
75
2
B
Saturated enhancement-type nMOS Inverters : graphic analysis
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 107
Load transistor never in saturation mode: VGS,load – VT,load >VDS,load (1)
VGS,load –VDS,load = VGG – VDD
(1) OK VGG – VDD >VT,load
non saturated load
drawback : 2 separate power supply voltage !!
Inverter with linear enhancement type load
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 108
VGS2 - VDS2 =VGG – VDD = 3V
VDS2 = VGS2 – 3V
T2
T1
VGG = +9V VDD = +6V
VGS1
VDS1
Loadresistance
Inverter with linear enhancement type load
Loadresistance
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 109
VDS1 = 6 – VDS2VDS1 = 6 – VDS2
Inverter with linear enhancement type load
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 110
Driver : enhancement VT,Driver >0Load : depletion VT,load <0 VGS,load =0 >VT,load
VSB,load = VDS,pilote = Vout VT,load sensitive to body effect
FioutFiToutloadT VVVV 22)( 0,
VDD = +6V
Depletion Load NMOS inverter
Vin Vout Driver loadVOL VOH Cut off Linear
VIL ~VOH Saturation Linear
VIH small Linear Saturation
VOH VOL linear saturation
111
VDS2 = 0 V, IDS2 = 0 µA
VDS1 = 6 – 0 = 6 V
VDS2 = 3 V, IDS2 = 22 µA
VDS1 = 6 – 3 = 3 V
Depletion Load NMOS inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 112
out
loadToutloadT
driver
loadoutdriverTIH
outloadTDDoutdriver
loaddriverTIL
OLloadTdriver
loaddriverTOOHdriverTOOHOL
DDOH
dVdV
VVkkVVV
VVVVkkVV
VVkkVVVVV
VV
,,,
,,
2,
2,,
)(2
)(
)()(
out
loadToutloadT
driver
loadoutdriverTIH
outloadTDDoutdriver
loaddriverTIL
OLloadTdriver
loaddriverTOOHdriverTOOHOL
DDOH
dVdV
VVkkVVV
VVVVkkVV
VVkkVVVVV
VV
,,,
,,
2,
2,,
)(2
)(
)()(
( goo
d exercise! )
Depletion Load NMOS inverter
Drawback (compare to enhancement load Inverter): • Additional processing step (VT adjust for load)
Advantages (compare to enhancement load Inverter):• Sharp VTC transition• Better noise margins• Single power supply• Smaller layout area
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 113
• Vin = 0 et Vout = VOH driver is cut off IDS=0. No power
• Vin= VDD et Vout = VOL both transistors ON large current
)()()( linIsatIVVI driverloadDDinDC )()()( linIsatIVVI driverloadDDinDC
2, )(22 OLloadTloadDD
DC VVkV
P 2, )(22 OLloadTloadDD
DC VVkV
P unacceptable
50% of time logic« 1 »
Depletion Load NMOS inverter: power considerations
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 114
C-MOS inverter
• All previous Inverters are based on :• enhancement driver NMOS • a load wich can be a resitor, an enhancement or depletion NMOS.
• Major drawback: in one state (output level « 0 ») DC comsuption or power dissipation nonzero
• New concept /design :
• One enhancement NMOS and one enhancement PMOS (Complementary MOS or CMOS).
• Depending on input Voltage, NMOS is the load and PMOS the driver and vice versa.
• Advantages:• No DC ( steady state) power dissipation ( except leakage current)• Full output voltage swing between VDD and 0• Very sharp VTC transition : very similar to ideal inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 115
C-MOS inverter
S
S
D
D
VGS,p ‐(VDD – Vin)VDS,p ‐(VDD – Vout)VGS,n Vin
VDS,n Vout
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 116
The structure complexity of CMOS is the price to be paid for the improvements achieved in power consumption and the noise margins
C-MOS inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 117
• careful! VTn > 0 et VTp < 0• 1st case: Vin < VTn
• VGS,n < VTn nMOS cut off zero current• VGS,p < VTp pMOS ‘ON ‘ Vout = VDD = VOH
• 2nd case: Vin > VDD + VTp
• VGS,n > VTn nMOS ‘ON ’ zero current• VGS,p > VTp pMOS cutoff Vout = VOL 0
C-MOS inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 118
C-MOS inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 119
Region Vin Vout nMOS pMOS
A < VTn VOH Cut off linear
B VIL « 1 » VOH Saturation linear
C Vth Vth Saturation Saturation
D VIH « 0 » VOL linear Saturation
E > (VDD + VT,p ) VOL linear Cut off
Consumption zone when switching
C-MOS inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 120
LWµCk
kk
k
k
VVk
VV
kVVkVV
V
kVkVVV
V
VVV
oxpp
npR
r
pTDDr
nT
th
R
nToutRpTDDIH
R
nTRDDpToutIL
OL
DDOH
p
)11(
)(1
1)2.(
120
,,
,,
,,
LWµCk
kk
k
k
VVk
VV
kVVkVV
V
kVkVVV
V
VVV
oxpp
npR
r
pTDDr
nT
th
R
nToutRpTDDIH
R
nTRDDpToutIL
OL
DDOH
p
)11(
)(1
1)2.(
120
,,
,,
,,
C-MOS inverter
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 121
Interconnect effects
Cint represents the parasitic capacitance betweenthe two inverters
C-MOS inverter: switching characteristics
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 122
• To simplify the problem, all the capacitances are combined into a unique lumped linear capacitance Cload
• The question of inverter transient response is reduced to finding the charge‐up and charge‐down time of a single capacitance which is charged and discharged through a transistor (NMOS or PMOS).
gpdbndbpgdngdload CCCCCCC int,,,, gpdbndbpgdngdload CCCCCCC int,,,,
Cload
C-MOS inverter: switching characteristics
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 123
• Delay-time or Propagation-time:
PLH : delay time from « 0 » to « 1 ».PHL : delay time from « 1 » to « 0 ».
The average propagation delaytime :
2PLHPHL
P
2PLHPHL
P
C-MOS inverter: switching characteristics
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 124
VOL
VOH
• Output voltage Rise and Fall time:
CDrise
ABfall
LOOHOL
OLHOOL
tttt
VVVVVVVV
)(9.0)(1.0
%90
%10
CDrise
ABfall
LOOHOL
OLHOOL
tttt
VVVVVVVV
)(9.0)(1.0
%90
%10
C-MOS inverter: switching characteristics
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 125
Calculation of delay times:
nDpDCout
load iiidt
dVC ,,
Fall time calculation:•Vin switches from VOL to VOH• nMOS is turned ‘ON’ and itstarts to discharge Cload•pMOS is switched off ID,p 0
nDout
load idt
dVC ,
C-MOS inverter: switching characteristics
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 126
Be carefull : during the switching, operating mode of MOS changes !!
In our case , we have to decompose the calcul in two delay‐times
C-MOS inverter: switching characteristics
NMOS in saturation ?VGSn – VTN < VDS Vin-VTN <Vout VOH – VTn < Vout
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 127
• After few steps
C-MOS inverter: switching characteristics
1)(4
ln2
)(,
,
,
, OLOH
nTOH
nTOH
nT
nTOHn
loadPHL VV
VVVV
VVVk
C
1
)(2ln
2
)( %50
,
,
,
, VVVVV
VVV
V
VVVkC
OH
pTOLOH
pTOLOH
pT
pTOLOHp
loadPLH
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 128
• Other method (more simple, less accurate): average current
C-MOS inverter: switching characteristics
HLavg
OHload
HLavg
HLloadPHL I
VVCI
VC )( %50
),(),(21
%50VVVViVVVViI outOHincOHoutOHincavgHL
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 129
T
avg dttitvT
P0
)().(1
fVCP DDloadavg2 fVCP DDloadavg2
Power dissipation for a gate CMOS during switching : this is the power used to charge and discharge the capacitance Cload.
C-MOS inverter: switching characteristics
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 130
Another source of power consumption: the short‐circuit current, ie a direct pathway from power supply to ground through PMOS and NMOS, both of them being in “ON” state.
C-MOS inverter: switching characteristics
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 131
bibliographic references• S.M. Sze « Physics of semiconductors devices », 2° edition, Wiley and Sons,
New York, 1981• H.Mathieu, « Physique des semi-conducteurs et des composants
électroniques », 4° edition, Masson 1998.• J. Singh, « semiconductors devices : an introduction », McGraw-Hill, Inc
1994• D.A. Neamen, « Semiconductor physics and devices », McGraw Hill, 2003• Y.Taur et T.H. Ning, « Fundamentals of Modern VLSI devices », Cambridge
University Press, 1998.• K.K. Ng, « complete guide to semiconductor devices », McGraw-Hill, Inc,
1995• E. H. Nicollian et J. R. Brews, « MOS Physics and Technology », John Wiley
and Sons, 1982• S.M. Kang et Y. Leblebici, « CMOS Digital Integrated Circuits : analysis and
design », Mc Graw Hill, 2° edition., 1999• J. Millman et A. Grabel, « microelectronique », Mc Graw Hill, 1995• Chenming C. Hu “ Modern Semiconductor Devices for Integrated Circuits”,
Prentice Hall, 2009
Figures and tables mainly from these references
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Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 133