MODERN WP2 Review Meeting preparation

Project Review MeetingCrolles, June 22, 2009

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MODERN WP2 Review Meeting preparation

Task 2.5

[email protected]


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T2.5 Task (2/1)• Task T2.5: PV-aware compact modelling• PV and reliability effects have to be implemented in device compact models to be able to

accurately describe the impact of variability on circuit operation. Implementation methodologies will be worked out and adopted in standard compact modeling.

• Partners: UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNGL• UNGL will develop compact model parameter extraction strategies that capture accurately the

statistical device variability and the statistical aspects of reliability in industrial standard compact models including BSIM, BSIMSOI and PSP. POLI will be developing PV aware compact models in conjunction with the activities carried out in task 2.2, on the basis of the so-called sensitivity approach. The approach will be exploited for the development of quasi-static models (through the implementation of the DC sensitivity concept) and of dynamic models (through the implementation of the large-signal sensitivity concept). The strategy allows very efficient compact models, also accounting for the PV statistics, to be developed, also taking into account the correlation between different input parameters, provided that the input statistics is modelled in closed form. Such models will be deriving their parameters from physics-based simulations or characterizations. The modelling strategy will be mainly applied to the CMOS 45/32nm process, but can be taken into consideration for other technologies like GaAn/AlGaN power or RF devices as well. The compact models will be implemented within the framework of a suitable circuit simulation platform.The aim of the activity of ST-I is to develop a statistical Spice model for the design of complex nano-scale IC starting from TCAD simulations directly linked to process fluctuations due to equipments specifications. In this flow numerical techniques will be introduced in order to reduce the number of technology CAD simulations to be performed to extract the statistical model of a single device fabrication process and as consequence to reduce the computational costs and the time consumed; at the same time techniques will be used to reduce the number of circuit simulations for extraction of the statistical spice model of the IC, taking advantage of multi-objective optimization algorithm for yield analysis in addition AMS will implement reliability effects in device state of the art compact models in order to describe PV for circuit simulation in 0.35um, 0.18um and 0.13um CMOS and HV technologies.


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T2.5 Task (2/2)• Task T2.5: PV-aware compact modelling (cont’)• STF2 will focus on the compact modelling of PV effects in bulk CMOS technology and application

to the simulation of 45nm devices for circuit design. The work goes through classification of variability relevant sources, development of a formal description of process/device variables and associated compact models extensions in order to allow Monte-Carlo circuit simulation. The compact model extensions derived are intended to reflect systematic and random effects observed in a 45nm core CMOS technology at local scale (mismatch), intra-die scale, and interdie, and their layout dependence. NXP’s contribution will address a realistic physics based implementation method to mimic process variations as well as device fluctuations in analog circuit simulation using the PSP compact model. This will initially be done for all device types in a relatively mature 45nm CMOS node using the standard bulk CMOS PSP model. Subsequently, the methodology will be ported, adjusted and refined to more advanced 40-32 and possibly 22nm bulk CMOS nodes. With further scaling it becomes mandatory to come up with viable analytical modeling approaches to efficiently incorporate new physics phenomena and their fluctuations in compact models, including quasi ballistic transport (QTB) features and the impact of variations of the dielectric thickness, channel doping and stress conditions, and with viable compact modeling approaches to reach the best trade-off between accuracy and statistics, including variability. UNET will address these aspects involving new physics for 45/32nm CMOS and for non-volatile memory technologies. NMX will in this task study a viable and effective implementation of an analytical compact model which takes into account PV in NVM logic devices (implementation of the characterization performed in WP2.3) and the impact random dopant, edge roughness, and trap position on scaled NVM cells; joint activities together with UNET are planned. Collaborations with ST-I and NMX are envisioned. Starting from BSIMSOI and an in-house PSP modified thin film device model, LETI will develop statistical modeling of the correlations between model parameters and variability sources for the FDSOI 22nm technologies. This will be used to classify and quantify FDSOI variability sources.


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Compact Modeling: T2.5 Deliverables

Ref Deliverable/ Contributors Due date

D2.5.1 PV-aware circuit-level models for standard CMOS technologies (down to 45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2) , and Non-Volatile-Memory technologies (NMX, UNET), and Discrete Power Device,SiC, GaN/AlGaN technologies (ST-I). State-of-the-art based statistical models, based on hardware and/or TCAD

M18

D2.5.2 Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS)

M30

D2.5.3 PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2)

Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET)

M33

Task Leader: [email protected]


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T2.5 Review• Activity done so far (UNGL)

– Statistical parameter extraction methodology for BSIM and PSP


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T2.5 Review Optimal parameter selection and related

accuracy


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T2.5 Review Optimal parameter selection and related

accuracy

1 32 4

5 6 7


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T2.5 Review Strategy for generating statistical parameters

As extracted

Naïve gaussian

PCA


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T2.5 Review How well this reproduces figures of merit

VT Ion Ioff

DIBL S Delay


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WP2 T2.5 Review• Company/Contributor: POLI/G. Ghione & F. Bonani• Activity done so far

– Progress: post-doc hired, preliminary work initiated– Status: preliminary results of a general methodology to

include doping fluctuations into MOSFET charge-based compact models (sensitivity generators)

• Plan for D2.5.1 deliverable: complete the definition of the compact modeling methodology, validation wrt TCAD

• Issues – Near term (up to D2.5.1 deliverable): Italy contract not

signed yet… – Mean term

• Interaction need with other WP, if any


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T2.1 Review• Activity done so far (ST-I)

- started contacted colleagues who shall provide inputs from fab.- Writing spec need to get contribution and TOK from AMS TUW– Status a bit late – waiting inputs from the person who is going to do the tool (end of June)To start gathering info from fab equipment (silicon based device for now)

• Plan for D2.1.1 deliverable• see spec

• Issues – Near term (for D2.1.1 deliverable) NONE for now– Mean term NONE for now

• Interaction need with other WP,– Need to give info to Asenov for characterization ToK– Need to be in contact Paolo Pavan and t2.5 to clarify work expected from ST-CT– Need info from other people involved in the task 2.1 (AMS TUW)


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WP2 T2.5 Review• Company/Contributor: ST-F, A.Juge

• Activity done so far– ST F is currently focusing on experimental data collection for supporting

the evaluation of PV aware compact models available for bulk planar 45nm CMOS technologies from ST Crolles. Data collection includes Local and Global deviations (as part Task 2.3)

– Next steps are Comparison of Simulation and Experiments, and possibly refinements of 45nm Compact models. This contribution to T2.5 will actually start in Q3 2009

• Plan for D2.5.1 deliverable– On track

• Issues – Near term (up to D2.5.1 deliverable): no issue– Mean term: no issue



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WP2 T2.5 Review• Company/Contributor: NXP• Activity done so far

– new 45 nm transistor matching test chip available; first 45 silicon measured

– first tests done for full (PSP) compact variability model extraction (selection of fluctuating parameter subsets)

– comparison with RDF simulator results on PSP ongoing (formally outside MODERN)

• Plans: – analyze 65-45 trends & select robust parameter set / extraction procedure

– asess usability of mismatch signatures and PCA

• Issues – Near term (for D2.3.1 D2.3.2 deliverable) & Medium term: none

• Interaction: align device simulation tuning procedures (although formally outside MODERN for NXP)


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WP2 T2.5 Review• Company/Contributor: IUNET-MI• Activity done so far

– Progress: study of physically-based models for PV– Status: study of physically-based models for PV

• Plan for D2.5.1 deliverable– Implement models and investigate results

• Issues – Near term (up to D2.5.1 deliverable): None– Mean term



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WP2 T2.5 Review• Company/Contributor: NMX• Activity done so far

– Progress: In this task NMX started to study the bits distributions of nanoscale NVM devices – Status: NMX is developing a physically based compact model approach able to mimic

process variations as well intrinsic fluctuations (i.e. random dopant, random traps,…) and scaling induced disturbs (cross-talk among adjacent cells) on the basis of models proposed in literature.

• Plan for D2.5.1 deliverable– NMX undertakes to dress the proposed analytical models (carried out in task 2.2, see

issues) in a compact-like fashion to be easily introduced in a circuit simulator. Then NMX will run MC simulations and can compare simulation results against the experimental trends captured from the bits distributions of NMV technologies down to 32 nm and beyond. NMX characterization also includes the impact of low frequency noise in the cell readout.

• Issues – NMX requires analytical models that can be probably developed tanks to the possible

cooperation with Glasgow group and IUNET (also inside T2.2) to account for:– Sigma Vth due to Random Dopant Fluctuations (done by Asenov)– Sigma Vth due to Oxide Traps Fluctuations – Line Edge Roughness (both in L and W direction) – Sigma Vth scaling vs W (down to 1-D conduction)– Sigma Vth scaling vs L (down to balistic transport regime)



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WP2 T2.5 Review - summary• Company/Contributor: all active (AMS, LETI?)

• Activity done so far– Status: statistical simulation and parameter extraction methodology started. – Info from AMS and TUW needed– Data collection started for both CMOS and NVM– Physically based models for PV under investigation

• Plan for D2.5.1 deliverable– Complete data collection to compare with simulation results from CM and MC.

• Issues – Nedd to improve interaction– Italian members not yet founded.


MODERN WP2 Review Meeting preparation

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