Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR Topics n Modeling with...
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Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PT Topics Modeling with hardware description languages (HDLs).
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Transcript of Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR Topics n Modeling with...
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Topics
Modeling with hardware description languages (HDLs).
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Hardware description languages
Textual languages for describing hardware:– structure;– function.
Most people today use textual languages rather than schematics for most digital design.– Schematics make poor use of screen space.
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Major HDLs
Two major HDLs designed for simulation:– VHDL;– Verilog.– Similar capabilities but somewhat different
language philosophies. EDIF is a standard netlist format.
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Simulation vs. programming
Simulation tags computations with times.– Must know when signals change to properly
simulate hardware. Simulation is parallel.
– Many statements can execute at the same (simulation) time.
– Just like hardware.
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Types of simulation
Compiled code simulation.– Generate program that evaluates a hardware
block.– Operational details within the hardware block
are lost. Event-driven simulation.
– Propagate events through simulation.– Don’t simulate a block until its inputs change.
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Event-driven simulation
An event is a change in a net’s value.
An event has two components:– value;
– time.timet=35 ns
net1=0 @ 35 ns
net
event
net1
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Propagate events only when nets change value.
If an input change doesn’t cause an output change, no event is propagated.
0
11
0
no event
10
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Timewheel
The timewheel is a data structure in the simulator that efficiently determines the order of events processed.
Events are placed on the timewheel in time order.
Events are taken out of the head of the timewheel to process them in order.
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Timewheel operation
a
b
c1
0
1
a=1 @ 0 ns
netlist timewheel
b=1 @ 1 ns1
c=0 @ 2 ns
0 time
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Order of evaluation
Order of evaluation is important.– Causality must be obeyed.
Evaluating events in the wrong order can cause inaccurate results.
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Order of evaluation example
a
b
c0
0
0
netlist timewheel
b=1 @ 1 ns
1 d=1 @ 2 ns
1d
e1
e=0 @ 4 ns
0
1
time
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Modeling
Structural modeling describes the connections between components.– Netlists are structural models.
Behavioral models describes the functional relationship between inputs and outputs.– Similar to programming but values are events.
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
HDLs language constructs
Must be able to define component types.– A model may be behavioral or structural.
May be able to define abstract data types.– A wire may carry an enumerated value.– Multi-valued simulation may be defined using
abstract data types. May be able to define modules to control
the scope of names.
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Testbenches
A testbench is a model used to exercise a simulation.– Provides stimulus.– Checks outputs.
Testbenches help automate design verification.– Rerun edited module against testbench.– Run models at behavioral, RTL levels against the
same testbench.
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Synthesis subsets
VHDL and Verilog were designed for simulation.
A synthesis subset is:– synthesizable;– produces consistent simulation results.
Different tools may use different synthesis subsets.
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR
Register-transfer synthesis
Most common type of synthesis. Synthesizes gates from abstract RT model.
– Registers are explicit.– Some tools will infer storage elements---be
careful. Optimized for performance, area, power.
