Modern VLSI Design 2e: Chapter 8 Copyright 1998 Prentice Hall PTR Topics n High-level synthesis. n...

Modern VLSI Design 2e: Chapter 8 Copyright 1998 Prentice Hall PTR

Topics

High-level synthesis. Architectures for low power. Testability and architecture.


High-level synthesis

Sequential operation is not the most abstract description of behavior.

We can describe behavior without assigning operations to particular clock cycles.

High-level synthesis (behavioral synthesis) transforms an unscheduled behavior into a register-transfer behavior.


Tasks in high-level synthesis

Scheduling: determines clock cycle on which each operation will occur.

Binding (allocation): chooses which function units will execute which operations.


Functional modeling code in VHDL

o1 <= i1 or i2;

if i3 = ‘0’ then

o1 <= ‘1’;

o2 <= a + b;

else

o1 <= ‘0’

end if;

clock cycle boundary canbe moved to design differentregister transfers


Data dependencies

Data dependencies describe relationships between operations:– x <= a + b; value of x depends on a, b

High-level synthesis must preserve data dependencies.


Data flow graph

Data flow graph (DFG) models data dependencies.

Does not require that operations be performed in a particular order.

Models operations in a basic block of a functional model -no conditionals.

Requires single-assignment form.


Data flow graph construction

original code:

x <= a + b;

y <= a * c;

z <= x + d;

x <= y - d;

x <= x + c;

single-assignment form:

x1 <= a + b;

y <= a * c;

z <= x1 + d;

x2 <= y - d;

x3 <= x2 + c;


Data flow graph construction, cont’d

Data flow forms directed acyclic graph (DAG):


Goals of scheduling and allocation

Preserve behavior - at end of execution, should have received all outputs, be in proper state (ignoring exact times of events).

Utilize hardware efficiently. Obtain acceptable performance.


Data flow to data path-controller

One feasible schedule for last DFG:


Binding values to registers

registers fall onclock cycleboundaries


Choosing function units

muxes allowfunction unitsto be sharedfor severaloperations


Building the sequencer

sequencer requires three states,even with no conditionals


Choices during high-level synthesis

Scheduling determines number of clock cycles required; binding determines area, cycle time.

Area tradeoffs must consider shared function units vs. multiplexers, control.

Delay tradeoffs must consider cycle time vs. number of cycles.


Finding schedules

Two simple schedules:– As-soon-as-possible (ASAP) schedule puts

every operation as early in time as possible.– As-late-as-possible (ALAP) schedule puts

every operation as late in schedule as possible. Many schedules exist between ALAP and

ASAP extremes.


ASAP and ALAP schedules

ASAP

ALAP


Critical path of schedule

Longest path through data flow determines minimum schedule length:


Operator chaining

May execute several operations in sequence in one cycle - operator chaining.

Delay through function units may not be additive, such as through several adders.


Control implementation

Clock cycles are also known as control steps.

Longer schedule means more states in controller.

Cost of controller may be hard to judge from casual inspection of state transition graph.


Controllers and scheduling

functional model:

x <= a + b;

y <= c + d;one state

two states


Distributed control

one centralized controller

two distributed controllers


Synchronized communication between FSMs

To pass values between two machines, must schedule outputof one machine to coincide with input expected by the other:


Hardwired vs. microcoded control

Hardwired control has a state register and “random logic.”

A microcoded machine has a state register which points into a microcode memory.

Styles are equivalent; choice depends on implementation considerations.


Data path-controller delay

Watch out for long delay paths created by combination of data path and controller:


Architectures for low power

Two important methods:– architecture-driven voltage scaling– power-down modes


Architecture-driven voltage scaling

Add extra logic to increase parallelism so that system can run at lower rate.

Power improvement for n parallel units over Vref:– Pn(n) = [1 + Ci(n)/nCref + Cx(n)/Cref](V/Vref)


Power-down modes

CMOS doesn consume power when not transitioning. Many systems can incorporate power-down modes:– condition the clock on power-down mode;– add state to control for power-down mode;– modify the control logic to ensure that power-d

own/power-up don corrupt control state.


Architecture testing

Want to make system as testable as possible with minimum cost in hardware, testing time.

Can use knowledge of architecture to help choose testability points.

May want to modify architecture to improve testability.


Some scan latches are more useful than others

Acyclic register-transfer graphs are easy to test.

Register-transfers with feedback are harder to test - state becomes contaminated during test.

When choosing partial scan registers, choose feedback paths first.


Identifying partial scan opportunities

Construct register graph, which shows connections between registers:– nodes are registers;– edge between two nodes if there is a combinatio

nal path between them. Sequential depth is distance from primary in

put to a node.


Register graph example

machine

register graph


Analyzing register graphs

High sequential depth implies that the register is harder to test.

Registers contained register-graph cycles (FF2-FF3) are hard to test (although self-loops are not hard).

Add partial scan registers to effectively reduce sequential depth of node and its neighbors.


Built-in self test (BIST)

Includes on-chip machine responsible for:– generating tests;– evaluating correctness of tests.

Allows many tests to be applied. Can’t afford large memory for test results -

rely on compression and statistical analysis.


Generating vectors

Use a linear-feedback shift register to generate a pseudo-random sequence of bit vectors:


BIST architecutre

One LFSR to generates test sequence. Another LFSR captures/compresses results. Can store a small number of signatures

which contain expected compressed result for valid system.

Modern VLSI Design 2e: Chapter 8 Copyright 1998 Prentice Hall PTR Topics n High-level synthesis. n...

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