Co-Simulation: Simulink and ModelSim (V.0.1)

Vysakh P Pillai

Department of Electronics and Communication Engineering

Amrita Vishwa Vidyapeetham

This document introduces the basics of a potent co-simulation methodology integrating two

powerful design tools – Simulink and ModelSim.

Software version information

MATLAB:

Version: 7.5.0.342 (R2007b)

August 15 2007

ModelSim:

Version: ModelSim SE 6.3f

Step 1: Invoking ModelSim

Invoke ModelSim from MATLAB environment using the command <vsim('socketsimulink',4449)>

in MATLAB

This sets the port links between ModelSim and MATLAB through socket 4449.

Co-Simulation : Simulink and ModelSim V1.0

Step 2: Compiling the designs and invoking the Simulink link

The following commands will be useful

a) vlib work : Sets up the work library in the present directory

b) vlog <design.v> : compiles the verilog design file

c) vsimulink work.<module1> work.<module2> :simulates the designs and opens require

port connections to Simulink environment

While issuing the vsimulink command, it is preferred to add the ‘-novopt’ switch to

suppress the optimization.

d) quit –sim : quits simulation

e) quit :quits ModelSim

f) add wave /<module name>/* : adds all signals to a wave window.

Code the designs that are to be integrated along with the Simulink blocks for Co-Simulation, compile

them, and invoke the Simulink link for the designs using the vsimulink command

Once invoked, the ModelSim window will look as shown below.

Co-Simulation : Simulink and ModelSim V1.0

Step 3: Invoking Simulink and configuring the ModelSim link

Use the ‘simulink’ command in MATLAB console to invoke Simulink

Open a new design and select the HDL Cosimulation block from the Link for ModelSim library.

Drag and drop the block and double click to invoke the property window.

Set connection method to ‘socket’ and give port number ‘4449’ in the ‘Connection’ tab

Co-Simulation : Simulink and ModelSim V1.0

In the ‘Port’ tab, delete the existing port maps and click ‘auto fill’. In the resulting dialog box, enter

the name of the module you want to invoke into the block. This will automatically list all the I/O

ports in the module. Set the input port sampling time to an appropriate value. (10 maybe)

In the Timescales tab, set the scaling factor to relate the Simulink sample time to the ModelSim

simulation time. ModelSim simulation is driven in terms of ‘Tick’, the resolution of which can be

identified by using the ‘report simulator state’ command.

This also controls the amount of data being generated at the ModelSim end.

The ‘Clocks’ tab can be used to set the clock properties.

Step 4: Adding additional components

Additional blocks can be added to the design along with the HDL module just as any other Simulink

design.

The HDL simulation link is highly data type specific since the manipulations are in the bit level. It also

cannot handle continuous data streams and thus data type is to be carefully set in the blocks that

are connected to the HDL block. Using the ‘inherit: Inherit via back propagation’ option in the signal

attributes tab of the source blocks would be a good option.

Use the appropriate masking blocks to do the type conversions.

For example when connecting the output of a free running counter to an 8 bit HDL inverter, the

counter bits should also be set to 8.The sampling time and conversion values should also be set

properly to avoid loss of data. The output in analog format is illustrated in the screenshot below.

Co-Simulation : Simulink and ModelSim V1.0

The type conversion block will be a valuable resource in this context.

Step 5: Configuring and executing the simulation

Since the HDL block cannot handle continuous data types and associated solver algorithms, the

simulation configurations in Simulink are to be set correspondingly.

In the solver option stab of the configuration parameters menu (Simulation > configuration

parameters), select the options ‘Fixed Step’ and ‘discrete [no continuous states]’ in the ‘type’ and

‘solver’ drop down menus respectively.

Now the simulation is ready to be executed.

Click the run button in Simulink and see the results in the ModelSim wave window.

Example 1: 4 bit counter interface to 8 bit inverter

Design:

Verilog Code:

module inverter (in, out);

input in;

output out;

wire [7:0] in;

wire [7:0] out;

assign out= (~in);

endmodule

Co-Simulation : Simulink and ModelSim V1.0

Simulink Model:

Block configurations:

Free Running Counter

Number of bits : 4

Sampling time : -1

Data type conversion

Output data type : Inherit: Inherit via back propagation

Input and output to have equal : real world value

Round integer calculations towards : Floor

Sampling Time : -1

HDL Cosimulation Block

Ports : Auto Fill from module instance ‘Inverter’

Clocks : None

Time Scale : 1 second in Simulink corresponds to 1s in HDL

Simulator

Connection : Full simulation mode using Socket at port number

4449

Command flow and steps:

MATLAB>> vsim(‘socketsimulink’,4449);

ModelSim>> <Navigate to required working directory where the design files are placed>

ModelSim>> vlib work

ModelSim>> vlog inverter.v

ModelSim>> vsimulink work.inverter -novopt

ModelSim>> add wave /inverter/*

MATLAB>> simulink

<Open a new design file, make the above design, and configure the blocks>

Run the design and observe the output in the ModelSim wave window.

To get the analog output format, right click the signal name and change format to ‘Analog’