Modelling and Analysis of Substrate Noise in Delta Sigma...

DEGREE PROJECT IN INFORMATION AND COMMUNICATION TECHNOLOGY,SECOND CYCLE, 60 CREDITSSTOCKHOLM, SWEDEN 2017

Modelling and Analysis of Substrate Noise in Delta Sigma ADCs

ABU DARDA

KTH ROYAL INSTITUTE OF TECHNOLOGYSCHOOL OF INFORMATION AND COMMUNICATION TECHNOLOGY

Modelling and Analysis of SubstrateNoise in Delta Sigma ADCs

Author:Abu DARDA

Supervisor:Nikola IVANISEVIC

Examiner:Prof. Dr. Ana RUSU

This thesis work has been performed in fulfillment of the requirementsfor the Masters Programme in Embedded Systems

at the

School of Information and Communication TechnologyKTH Royal Institute of Technology

November 11, 2017

Stockholm

TRITA-ICT-EX-2017:193

https://www.kth.se/profile/darda/

https://www.kth.se/profile/nikiva

https://www.kth.se/profile/arusu

https://www.kth.se/en/ict

http://www.kth.se

ii

AbstractModelling and Analysis of Substrate Noise in Delta Sigma ADCs

by Abu DARDA

The rapid development in the semiconductors industry has enabled the placementof multiple chips on a single die. This has helped boost the functionality of modern-day application specific integrated circuits (ASICs). Thus, digital circuits are beingincreasingly placed along-side analog and RF circuits in what are known as mixedsignal circuits. As a result, the noise couplings through the substrate now have anincreased role in mixed-signal ASIC design. Therefore, there is a need to study theeffects of substrate noise and include them in the traditional design methodology.

∆Σ analog-to-digital converters (ADCs) are a perfect example of digital integrationin traditionally analog circuits. ADCs, used to interface digital circuits to an analogworld, are indispensable in mixed-signal systems and therefore set an interestingcase study. A ∆Σ ADC is used in this thesis to study the effects of substratenoise. A background study is presented in the thesis to better understand ∆Σmodulators and substrate couplings. An intensive theoretical background ongeneration, propagation and reception of substrate noise is presented in light ofexisting researches.

System and behavioural level models are proposed to include the effects ofsubstrate noise in the design stages. A maximum decay of 10dB is seen due toinjection of substrate noise system level simulations while a decay of 12dB is seen inbehavioural simulations. A solution is proposed using controlled clock tree delaysto overcome the effects of substrate noise. The solution is verified on both the systemand behavioural levels. The noise models used to drive the studies can further beused in mixed-signal systems to design custom solutions.

Keywords: Analog Mixed Signal Design, Delta Sigma ADC, Substrate Noise,,System Level Modelling, Behavioural Level Modelling

iii

SammanfattningModelling and Analysis of Substrate Noise in Delta Sigma ADCs

by Abu DARDA

Den snabba utvecklingen inom halvledarindustrin har möjliggjort placering av fleramarker på en enda dö. Detta har hjälpt till att öka funktionaliteten hos modernaapplikationsspecifika integrerade kretsar. Sålunda placeras digitala kretsar i allthögre grad parallella och RF-kretsar i de så kallade blandade signalkretsarna.Som ett resultat har bullerkopplingarna genom substratet nu en ökad roll i ASIC-design med blandad signal. Därför finns det behov av att studera effekterna avsubstratbuller och inkludera dem i den traditionella designmetoden.

∆Σ analog-till-digital omvandlare är ett perfekt exempel på digital integration itraditionellt analoga kretsar. ADC, som används för att gränssnitta digitala kretsartill en analog värld, är oumbärliga i blandningssignalsystem och är därför enintressant fallstudie. A ∆Σ arkitektur används i denna avhandling för att studeraeffekterna av substratstörning. En bakgrundsstudie presenteras i avhandlingenför att bättre förstå ∆Σ modulatorer och substratkopplingar. En intensiv teoretiskbakgrund på generering, förökning och mottagande av substratbuller presenteras iljuset av befintliga undersökningar.

System- och beteendemodellmodeller föreslås inkludera effekterna av substratbulleri konstruktionsstadiet. Ett maximalt förfall på 10dB ses på grund av injektion avsubstratbuller på systemnivå medan ett förfall av 12dB ses i beteende simuleringar.En lösning föreslås med hjälp av kontrollerade klockträdfördröjningar för att övervinnaeffekterna av substratbuller. Lösningen är verifierad på både system och beteendenivåer.De brusmodeller som används för att driva studierna kan vidare användas iblandningssignalsystem för att designa anpassade lösningar.

Nyckelord: Analog blandad signaldesign, Delta Sigma ADC, Substrate Noise,Systemnivåmodellering, Behavioralnivåmodellering

iv

AcknowledgementsFirst of all, I would like to thank my examiner Dr. Ana Rusu for giving me an

opportunity to work on such an interesting and challenging project. As a newbie tothe field, gaining experience under a talented research group is all one can hope forand you gave me just that. I highly appreciate the feedback I received throughoutthe thesis-work and am grateful for the patience you have shown.

Next I would like to extend a note of thanks to my supervisor Nikola Ivanisevic.Without your constant guidance and supervision, it would have been a very difficultpath for me. Thanks for making it easier. I would like to thank you once again foranswering all my questions throughout and keeping up with my constant bugging!

I would like to thank the entire Integrated Circuits and Systems group for theirhelp not only during the thesis but also for the courses I took with them.

A special thanks goes to my friends, Aditya Gahlaut, Prashant Sharma and RohitPrasad, for giving me company during our stake-outs at the department. Also, Iwould like to thank Hassan Mahmood , Abhineet Singh Tomar for their help duringthese last few months.

And last but not the least, I would like to thank my family for their unconditionallove and support during my masters degree. A special token of appreciation for mydad who pushed me to follow my dream and go for this career path.

v

Contents

Abstract ii

Sammanfattning iii

Acknowledgements iv

List of Figures vii

List of Tables viii

List of Acronyms ix

List of Symbols x

1 Introduction 11.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Research Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Background Study 42.1 Basics of A/D Conversion: The Ideal ADC . . . . . . . . . . . . . . . . 4

2.1.1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1.2 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 ∆Σ modulation based Converters . . . . . . . . . . . . . . . . . . . . . 62.2.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.2.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2.3 Basic Architecture of a ∆Σ ADC . . . . . . . . . . . . . . . . . . 72.2.4 A Detailed look into ∆Σ Modulation . . . . . . . . . . . . . . . 82.2.5 Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Substrate Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3.1 Effects of Substrate Noise on Mixed Signal ICs . . . . . . . . . . 122.3.2 Substrate Noise Injection in a Mixed Signal IC . . . . . . . . . . 132.3.3 Reception of Substrate Noise in a Mixed Signal IC . . . . . . . . 142.3.4 Effects of Substrate Noise on a ∆Σ ADC . . . . . . . . . . . . . . 152.3.5 Existing solutions to the substrate coupling problem . . . . . . 15

3 System Level Modeling 183.1 Substrate Noise Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.1 Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.1.2 Noise Characterization . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2 System Level Study Results . . . . . . . . . . . . . . . . . . . . . . . . . 30

vi

4 Behavioural Level Modelling 334.1 Substrate Noise Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . 334.2 Behavioural Level Study Results . . . . . . . . . . . . . . . . . . . . . . 34

5 Conclusions 375.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

A Appendix 39A.1 Schematic of the OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40A.2 VerilogA code for Substrate noise generation . . . . . . . . . . . . . . . 41A.3 VerilogA code for OTA with substrate sensitivity . . . . . . . . . . . . . 41

vii

List of Figures

2.1 Ideal ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2 Principle of noise shaping . . . . . . . . . . . . . . . . . . . . . . . . . . 72.3 Delta Sigma ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . 82.4 Basic scheme of a ∆Σ modulator . . . . . . . . . . . . . . . . . . . . . . 92.5 Simplified representation of IC parasitics . . . . . . . . . . . . . . . . . 132.6 Illustration of separate in-chip power lines . . . . . . . . . . . . . . . . 16

3.1 Equivalent circuit for Substrate Coupling . . . . . . . . . . . . . . . . . 183.2 Substrate Noise waveform as per the parameters in [1] . . . . . . . . . 203.3 CT Implementation of Substrate Noise Injection . . . . . . . . . . . . . 213.4 Substrate Noise waveforms for different clock periods. . . . . . . . . . 213.5 Parasitics report from Cadence Virtuoso . . . . . . . . . . . . . . . . . . 223.6 Test-bench for PSRR estimation (Schematic for OTA is shown in

Appendix A.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.7 Simulation set-up for the test-bench . . . . . . . . . . . . . . . . . . . . 233.8 Transient Simulation result . . . . . . . . . . . . . . . . . . . . . . . . . . 243.9 Variation in the differential output due to substrate noise . . . . . . . . 243.10 Magnitude and phase response of the PSRR reported by circuit

simulation in Virtuoso . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.11 Magnitude and Phase response of DT function from eq.(3.9) . . . . . . 263.12 System level model of substrate coupling noise . . . . . . . . . . . . . 263.13 Inclusion of substrate noise in the integrator model . . . . . . . . . . . 263.14 Substrate Noise Characteristics . . . . . . . . . . . . . . . . . . . . . . . 273.15 Noise characteristics for a leading digital clock . . . . . . . . . . . . . . 283.16 Noise characteristics for a lagging digital clock . . . . . . . . . . . . . . 293.17 Noise PSD of a single- bit second-order ∆Σ modulator at an OSR of 128 303.18 SNDR variation with the delay in the analog and digital clocks of the

single-bit second-order modulator . . . . . . . . . . . . . . . . . . . . . 313.19 Noise PSD of the second-order single bit modulator for a delay of 30ns 313.20 SNDR variation with the delay in the analog and digital clocks of the

4-bit second-order modulator . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1 Behavioral model of Substrate noise coupling . . . . . . . . . . . . . . . 334.2 Transient simulation of the behavioral substrate noise block . . . . . . 344.3 Transient simulation of the behavioural substrate noise block . . . . . . 354.4 System performance parameters of the modulator . . . . . . . . . . . . 36

A.1 Amplifier circuit used to implement integrators in the given ADC model 40

viii

List of Tables

3.1 Loop filter coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.2 Second-order modulator parameters . . . . . . . . . . . . . . . . . . . . 30

4.1 Loop filter coefficients in the mixed-signal simulations . . . . . . . . . 344.2 Second-order modulator parameters . . . . . . . . . . . . . . . . . . . . 354.3 Effect of delay between aggressor and sampling clock . . . . . . . . . . 36

ix

List of Acronyms

∆Σ Delta SigmaA/D Analog-to- DigitalADC Analog-to-Digital ConverterAMS Analog Mixed SignalASIC Application Specific Integrated CircuitsCIFB Cascade-of- Integrator -FeedBackCT Continuous-TimeDAC Digital-to-Analog ConverterDR Dynamic RangeDT Discrete-TimeENOB Effective Number Of BitsFOM Figure Of MeritIC Integrated CircuitsLSI Large Scale IntegrationOSR OvertextbfSampling RatioOTA Operational Transconductance AmplifierPDF Probability Distribution FunctionPSRR Power Suplly Rejection RatioRF Radio FrequencyRSB Reduced Supply BounceSINAD Signal to Noise and Distortion RatioSNDR Signal+Noise Distortion RatioSoC System On ChipVLSI Very Large Scale Integration

x

List of Symbols

ε Quantization NoiseN Number of BitsP PowerDR Dynamic RangeENOB Effective Number of bitsOSR Oversampling RatioN Number of bitsfs Sampling frequencyTs Sampling PeriodfBW BandwidthYFS Full-scale ValueSTF Signal Transfer FunctionNTF Noise Transfer FunctionL Order of modulatorfc Corner frequencyω0 Resonance Frequencyβ Frequency of oscillationsχ Damping ConstantG Gain∆T Jitter

1

Chapter 1

Introduction

The idea of having multiple electronic systems on the same substrate was firstconceived in 1950s. As Gordon Moore predicted in the late 60s, the number oftransistors in a chip has doubled every one and a half year [2]. This was later referredto as the Moore Law and the developments in the semiconductor industry havesince then been in compliance with the prediction. Thus, integrated circuits (ICs)have functionally replaced electronic systems that occupied multiple printed circuitboards (PCBs) with some ICs featuring several million gates. The miniaturizationtrend has led the technology from large scale integration (LSI) to very large scaleintegration (VLSI). The continued scaling has made the placement of variousfunctional circuits together possible, thus giving rise to the system on chip (SoC)design methodology. High speed digital circuits are being integrated together withhigh performance analog circuits in a SoC to boost the overall system performance[3]. This has led to many design issues arising that were insignificant only a decadeago. Such trends demand that the design methodology be accompanied by an in-depth understanding of these issues. This thesis attempts to do so by studying theissue of substrate coupling between the analog and digital blocks of a delta sigma(∆Σ) analog to digital converter (ADC).

1.1 Background

Most functions on a modern SoC are implemented with digital circuitry butanalog circuits are still crucial for interfacing with the real world signals. Analogcircuitry is also integrated on the same die as the digital thus giving rise to theappropriately named analog mixed signal (AMS) systems or simply mixed signalsystems. The reduction of cost, size and power dissipation has motivated thedevelopment of highly complex mixed signal systems. A typical mixed signalsystem consists of both noise sensitive analog blocks and noise injecting digitalblocks. This leads to a very unique situation as noise coupling occurs between theaggressor (digital circuits) and the victim (analog circuits) within the system throughthe shared silicon substrate [4]. This phenomenon is termed as substrate coupling.The coupling is generally weak but can still hamper the performance of low-noisecircuits [5].

In mixed signal systems, the fast switching transients at the digital end propagateto the analog circuits through the substrate coupling, thus limiting the achievableanalog precision. As the demands for high speed digital circuits and analogprecision increase for the next generation SoCs, the substrate noise will pose aserious concern in the design methodology [6]. Previous researches in the topichave been able to provide equivalent substrate impedance models using meshes andgreen functions [7–9], experimental circuits for substrate noise generation [1,10,11] ,time domain analysis of switching noise [12] and even experimental measurements

2 Chapter 1. Introduction

and analyses of substrate noise on ICs [13, 14]. A number of noise suppressiontechniques have been proposed and studied in the literature, refer Chapter 2.

However, to actually implement any of these techniques one has to carefullystudy the target mixed signal system and design a custom solution according tothe system requirements. The digital block of the system defines the characteristicsof the noise being generated while the packaging, the underlying circuitry and thesemiconductor technology provide for the coupling transfer function. The effectof this noise has to be studied on the analog circuitry before any suppressiontechnology can be applied to the system. Therefore, there is a need for a moreattentive approach to AMS design methodologies regarding substrate noise.

1.2 Research Problem

Despite the recent trend of replacing analog circuitry by its digital counterparts,there are some aspects that can only be implemented using analog circuits. Analogcircuits are indispensable in electronic systems interacting with the environment andin every such system an ADC is required to establish a communication channelbetween the analog and digital blocks. Thus, a lot of effort has been put into thedevelopment of high resolution ADCs. As relatively large digital circuitry is beingincluded to achieve even higher performance levels, there is a need of awareness ofthe effects of substrate noise on the ADC resolution.

In this thesis, the focus is on the effect of substrate noise on a high resolution ∆ΣADC architecture. A ∆Σ ADC is most susceptible to the noise injected by digitaltransitions occurring during the analog sampling period [15]. In this work, theauthor seeks to model the impact of substrate noise on the resolution of a ∆Σ ADCand identify the critical conditions that degrade the performance.

1.3 Objectives

The goal of this project is to study the corelation between the substrate noise andthe resolution of a ∆Σ ADC. During the thesis project, the effects and suppressiontechniques of substrate noises have been studied. A MATLAB model for thesubstrate noise source is provided alongside a study made on system level models ofthe ADC. The results of this study paved the way for a slightly more realistic studyin the Cadence Design Environment. A Verilog-AMS model for the substrate noisegeneration and injection is developed and used to perform the study in CadenceVirtuoso. This approach has the advantage of making the study less complex as thebehavioural model are used to validate a solution which was tested and verified atthe system level beforehand. The results and models obtained in this thesis can beused for further researches into the topic and help develop a more substrate noiseaware mixed-signal ASIC design methodology.

1.4 Thesis Overview

This thesis work aims to identify and analyse the critical conditions that degradethe performance of a ∆Σ ADC. The findings of the system level study will then beused to perform a Case-Study on a given ADC architecture model.

Chapter 2 provides a background study on the related topics. A brief introductionto ADCs has been provided. Subsequently, ∆Σ are introduced and their operation

1.4. Thesis Overview 3

is explained. A short literature review on the substrate noise coupling has also beenincluded in the chapter.

Chapter 3 presents a system level model for the substrate noise generationalongside its implementation in MATLAB. The MATLAB model for the ADC is alsomade available to the reader and a detailed look into the conducted study is alsopresent.

Chapter 4 entails the circuit level modelling and study on the behaviouralmodels. The results of the study are presented and verified on a given amplifiercircuitry.

Chapter 5 presents the conclusion for the thesis and a discussion on future work.

4

Chapter 2

Background Study

ADCs act as bridges between the analog and digital domains of an electronicsystem. Conceptually, an ADC takes a continuous time and amplitude signal asinput and outputs its discrete time and amplitude equivalent. However, the A/Dconversion process is more complex than that and familiarity with the theoreticalimplications and limitations of the data conversion process is crucial to understandthe working of an ADC. This chapter entails the basics of A/D Conversion and ∆Σmodulation. Modern ADC architectures consist of a number of digital blocks to meetthe high resolution requirements while replacing the constraints on analog blocks.This leads to noise coupling between the digital and analog circuits through theshared substrate. The effects of this noise, aptly named substrate noise, on a ∆Σmodulator architecture is the premise of this thesis and will be studied through thecourse of the thesis. Therefore, a background study on substrate noise, its effects onmixed-signal ICs and existing solutions is included in the last section of the chapter.The sections pertaining to ADCs and ∆Σ modulation draw inspiration from [16–18]and the readers are guided to these texts for a detailed insight into the topics.

2.1 Basics of A/D Conversion: The Ideal ADC

The operation of an ideal ADC can be depicted as a cascade of basic buildingblocks as shown in fig.2.1. First, the analog input xa(t) is passed through the anti-aliasing filter that protects the information content of the signal. It limits bandwidthof the signal and as a result prevents unwanted interference due to aliasing. Theresulting filtered signal xf (t) is sampled at a sampling frequency fs, thus yieldinga discrete time signal xs(n) = xf (nTs), where Ts is the sampling interval (= 1/fs).The N-bit quantizer maps the sampled input onto the closest discrete level out of the2N . Finally, the encoder transforms the digital output Yd(n) of the quantizer to therequired coding scheme.

FIGURE 2.1: Ideal ADC Operation

As seen in fig.2.1, the two most fundamental operations involved in an ADC aresampling and quantization. The sampling performs discretization in time whereasquantization performs amplitude discretization. These two transformations lead to

2.1. Basics of A/D Conversion: The Ideal ADC 5

limitations in the ADC performance and thus the output is distorted compared tothe input signal.

2.1.1 Sampling

A sampler transforms the continuous analog signals into its sampled dataequivalent. Ideally, a sampler yields a sequence of delta functions each equalling thesignal amplitude at the sampling instants. The sampling process imposes limitationson the bandwidth of the analog input. According to the Nyquist Criterion, samplingfrequency (fs) at-least at twice the signal bandwidth fBW to avoid information lossesi.e. fs = 2fBW . Based on the sampling rate ADCs can be broadly classified intoNyquist , oversampling and undersampling ADCs. ADCs operating in accordancewith the Nyquist Criterion are known as Nyquist ADCs. Oversampling ADCs workat a sampling rate higher than the Nyquist frequency while under-sampling ADCshave a lower sampling rate. The different types of ADCs will be covered in detail inthe subsequent sections.

2.1.2 Quantization

The quantizer assigns the sampled data-signal to a discrete level and theoutput value represents the quantization interval input amplitude resides in. Thisintroduces a limitation on the ADC performance as the input signal is accompaniedby an additive white noise, known as quantization noise (error).

Suppose an N-bit quantizer has an input signal varying between ±Yfs/2 andthe full scale output range is Yfs. The quantization step (δ) for this system can becalculated as follows-

δ = Yfs/(2N − 1) (2.1)

Thus, a linear model for the quantizer can be defined as - y = gqx + e(x). Thequantizer’s intrinsic gain gq and error e(x) can lead to the quantizer having differentfull-scale values at the input and outputs i.e. Xfs 6= Yfs. The error, e(x) is anon-linear function of the input x and is bounded by ±δ/2. The input range of[−Xfs/2,Xfs/2] is known as the non-overload range and inputs outside this rangelead to quantizer overload. s

The degradation resulting due to quantization noise is expressed through thein-band quantization power, PQ, which can be written as-

PQ =

∫ fb

−fbSE(f)df =

∫ fb

−fbSE(f)df = δ2/12 (2.2)

The dynamic range (DR) of the ideal ADC can be determined as the ratio of theoutput power at the frequency of an input sinusoid with a maximum amplitude tothe in-band quantization error power.

P outXfs/2∼= (Yfs/2)2/2 ∼= (2Nδ/2)2/2 ∼= 22N−3δ2 (2.3)

The DR of the ideal ADC can thus be calculated as-

DR = P outXfs/2/PQ = 1.5(22N ) (2.4)

DRdB = 6.02N + 1.76 (2.5)

6 Chapter 2. Background Study

Therefore, the dynamic range of an ideal ADC is limited by quantization noise.It is also worth noting that each additional bit in the ideal quantizer results in anincrease of approximately 6dB in the ADC DR.

The aforementioned ideal ADC is also referred to as Nyquist rate ADCs. TheseADCs have a one-to-one correspondence between the input and output samples.Each sample is processed separately without regard to any previous samples and soit is a memory-less converter. As the name implies Nyquist-rate ADCs can have asampling rate as low as the Nyquist criterion i.e. they can be sampled at a rate oftwice the signal bandwidth. In most cases, the linearity and accuracy of Nyquist-rate ADCs is determined by the matching accuracy of the analog components andthe practical conditions restrict the effective number of bits (ENOB).

2.2 ∆Σ modulation based Converters

Most Nyquist-rate ADCs are not suitable to meet high resolution and linearityrequirements. Dual Slope ADCs have the capacity to provide the resolution buthave been deemed too slow for modern signal processing applications. On theother hand, oversampling ADCs have the capability to achieve higher resolutionsat the expense of high latencies. Oversampling ADCs employ higher samplingrates than the Nyquist rate, typically by a factor between 8 and 512. This factor isknown as Oversampling Ratio (OSR). The converter makes use of memory elementsin its structure and each of its output is generated by utilizing all the precedinginputs. The implementation of oversampling ADCs requires a considerable amountof digital circuitry in addition to the already present analog circuits. The accuracyrequirements on the analog circuits is a bit relaxed and thus the high accuracycomes at the price of faster clocks and inclusion of digital circuits. This has led towidespread use of oversampling ADCs in many applications previously dominatedby the Nyquist-rate ADCs. The ∆Σ modulation technique has been recognized tobe one of the most suitable oversampling analog-digital conversion technique fordesigning high resolution ADCs [19].

2.2.1 Oversampling

The key advantage of this technique is that the signal band occupies a smallportion in the Nyquist bandwidth. This makes it possible to perform digital filteringon the signal, as a large fraction of noise lies outside the band of interest. Thusoversampling is used to spread the noise power in a wider spectrum and a filter isemployed to reject the out of band noise, The use of an ideal digital filter after anoversampling ADC effectively reduces the quantization noise power by a factor ofOSR,thus resulting in the following relation -

PQ = (δ2/12) · (1/OSR) (2.6)

The dynamic range (DR) of an oversampled ADC can be written as

DR = P outXfs/2/PQ = 1.5 ·OSR · (22N ) (2.7)

DRdB = 6.02N + 1.76 + 10 log(OSR) (2.8)

2.2. ∆Σ modulation based Converters 7

This implies that oversampling results in an overall increase in the dynamicrange. Another effect of oversampling is on the resolution of the ADC, characterizedby the effective number of bits (ENOB) of the ADC.

ENOB = n+ 0.5 log2(OSR) (2.9)

Thus, the quadrupling the OSR has the potential to increase the ADC resolutionby 1-bit. Thus, the use of oversampling to directly increase the resolution is notpractical. However, oversampling relaxes the design constraints of the anti-aliasingfilter.

2.2.2 Noise Shaping

The real effectiveness of the oversampling technique is achieved by reducing thenoise power in the signal band at the expense of an increase in out of band noise.The out of band noise is not an issue since it is removed by a digital filter.

FIGURE 2.2: Principle of noise shaping

Using a quantizer in a feedback loop, as shown in fig.2.2, can have the requiredeffect of noise shaping on a signal.

(X − Y ·G(z)) ·H(z) + ε = Y (2.10)

The solution of the above equation results yields

Y =X ·H(z)

1 +H(z)G(z)+

ε

1 +H(z)G(z)(2.11)

It can be seen in eq.(2.10) that the signal and quantization noise pass through twodifferent functions-

Y = X · STF (z) + ε ·NTF (z) (2.12)

Here, STF represents the signal transfer function while NTF represents the noisetransfer function. Thus, for achieving good noise shaping the signal transferfunction must be a low pass filter while the noise transfer function must be a highpass filter to achieve noise shaping effect.

2.2.3 Basic Architecture of a ∆Σ ADC

The basic architecture of a ∆Σ ADC is shown in fig.2.3. As can be seen, a ∆ΣADC consists of a ∆Σ modulator and a digital decimation filter. The scheme consistsof four basic blocks namely the anti-aliasing filter, ∆Σ modulator, digital filter , andthe decimator.


• Anti-Aliasing FilterThe anti-aliasing filter performs the same function as in a Nyquist rate ADCi.e. attenuation of the out-of-band signal elements to avoid aliasing. However,the use of oversampling relaxes the requirements on this block.

• ∆Σ ModulatorThe modulator over-samples the input signal and performs a very coarseanalog to digital conversion at the resulting narrow-band signal. A coarsedigital to analog conversion is used as feedback to shape the quantization errorintroduced in the analog to digital conversion i.e. most of the noise is shiftedoutside the signal band.

• Decimation FilterThe decimation filter performs the dual task of filtering and decimation. Itremoves the out-of-band noise provided by the ∆Σ operation.

The decimator brings the sampling rate back to the Nyquist rate. Down-sampling on digital signals is often required as it helps reduce the powerrequirements in digital circuits as it is mostly dependent on clocks. Thisprocess of oversampling coupled with quantization noise shaping and decimatingthe output results in a high precision ADC.

FIGURE 2.3: Delta Sigma ADC Operation

∆Σ ADCs offer many advantages such as their inherent linearity and robustanalog implementations among various others.The main advantage is the relaxationon the analog filter (anti-aliasing filter). This is achieved at the expense of increasedrequirements on the digital filter, which are relatively easier to fulfill. However,the introduction of digital circuitry alongside the ∆Σ modulator makes the ∆ΣADC a mixed signal system in itself. This not only increases the complexity inthe design methodology but also presents new challenges to the designer. Thesubstrate coupling noise is one such factor that is increasingly becoming a concernin high resolution ADCs. A detailed description of ∆Σ modulators and the effectsof substrate coupling are present in the subsequent sub-sections.

2.2.4 A Detailed look into ∆Σ Modulation

The ∆Σ modulator block has the largest influence on the ADC accuracy. Thebasic scheme of the modulator is shown in fig.2.4. It consists of a loop filter H(z), ann-bit quantizer and a negative feedback through a digital to analog converter (DAC).The following section provides an insight into ∆Σ modulation and the reader isguided to [16] for a complete understanding of the topic.


FIGURE 2.4: Basic scheme of a ∆Σ modulator

Assuming the gain of the loop filter, H(z), is large in the signal band and smalloutside of it. Consequently, the error signal i.e. x− y will be insignificant within thesignal band. Discrepancies in x and y are thus pushed to the out-of-band spectrum.

As seen previously, the signal passes through two different transfer functionsnamely the signal transfer function STF and the noise transfer function NTF.

Y (z) = X(z) · STF (z) + ε(z) ·NTF (z) (2.13)

whereX(z) and ε(z) give the z-transforms of the input signal and the quantizationnoise while STF and NTF are given by-

STF (z) =gq ·H(z)

1 + gq ·H(z)(2.14)

NTF (z) =1

1 + gq ·H(z)(2.15)

Since the noise and signal are affected by different transfer function, H(z) can bemodelled so as to avoid signal degradation. Assuming a unity gain in the quantizerand a high loop filter gain within the signal band, the transfer functions can beapproximated as-

STF (z) =gq ·H(z)

1 + gq ·H(z)∼= 1 (2.16)

NTF (z) =1

1 + gq ·H(z)∼=

1

gq ·H(z)<< 1 (2.17)

H(z) is selected so as to achieve the Lth order NTF. The easiest way to do this isto model the loop filter to be an integrator-

H(z) =z−1

1− z−1(2.18)

In this case, the modulator output is as follows-

Y (z) = X(z).z−1 + ε(z).(1− z−1) (2.19)

This modulator is called a first order modulator, in reference to its noise-shapingfunction. Subsequently, the output of an Lth order modulator is-


Y (z) = X(z).z−L + ε(z).(1− z−L) (2.20)

Involving the n-bit quantizer in the calculations, we can derive the followingequation for the dynamic range-

DRdB = 20 log(2N−1)+1.76+(2L+1)10 log(OSR)+(2L+1)10 log((2L+ 1)

π2L) (2.21)

We can see from the equation that the dynamic range of a ∆Σ modulator dependson the modulator order L, oversampling ratio OSR, and number of bits in thequantizer N . Thus, it is crucial to study the effects of each of these quantities onthe ideal performance of a ∆Σ modulator.

• Effect of modulator order, L

Since noise shaping is crucial to a ∆Σ modulator, an increase in L cansignificantly increase the modulator performance. The increase in the dynamicrange due to the modulator order, while keeping OSR and n constant, iscalculated in [16] as-

∆DRdB = 10 log (2L+ 3

2L+ 1) · (OSR

π)2 (2.22)

Thus, high order modulators naturally have better noise shaping capabilities.But stability problems arise with the inclusion of higher order modulators.

• Effect of Oversampling ratio, OSRThe effects of oversampling are same on a ∆Σ modulator as any otheroversampled ADC. Increasing the OSR has the potential to increase thedynamic range as-

∆DRdB = 10(2L+ 1) log(1 +∆OSR

OSR) (2.23)

For a given signal band, increasingOSR corresponds to faster circuit operationand hence increased power requirements.

• Effect of number of bits in quantizer, n

Increasing the number of bits in the quantizer leads to better performance ofa ∆Σ modulator. An inverse proportionality is present between the numberof bits in the quantizer and the power associated to the quantization error. Inpractice, it is assumed an additional bit in the quantizer leads to a 6dB increasein the modulator DR [16].

However, multi-bit modulators make use of a multi-bit DAC in the feedback.Thus, the linearity of the modulators suffers on account of the DAC’s non-linear behavior, and is in fact limited by it.

2.2.5 Design Issues

A number of circuit and architectural design issues limit the performance of a∆Σ ADC. It is important to have an understanding of the limits and solutions to


using these real basic blocks. Some of the issues that affect the performance of anADC are discussed in this section. The reader is recommended to read [18] for thecomplete text on design issues in ∆Σ ADCs.

• Offset of the op-amp (or OTA)

The loop filter in a ∆Σ modulator can be implemented as a cascade of op-ampor OTA based integrators. Any offset present at the first integrator’s op-ampcan is directly digitized. The second integrator’s offset when referred to themodulator input is dc and hence gets canceled by the high pass action of themodulator’s NTF .

• Finite op-amp gain

The finite gain of an op-amp limits the in-band aggressiveness of the NTF.A detailed analysis on the effects of finite op-amp gain on the modulatorperformance indicate that the finite gain has effect on the shape of the NTFmagnitude response below a certain frequency known as corner frequency,fc [18], where-

fc ∼=fs

2π(A0 + 2)(2.24)

The finite gain does not have any effect on the SNR unless fBW >> fc, whichleads to the constraint on the op-amp gain for modulators with a medium OSR.

π(A0 + 2) >> OSR (2.25)

• Finite op-amp Bandwidth

Poles of the transfer function determine the bandwidth and the phase marginof the op-amp. The finite bandwidth of the op-amp leads to a gain errorsimilar to that of the passive elements and has a slight effect on the modulatorresponse [18]. The gain error is given by the following equation, where β is thefeedback factor and τd is the RC constant of the passive network.

εb = Vin · e−Tsβ/2τd (2.26)

This can lead to parasitic poles in both the NTF and STF at high frequency.However, since the parasitic poles are generally at higher frequencies, they donot affect the modulator action.

• Finite op-amp slew rate

Finite slew-rate combined with a finite bandwidth poses a significant limit.Since slewing results in a non-linear transient response, its estimation in the z-domain is not possible, and time-domain simulations must be done. The slewrate error must be shaped by the NTF and then added to the output. Thus, ina second order ∆Σ modulator, the error in the second integrator is less criticalthan the first one.

• Non-Ideal ADC operation

The output of the ADC is a digital equivalent of the input plus the quantization(εq) and ADC errors εADC . Thus, if εq > εADC , the modulator performance isnot affected or negligible affected by non-ideal ADC operation.


• Noise

The performance of an ADC is affected by a number of noise signals arisingfrom intrinsic as well as extrinsic sources. Intrinsic noise, mainly comprised offlicker, thermal and shot noises, is introduced by the active and passive devicesin the circuit. These random device noises are a fundamental limitation inanalog circuits and can be minimized by proper process, device, circuit andtopology selections, and optimum bandwidth designs [4]. Digital switchingnoise and crosstalk are the major extrinsic noise sources. In practice, digitalswitching noise is the dominant source of deterministic noise in mixed-signalICs [20]. Switching noise leads to induction of high frequency analog noisesignals at the substrate, called substrate noise. Substrate noise is highlydeterministic and deleterious as it can get coupled over long distances throughthe substrate to analog circuits.

2.3 Substrate Noise

With the aim of meeting the increased demands for less area and more functionality,the semiconductor industry has been pushing the analog-digital integration inSoC designs to new heights. This has the advantage of getting the best signalprocessioning from both the analog and digital domains and thus a large amountof analog circuitry is being designed alongside the digital circuits. Some ofthe most prevalent problems due to mixed-signal integration are chip/packagecapacitive and inductive coupling, ringing on the RLC tuned circuits that formthe chip/package power supply rails and off-chip drivers and receivers, couplingbetween circuits through the chip substrate bulk, and radiated emissions from thechip/package interconnects. Over the years, substrate coupling effect has attractedthe interest of mixed signal designers and a lot of research has been carried out. Anoverview of some of these researches has been provided in [4]. The problem hasfurther been aggravated in mixed signal circuits with the inclusion of digital blocksin traditionally analog blocks to achieve better performance. Thus, it is necessaryfor today’s mixed signal designers to have an insight into substrate coupling, itseffects, simulation techniques, and design methods adopted to counter the effects.The following subsections attempt to acquaint the reader with the issue of substratecoupling and it is advised to look into [21, 22] for an advanced read.

2.3.1 Effects of Substrate Noise on Mixed Signal ICs

A typical mixed-signal IC has random and deterministic noise sources. Thermal,shot and flicker noises are the general contributors to the random noise levels whilecrosstalk, digital switching etc. are the primary deterministic noise sources. Digitalswitching noise is highly probabilistic and is, therefore, quantifiable in both the timeand frequency domains. In reality, it is one of the dominant source of deterministicnoise in mixed-signal chips [20]. This noise gets coupled to the sensitive analogcircuits through the substrate and modulates their threshold voltages, gains, amongother characteristics.

The significant degradation in the system performances due to parasitics occurringin mixed signal systems is proof to the increasing influence of parasitics in today’smixed signal designs. More often than not, substrate has been credited to providinga medium of parasitic coupling. A negative influence has been seen on integratedcircuits due to substrate parasitics [13–15, 23]. A voltage drop is created by the

2.3. Substrate Noise 13

current flowing to the bulk which in turn affects the device operation. Thewire capacitances between the substrate delays signal transmission to the variouslocations of an IC, giving rise to a parasitic behaviour. In addition, perfect isolationbetween is not the substrate does not provide a perfect isolation between devices isnot achieved due to undesirable crosstalk through the substrate.

Substrate

Int e rconne ct s

BondingWire

AD

AnalogDigitalPackage

On-chip

Off-chip

FIGURE 2.5: Simplified representation of IC parasitics

A very simplistic representation of IC parasitics is provided in the fig.2.5. Thesubstrate block shown in the figure is , in practice, a RC network [27] and thus addsup to the existing parasitic capacitances due to the interconnects. Thus, the first effectof the substrate parasitics on an IC is the addition of its equivalent RC network tothe existing IC parasitics.

Secondly, the substrate also acts as a noise propagating medium between variousareas in an integrated circuit. A considerable amount of noise is present in the digitalinterconnects carrying switching signals as well as the digital power supply lines.This digital noise reaches the sensitive analog cells through the interconnects andthe substrate. With the constant scaling of the feature size, substrate noise couplingis becoming a critical issue in high-end IC design.

There are two distinct aspects to substrate noise. On one hand, substrate isused as a parasitic return path for signals carrying relevant information. Crosstalkhappens in case a sensitive cell is present along this parasitic path is perturbed by thesignal. On the other hand, the bulk conducts AC noise to ground. In this case, theleast resistive path is followed and the noise flow is determined by the distributionof substrate contacts to AC ground.

The occurrence of one or the other type of parasitic effect, together with thetechniques available to reduce the parasitic impact, relates significantly to the kindof wafer and process used for the IC fabrication.

2.3.2 Substrate Noise Injection in a Mixed Signal IC

Any current injected into the substrate causes fluctuations in the substratevoltage. This variation in substrate voltages is called substrate noise and is causedby coupling of switching or noisy signals to the substrate.

In digital CMOS circuits, the noise is caused by three mechanisms:

• Coupling to the digital power supply

The resistive voltage drops due to the parasitic couplings in the power-supplyconnections to the chip and di/dt noise leads to the induction of noise at thedigital power supply. Ringing takes place due to inductance in the power-supply connection and the on-chip capacitance between power and ground.


These effects are also called ground bounce or simultaneous switching noise[24, 24, 25]. Typically, the substrate is connected to the digital ground in everyCMOS gate, which results in a very low resistance path between the two, thusthe noise is also present at the substrate. This noise coupling mechanism isoften the dominant cause of substrate noise.

• Coupling from switching or noisy signals

The switching source and drain nodes of the MOSFETs in the digital circuitsare the second most dominant source of substrate noise. The resulting noisehas the same characteristics as the switching signals on these nodes [21]. Thisis not the case in the digital power supply noise where the switching causes anincrease of the ground voltage inducing a positive noise peak at the substrate.

• Impact ionization in the MOSFET channel

The third source of substrate noise is impact ionization [7,26]. The importanceof impact ionization as a source of substrate noise depends on the technology,especially on the combination of the supply voltage and channel length.

2.3.3 Reception of Substrate Noise in a Mixed Signal IC

A typical mixed signal IC consists of both analog and digital signal processingblocks. The chip typically contains a silicon substrate in which the circuits arerealized. Thus, different areas on the IC are coupled through the substrate. Asmentioned earlier, the excessive switching activity at the digital end induces a noisesignal in the substrate. This noise at the substrate is called substrate noise andgets coupled to the circuits and noise is reflected to each of the circuit present inthe system. The analog circuits are the most sensitive to such noises and suffer asignificant degradation in their performance.

The propagation of switching noise through the substrate is a three-dimensionalphenomenon and the type of substrate plays a significant role in crosstalk effects.Previous research on the topic has revealed that switching noise at heavily dopedsubstrates gets evenly distributed throughout the chip [1]. Substrate noise effectsare also heavily dependent on the layout geometry. It has been observed that theseparation between analog and digital sub-systems suppresses substrate noise up-to a certain limit. This limit is found to be four times the thickness the epitaxiallayer thickness. Further increases in the separation have no effect in reducing thesubstrate noise. An effective way to minimize the substrate noise, proposed in [1], isto reduce the substrate inductance.

In an analog circuit, the substrate is biased via the substrate contact. Thus,any noise at the substrate gets reflected into the analog circuits through couplingto the contact. Further if the analog ground is used to bias the substrate, noise cancouple directly to the ground thus entering the analog circuitry via the power supplyrejection ratio (PSRR). In addition to this, substrate noise is received in the analogcircuits via couplings at interconnects, MOS body effect, and passive components.The disturbances due to the interconnects and MOS body effect can be minimizedby making the circuit differential and matched while that to the passive componentscan be suppressed by using parasitic insensitive architectures.

Using differential circuits is naturally a good solution to minimizing the substratenoise effects in an analog circuit. The differential noise is then mostly provided bythe mismatches in the circuits. Again, making a highly symmetric circuit helps tominimize mismatches.


2.3.4 Effects of Substrate Noise on a ∆Σ ADC

The effects of switching noise on a ∆Σ ADC have been previously studied in[15]. The paper presents an experimental study of the effects of switching noise ona second order ∆Σ modulator. It follows that the substrate noise can significantlylimit the achievable performance in analog circuits. The effects of substrate noise ismaximum when the noise appears in the vicinity of the analog sampling clock. Theeffect persists outside this time-frame due to ringing effect at the inductances.

The capacitive coupling between the noise source and the receptor nodes has ahuge role to play. The peak signal-to-noise-plus-distortion ratio (SNDR) decreasesnon-linearly with an increase in the coupling strength. In the critical timing regionpreceding the sampling interval even a small coupling can lead to drastic drop inthe ADC performance.

The research put forward in the afore-mentioned paper concludes that thedecrease in performance is due to the harmonic distortion, thus implying signaldependent disturbances.

2.3.5 Existing solutions to the substrate coupling problem

The ever-growing demand for smaller feature size high performance mixed-signal SoCs combined with degradation of analog performance due to substratenoise has pushed researchers to come-up with methods to mitigate the problem.There are three basic approaches to counter the issue at hand- reduction of noiseat the source i.e. digital blocks, reduction in the coupling between the analog anddigital sub-domains in a mixed signal system, and lowering the sensitivity of analogcircuits to substrate noise. Each of these approaches will be discussed in detail in thesubsequent sub-sections.

• Suppressing Digital Switching Noise

As mentioned earlier, parasitic couplings in the digital power supply leadto switching noise which in turn couples at the substrate. Several strategieshave been introduced and used to effectively suppress the switching noise. Acommon solution is to lower the effective impedance on the power supplypath, thereby reducing the voltage fluctuations. One way to do this is tohave multiple power supply interconnects for the chip, so as to reduce theeffective inductance [27]. However, just increasing the effective inductanceis not enough to have better noise characteristics but it should also be keptin mind to have opposite currents in adjacent interconnects. Double-bonding(having two bond wires) the on-chip pad to off-chip interconnect is beneficialin reducing the parasitic resistance in the supply path [28]. On-chip decouplingcapacitances have also been shown to have significant effect on decreasing thesupply path impedance [27]. The resonance frequency of the on-chip powersupply lines depends on the effective impedance which can be lowered usinga simple RLC circuit [29]. The RLC values are chosen to place the impedancein the vicinity of the peak and hence counter it. A reduced supply bounce(RSB) CMOS logic has also been proposed to suppress the switching noise indigital circuits [10].

The noise induced in the substrate is a direct consequence of the switchingactivity in the digital circuits. As a result, another common approach forsuppressing the noise is to controlling the unwanted switching activity indigital circuits. In synchronous digital circuits, clocks are the trigger for any


switching activity in the circuit. Division of the entire digital circuit intosub-circuits with a dedicated clock skew can be done for substrate noisesuppression [30]. This technique is effective as each sub-circuit switches atdifferent instants and thus, the net noise coupled at substrate at any giveninstant is lesser in magnitude. The principle of reducing the unwantedswitching can also be applied to the timing of output buffers. This is yetanother simple and effective way to suppress switching noise [27]. Buffersusually have a lot of switching activity and thus are major contributors toswitching noise. Although the switching activity cannot be decreased, timingthe buffers to avoid simultaneous switching is a good idea to reduce noise atthe source.

• Reducing Coupling between Analog and Digital Sub-Domains

Since the digital and analog circuits are realized on the same substrate, it isimpossible to isolate them but the major coupling paths can be modified so asto get a weak noise signal. Since power supply bounces are an important issuein this regard, it is the obvious target for research. Thus, to prevent switchingnoise getting coupled to analog circuits, separate power lines are used for thedigital and analog sub-domains. Even having the same off-chip power sourcebut having separate on-chip power lines effectively reduces the couplingstrength [22]. The concept, as illustrated in fig.2.6, is effective as now the on-chip power and ground lines are coupled to a off-chip point which is weaklycoupled to the power source at high frequencies. Here Z1 − Z4 representthe packaging inductances. Major contributors to this coupling are wirecapacitances, bond inductances, and other stray capacitances/inductances.However, implementing separate power lines leads to critical design issueswhich must be dealt with during the design process [27].

FIGURE 2.6: Illustration of separate in-chip power lines

Another effective method to decouple analog and digital sub-domains is topay special attention to floor-planning. A lot of substrate coupling can beavoided by having a substrate noise aware approach during floor-planningby placing the noisy circuits as far as possible from the sensitive circuits [31].An interesting approach to this is presented in [32], System-C and behaviourallevel description are used to make an early estimate of the noise generationcapacities of various blocks before the floor-planning.


Use of guard bands is another widely researched solution. Guard bandsprovide a low impedance path for substrate currents. Thus, placing theguard bands between the analog and digital circuits can lead to a reduction insubstrate noises. It has been observed that guard bands are effective in lightlydoped substrates but their effect is limited in heavily doped substrates [4].Another interesting approach is presented in [33], where an amplifier is usedas an active guard band to sense and suppress the substrate noise.

• Desensitizing the analog circuits to Substrate Noise

Analog circuits can be made less sensitive to substrate noises by employingdifferential architectures [34]. A symmetric circuit can have a high rejection tosubstrate noises. Ideally a differential architecture should be able to completelyreject substrate noise as the substrate noise has the same effect on differentialpaths. However, upon fabrication the differential paths are not entirelyequal due to component mismatches. Furthermore, the noise injection is notsymmetrical due to asymmetries of the layout with respect to the noise path.As a result, differential architectures can suppress the substrate noise effectsbut cannot eliminate them.

• Planning in the frequency and time domains

Instead of targeting the noise magnitude it is also possible to modify thesubstrate noise frequency domain characteristics. Proper frequency planningcan be done to achieve a noise shaping action on the noise, thus moving thenoise to higher or lower frequencies [27]. Critical frequency components canbe placed outside of the signal band to minimize its effects. The analyses ofsubstrate noise in the frequency domain can be used for frequency planning ofanalog/radio frequency (RF) circuits.

Time-domain analysis of substrate noise can also prove beneficial for mixed-signal IC design. As seen in [15], the sampling instant of an ADC can be placedin a window where the substrate noise is negligible. In a similar fashion,output buffers can be timed to switch when the corresponding substrate noisehas minimal impact on the analog circuits.

18

Chapter 3

System Level Modeling

The primary aim of a system level model is to set the design goals andpriorities for the later design stages. The system specifications are capturedwith MATLAB/Simulink to obtain a precise definition and verification of thespecifications. A system level study also allows the exploration of various architecturesand configurations to meet the system requirements.

In the context of this thesis, a system level block is implemented for the substratenoise injection into existing ∆Σ ADC models. The modeling of substrate noise blocktakes inspiration from [1] while the ADC model has been developed by using thedesign methods introduced in [19].

3.1 Substrate Noise Modeling

The study in [1] presents a simplified schematic, shown in fig.3.1, to analyse theeffects of substrate noise in mixed signal systems. The noise source VSSN refers tothe switching activity leading to noise injection into the substrate. The capacitorCC models the diffusion and interconnect capacitive couplings and switching noisesources such as logic gate outputs, buffer outputs, noisy power lines, etc. Thesubstrate bias impedance is comprised of Cs, Rs, and Ls. VSSN models thesimultaneous switching noise injected by digital circuits while Vsub is the noisereceived at the substrate.

FIGURE 3.1: Equivalent circuit for Substrate Coupling

3.1. Substrate Noise Modeling 19

Upon analysis of the circuit, the transfer function Vsub/Vssn can be easily deducedas-

Vsub(s)

Vssn(s)=

CcCc + Cs

.s(s+ Rs

Cs)

s2 + s.RsCs

+ 1Ls(Cc+Cs)

(3.1)

A resonance is observed in the response at frequency ω0, where

ω0 =

√1

Ls(Cc + Cs)− R2

s

L2s

(3.2)

If magnitude of the response is large, then special steps must be taken to insurethat the switching frequencies and their low-order harmonics do not coincide withthe substrate resonance frequency.

Modelling Vssn as a unit step, the substrate noise can be calculated in the timedomain-

Vsub =Cc

Cc + Cs· e−αt · [cosβt+

α

β· sinβt] (3.3)

where the damping coefficient, α, is given by-

α =Rs2Ls

(3.4)

and the frequency of oscillations, β, is given by-

β =

√1

Ls(Cc + Cs)− R2

s

4L2s

(3.5)

The settling behaviour is governed by the damping factor, ζ, given by-

ζ = α ·√Ls(Cc + Cs) (3.6)

The maximum amplitude of the response occurs at t = 0 and is given by-

V maxsub =

CcCs + Cc

(3.7)

Equations (3.3)− (3.7) provide an insight into how the relative values of Rs, Ls,Cs, and Cc can be chosen to minimize the substrate noise amplitude and settlingtime. These equations show that the substrate noise can be over-damped (ζ > 1) orunder-damped (ζ < 1), as shown in fig.3.2.

Unfortunately, the components presented in the analysis are dependent on theimplementation and cannot be adjusted arbitrarily . Cc is dependent on the processtechnology, circuit performance and functionality considerations. Rs is determinedby size and number of substrate contact diffusions, which are in turn governed bythe latch-up considerations. On-chip decoupling capacitors can be used to increasethe value of Cs and hence decrease the noise magnitude. But this measure leadsto the lowering of the substrate resonance frequency, ω0, as per the relation inequation(3.2). However, if the value ofLs is reduced, both the amplitude and settlingtime can be lowered. Therefore, substrate noise can be minimized by lowering theparasitic inductance of the IC package. In case of a conventional package, Ls can bereduced by connecting multiple bond wires to the substrate contact.

20 Chapter 3. System Level Modeling

FIGURE 3.2: Substrate Noise waveform as per the parameters in [1]

Although simple rules of thumb can be helpful in minimizing substrate noiseeffects, circuit and system simulations that can quantitatively predict substratecrosstalk effects are imperative in mixed-signal design methodology. Thus, a systemlevel block for substrate noise waveform is designed to be included in system-level implementations of ∆Σ ADC architectures. This helps in establishing thevarious factors affecting the substrate coupling and quantifying its effect on ∆Σarchitectures.

3.1.1 Design Process

The first step in the design procedure is to have a functional substrate noiseblock that can be integrated with the existing MATLAB/Simulink models of theADC architectures. Building up on the study presented in [1], a continuous time(CT) block is implemented in Simulink, as shown in fig.3.3a, to capture the noisyswitching activity and produce the resulting noise signal. For the purpose ofsimplicity, the digital noise aggressor has been modeled as an ideal clock havinga 50% duty cycle.

Running CT blocks on SimuLink can be time-consuming if high frequency (HF)signals are present. The simulator decides the time-step depending on the highestfrequency element in the model. The model, shown in fig.3.3b, generates a HF signalof the order of GHz. Therefore, an enable signal is included in the model to controlthe simulation time. The block has is only enabled for 50ns around the clock peaks.The reason behind choosing 50ns can be seen in fig.3.4, where the noise waveformdisappears less than 50ns after the noisy digital peak irrespective of the clock period!However as the clock period approaches 50ns the subsequent stages of the signalstart interfering with each other and lead to ringing. Therefore, the implementedCT block accurately provides the substrate noise signal corresponding to the digitalsignal at its input.

The next step is to define the coupling path of the noise signal into the ∆Σ ADC.The parasitic extraction feature of Cadence Virtuoso is used for this purpose. Theschematic of the OTA , provided in Appendix A.1, used to implement integrators ina second-order ∆Σ modulator is studied. For the given OTA model, the main entrypoints for the substrate noise, as shown in fig.3.5, were found to be through thepower supply lines, the input and outputs nets, and the common-mode feedbacknet. The coupling effects at the input and outputs nets (reported as nets A and B


(a) Substrate Noise Block

(b) Block Implementation

FIGURE 3.3: CT Implementation of Substrate Noise Injection

(a)Tclk=180

ns

(b)Tclk=90

ns

(c)Tclk=45

ns

(d)Tclk=22

ns

FIGURE 3.4: Substrate Noise waveforms for different clock periods.


in fig.3.5) is not considered for the course of the study as the circuit is differentialand highly symmetric in nature. Therefore, the effects of these coupling paths areexpected lead to negligible effects. The common-mode feedback is an importantcoupling path as it connects to off-chip components. However, the scope of theinvestigations has been limited to the layout of the amplifier and thus the effect ofthis path has not been extensively studied.

FIGURE 3.5: Parasitics report from Cadence Virtuoso

The power supply net (reported as VDDA and VSSA in fig.3.5) is treated as theexclusive source of substrate noise. Thus, any noise appearing at the substrate getscoupled to the power/ground lines through a coupling capacitance. The effect ofthis noise at the output can be modelled as a noise signal at the amplifier’s powerlines. Therefore, the substrate noise waveform multiplied by the amplifier PSRR canbe directly added to the integrator output in the Simulink models.


FIGURE 3.6: Test-bench for PSRR estimation (Schematic for OTA isshown in Appendix A.1)

The natural next step is then to estimate the PSRR of the amplifier for inclusionin the system level model. A test-bench, shown in fig.3.6, is implemented to getan insight into the effects of the substrate coupling through the power supply lines.The OTA inputs are set to get it into the operating point and a substrate noise signalis applied to the V DDA input through a coupling capacitance, as per the report infig.3.5. Here again for the sake of simplicity, the digital noise is modeled as a simple50% duty cycle clock signal. The digital noise is translated to its equivalent substratenoise by the sub2blk block, implemented in verilog-A (see Appendix A.2).

FIGURE 3.7: Simulation set-up for the test-bench

The test-bench simulations are set-up as shown in fig.3.7. The DC analysis isdone to verify the DC operating point while the transient analysis is to see thesubstrate noise waveform generated by the verilog code. The AC analysis provides


the magnitude and phase response to get a rough idea of the crucial poles and zeros.Finally, a pole-zero analysis is done to get the system poles and zeros for the PSRR.

FIGURE 3.8: Transient Simulation result

The transient simulation for five clock cycles, in fig.3.8, shows that the substratenoise waveform is preserved and thus the test-bench can be used for further analysis.The noise at the substrate leads to quite random variations in the differential outputswhich can be seen in fig.3.9. It must be taken into note that voltage difference in thisresult is small (of the order of a few fV ), but this simulation is performed transientlyon the circuit level and the degradation is expected to be more pronounced in a morerigorous simulation setup such as Monte-Carlo simulation.

FIGURE 3.9: Variation in the differential output due to substrate noise

An ac analysis is performed on the test-bench and the outputs are set such to seethe magnitude and phase responses of the PSRR. The results can be seen in fig.3.10.The markers depict the two crucial points where the response seems to change.Thus, the AC analysis gives us the expected PSRR response and the MATLAB modelcan be checked against this.


FIGURE 3.10: Magnitude and phase response of the PSRR reportedby circuit simulation in Virtuoso

The last step in the PSRR extraction is the pole-zero analysis. This is done to getthe exact poles and zeros of the PSRR and hence model it in Simulink as a Pole-ZeroSystem. Upon simulation, the analysis reports nearly 50 poles and zeros. However,a number of these poles and zeros are in close vicinity to each other and cancel eachother out! The following transfer function is formed by selecting the appropriatepoles and zeros from the results of the pz analysis.

PSRR(s) =∆Vout

VDD,SSN= G0 ·

(1 + s2π·2.58mHz ) · (1 + s

2π·4.8MHz )

(1 + s2π·3kHz ) · (1 + s

2π·4.75MHz ) · (1 + s2π·7.66MHz )

(3.8)

The transfer function derived in eq.(3.8) is modeled in MATLAB/Simulink as adiscrete-time (DT) block in SimuLink. The poles and zeros of eq.(3.8) are translatedto their discrete counterparts and the following transfer function is obtained.

PSRR(z) == G0 ·(z + e−2π·2.58mHz) · (z + e−2π·4.8MHz)

(z + e−2π·3kHz) · (z + e−2π·4.75MHz) · (z + e−2π·7.66MHz)(3.9)

The gain, G0, in eq.(3.9) is -

G0 = G0 ·(2π · 3kHz)(2π · 4.75MHz) · (2π · 7.66MHz)

(2π · 2.58mHz) · (2π · 4.8MHz)(3.10)

The magnitude and phase response of the DT simulink implementation is,shown in fig.3.11, observed to capture the essence of the actual response shown infig.3.10. This is done to check if the response can be reconstructed after omitting anumber of poles from Cadence pole-zero analysis.


FIGURE 3.11: Magnitude and Phase response of DT function fromeq.(3.9)

Therefore, the final implementation of the system level model of the substratenoise injection is as shown in fig.3.12. An important feature included in the modelis the delay between the digital aggressor clock and analog sampling clock. Thenoise aggressor clock is modelled as an ideal clock as while the analog samplingclock is jittery. Thus, the sampling jitter is taken into consideration. So, the outputis not just a DC offset but it contains pulses of varying amplitudes and time period.The amplitude and time periods depend on the inconsistencies introduced in thesampling instant due to clock jitter.

FIGURE 3.12: System level model of substrate coupling noise

The SimuLink block in fig.3.12 is directly included in the given ADC models byadding it at the output of each integrator in the modulator block as shown in fig.3.13.

FIGURE 3.13: Inclusion of substrate noise in the integrator model


3.1.2 Noise Characterization

Substrate noise, being a random process, cannot be directly incorporated in thecircuit analysis. Therefore, it is imperative to characterize the signal in frequency andtime domains. The instantaneous amplitude of the substrate noise is unpredictable.However, we can compute the probability distribution function (PDF) that gives anindication of how often each value occurs. Therefore, PDF gives information on theamplitude distribution of the time-domain signal.

It is essential to take a look into the spectral density and amplitude distributionof the substrate noise in the ideal situation (i.e. no delay in the analog and digitalclocks). As can be seen in fig.3.14a, the substrate noise spectrum is very flat in theband of interest. Therefore, it most likely adds to the noise floor of the system. Theamplitude distribution is presented in fig.3.14b with the maximum number of binslying in the range of −20mV to 20mV . This implies that all the peaks in the noisesignal are captured at the output.

(a) Spectral Density (b) AmplitudeDistribution

FIGURE 3.14: Substrate Noise Characteristics

The study presented in [15] states that delay in the digital aggressor and analogsampling clocks affects the ∆Σ ADC. It is therefore imperative to take a look intohow this delay affects the amplitude distribution and the spectra of the noise signals.

The effect of having a leading digital clock is seen in 3.15. The noise floorcorresponding to a delay of 5ns is lower than the ideal case presented in 3.14a. Theamplitude distribution in this case gets less diverse and most of the bins are locatedin a pretty negligible voltage range of −3mV to 5mV . As the delay is increased to25ns, the noise floor rises but is still lower than that corresponding to the ideal case.An interesting observation can be made from the PDF. The noise voltage levelsget distributed over a wider range as the delay is increased. Further increasing thedelay to 30ns, the noise floor becomes comparable to the case of no delay. It can beseen from the amplitude distribution that the voltage levels occupy nearly the entirerange as in fig.3.14b. The general trend seems to be as the delay between the twoclocks increases, the noise signal characteristics come closer to the levels shown infig.3.14b. Thus, it can be concluded that having a lead in the digital clock is probablynot an ideal solution to counteract the substrate noise problem.

Upon repeating the same set of observations as in fig.3.15 but for a lagging digitalclock, the results shown in fig.3.16 are obtained. It is interesting to note that theobservations made for a lag of 5ns and 25ns are up-to some extent mirror images


of the observations made for a lead of 25ns and 5ns respectively. It can thereforebe concluded that a lead in the digital clock results in the filtering of most of thenegative peaks in the noise signals. The vice-versa can be said for a lagging digitalclock where a large chunk of positive peaks in the noise signal are filtered out.

(a) δ = −5ns (b) δ = −5ns

(c) δ = −25ns (d) δ = −25ns

(e) δ = −30ns (f) δ = −30ns

FIGURE 3.15: Noise characteristics for a leading digital clock


(a) δ = 5ns (b) δ = 5ns

(c) δ = 25ns (d) δ = 25ns

(e) δ = 30ns (f) δ = 30ns

FIGURE 3.16: Noise characteristics for a lagging digital clock

However, when the lag in the digital clock is increased to 30ns the noise floorbecomes considerably lower. It can also be seen in from the PDF plot that most ofthe signal bins reside in the vicinity of 0V . Thus, having a analog sampling instantbefore the digital clock is potentially a solution to the substrate noise coupling.


3.2 System Level Study Results

The substrate noise block is included in single-bit and multi-bit ADC architecturesbased on second-order cascade-of-integrator-feedback (CIFB) ∆Σ modulator. Theloop-filter coefficients used to model the modulator are present in table 3.1. For adetailed look into the modulator design, please refer to [35].

Coefficient Single-bit Modulator Multi-bit Modulatora1 0.4444 1.9765a2 0.4444 1.0096b3 0.1111 1.002

TABLE 3.1: Loop filter coefficients

The modulator non-idealities have been implemented as in [19]. This modelis used along-side the substrate noise block to impart a realistic operation to thesystem. Table 3.2 shows the parameters selected to model the operation of themodulator.

∆Σ modulator parameter Single-bit Multi-bitJitter Standard Deviation 0.01 0.01Integrator Coefficient, b 0.5 0.5883

Finite gain-bandwidth (1st Integrator), GBW1 (normalised) 3.2554 2.0097Finite gain-bandwidth (2nd Integrator), GBW2 (normalised) 2.0569 2.0221

Slew Rate (1st Integrator), SR1 (normalised) 11.4219 11.4775Slew Rate (2nd Integrator), SR2 (normalised) 4.8183 11.0148

TABLE 3.2: Second-order modulator parameters

The noise PSD of the single-bit modulator obtained without the inclusion ofsubstrate noise in the simulations is plotted along-side the modulator performanceunder the effect of substrate noise in fig.3.17. The plot represents the case whenno delay is present between the two clocks and thus is the worst case scenario inthis context. It can be easily seen that the in-band noise floor has risen above by aconsiderable amount leading to a drop of 10dB in the modulator SNDR.

FIGURE 3.17: Noise PSD of a single- bit second-order ∆Σ modulatorat an OSR of 128

3.2. System Level Study Results 31

As seen in the previous sub-section, the delay in the clocks has considerable effecton the substrate noise spectrum. A similar study is conducted to see the effect of thedelay on the SNDR of the ADC architectures. The system level simulation results,shown in fig.3.18, are similar to the results presented in [15]. Maximum SNDR drop,of nearly 10dB, is seen in the case of synchronized analog and digital clocks (i.e.δ = 0). This is due to the fact that the noise is sampled around its maxima, as can beseen in 3.14b. An interesting result is seen in the case when the delay in the analogand digital clocks is 30ns. The noise floor is higher than when it lags by the samemargin. This can be attributed to the fact that the noise floor at a lag of 30ns is quitelow, as seen in fig.3.15.

FIGURE 3.18: SNDR variation with the delay in the analog and digitalclocks of the single-bit second-order modulator

It can thus be concluded that the substrate noise has less pronounced effect onthe ADC action when a lag of 30ns or more exists between the digital aggressor andanalog sampling clocks. The noise spectrum, seen in fig.3.19, in this case is nearlythe same as in the case of absence of substrate noise.

FIGURE 3.19: Noise PSD of the second-order single bit modulator fora delay of 30ns

A similar effect can be seen for a 4-bit 2nd order ∆Σ architecture. However,as seen in fig.3.20 the variation in this case is bounded by an upper limit of


2dB. Therefore, the effect of substrate noise is more pronounced on the single-bitarchitecture. Again, having a a delay of 30ns in the analog sampling clock leads to astable modulator performance.

FIGURE 3.20: SNDR variation with the delay in the analog and digitalclocks of the 4-bit second-order modulator

33

Chapter 4

Behavioural Level Modelling

In the absence of analog synthesis, analog design is done by manually convertingsystem specifications to circuits. Thus, a behavioural study is conducted to capturethe effect of substrate coupling on the given ∆Σ architecture.

A verification of the system level results, presented in chapter 3, is done usingbehavioural models.

4.1 Substrate Noise Modelling

The substrate noise injection is modelled at the circuit level by building on resultsof the system level design process. The SimuLink models provide the ideal-casescenario of the ADC. To capture circuit non-idealities, mixed signal simulations aredone with the inclusion of substrate noise.

A behavioural model for the substrate coupling is implemented in VerilogAMS. This is done to speed-up the mixed signal simulations which are very timeconsuming. The implementation of substrate noise block is shown in fig.4.1. Thefunctionality is identical to the Simulink model, shown in fig.3.12. An ideal clock ismodelled as source of the noise signal and a jittery clock acts as the analog samplingclock.

FIGURE 4.1: Behavioral model of Substrate noise coupling

Similar to the MATLAB model, the digital aggressor clock is modelled as an idealclock with a finite rise and fall times of 1%. However, the analog sampling clock ismodelled with a nominal jitter of 5%. This ensures that a noise signal is seen as

34 Chapter 4. Behavioural Level Modelling

substrate noise instead of a DC offset, as can be seen in fig.4.2. One advantage of themodel is that it is independent of the rest of the design. As a result it can be directlyused to inject substrate noise in any design, given that its PSRR is known.

FIGURE 4.2: Transient simulation of the behavioral substrate noiseblock

As functionality of the model is verified, it can be used to obtain results atbehavioural level and perform a case-study on the high pass filter operation withthe modified behavioural amplifier model.

4.2 Behavioural Level Study Results

In complex systems, individual building blocks can function properly standalone,but they can produce unsatisfactory results due to various coupling mechanismswhen interconnected. For overcoming this problem, a top-down methodologyis employed for AMS circuits. Mixed-level simulations are established to ensurefunctionality of the overall system. After verification, the behavioural substratenoise block is included in a mixed-signal simulation set-up to see the effects ofsubstrate noise. The system under test has the same specification as the MATLABmodel and thus a confirmation of the results obtained in the system level study isexpected.

For the behavioural level study, the substrate noise block is included in a single-bit ∆Σ ADC architecture. The loop filter coefficients used to model the modulatorare presented in table.4.1

Coefficient Single-bit Modulatora1 2a2 2b3 1

TABLE 4.1: Loop filter coefficients in the mixed-signal simulations

4.2. Behavioural Level Study Results 35

Table 4.2 shows the parameters selected to model the operation of the modulator.These can be used to re-model the system and reproduce the results presented in thesubsequent sections.

∆Σ modulator parameter Single-bitJitter Standard Deviation , ∆τ 0.01

Integrator Coefficient, b 0.5Finite gain-bandwidth (1st Integrator), GBW1 (normalised) 3.2554Finite gain-bandwidth (2nd Integrator), GBW2 (normalised) 2.0569

Slew Rate (1st Integrator), SR1 (normalised) 11.4219Slew Rate (2nd Integrator), SR2 (normalised) 4.8183

TABLE 4.2: Second-order modulator parameters

The spectrum of the behavioural model of the ∆Σ modulator with and withoutthe inclusion of the substrate noise is seen in fig.4.3. This spectrum pertains to thecase when there is no delay in the digital aggressor and analog sampling clocks.

FIGURE 4.3: Transient simulation of the behavioural substrate noiseblock

The drop in SNDR can be seen in fig.4.4, where the SNDR, equivalent to Signal toNoise and distortion ratio (SINAD), is calculated using the spectrum tool in CadenceVirtuoso. A drop of nearly 12dB is seen in this case. The result is in agreement withresults from MATLAB where a SNDR drop of 10dB was observed. The extra 2dB canbe attributed to the more realistic models used in the cadence design environment.

36 Chapter 4. Behavioural Level Modelling

FIGURE 4.4: System performance parameters of the modulator

The next step in the study is to see the effect of clock tree delays on the sensitivityto substrate noise. Since simulations in the Cadence environment take a lot moretime than MATLAB/SimuLink, the spectrum was observed at a limited set of points.These points were decided by identifying crucial points in the system level results.The result is seen in table 4.3, where the SNDR values at different delays is listed.The degradation in SNDR, as observed at behavioural level, is similar to that seen inthe results of system level study in fig.3.18.

Delay SNDR5ns 72.4dB

10ns 73.1dB

20ns 79.2dB

30ns 81.7dB

70ns 82.3dB

TABLE 4.3: Effect of delay between aggressor and sampling clock

As seen in table.4.3, a delay of 70ns is required to get the desired SNDR value.This is in slight contradiction to the results obtained from MATLAB/SimuLinkwhere a delay of 30ns was seen to achieve the desired effect. Another observationwas found that since the verilogA model captures a more circuit-oriented behaviourin contrast to the mathematical behaviour imparted by MATLAB/SimuLink, thesubstrate noise waveform has significant values for nearly 70ns. Therefore, havinga delay of 70ns leads to the sampling instant occurring before the substrate noiseperturbations have appeared at the substrate. Subsequently the SNDR value seesan improvement and returns to its original value. It must be noted that this delayis actually dependent on the values taken to model the substrate noise waveform.Although in the given scenario, the delay is nearly 1% of the clock period it couldbe greater and difficult to implement. Additionally, the clock delay has to beprogrammable so as to overcome the effects of substrate noise in a real-worldsituation.

37

Chapter 5

Conclusions

5.1 Summary

With the ever-changing trends in the electronics industry, the ASIC designmethodology has been a constant work in progress. With the advent of mixed-signal ASICs and their growing demands, the analog-digital integration limits havebeen pushed to new highs. A typical mixed-signal ASIC consists of a number ofanalog and digital blocks on a same die. With technology scaling taking placealong-side the addition of functionality issues related to the complexity in ASICdesign have started to emerge. Substrate noise is one such problem and has beenthe central focus in this thesis-work. As ASICs keep shrinking, the cross-talk, dueto substrate coupling, between analog and digital sub-domains leads to degradationin the overall performance. Through this thesis-work, the author seeks to study theeffects of substrate coupling on a ∆Σ architecture and propose design methods toinclude the effects of substrate coupling in MATLAB/SimuLink and Cadence DesignEnvironments.

The amplifier, shown in A.1, used in the ∆Σ architecture is studied and the mainpath for substrate noise propagation is established to be through the power rails.Building upon this the PSRR is estimated using Cadence Virtuoso, which is in turnused to create MATLAB models for a system level study. It is observed that in theabsence of clock jitter, the substrate noise is seen as a DC offset. A system levelstudy, on single and multi-bit ∆Σ architectures in Simulink, including the effects ofsubstrate coupling along-side those of jitter and switch noises reveals a maximumdecay of 10 dB in the SNDR. It is also seen that the effects of substrate noise can begreatly suppressed by adjusting the clock tree delays in the digital and analog sub-domains. A delay of nearly 30ns in the digital clock nearly counters the substratenoise in this system. The exact value of delay, however, depends on the systemparameters used to define the noise path and overall system.

With the results of the system level study predicting quite a degradation in theSNDR, an attempt is made to replicate the results in Cadence design environment.Following the same approach as in MATLAB, a substrate noise propagation blockis modelled in Virtuoso. However, to keep the simulation times reasonable,behavioural simulations are performed. A maximum decay of 12dB is seen in thiscase and a similar sensitivity to clock tree delays, as in MATLAB, is observed. Thecoherence in results in MATLAB and Virtuoso with the expected results from aprevious study [15] validates the noise models proposed in this work.

The work presented in this thesis demonstrates that substrate noise is a majorsource of degradation in the used ∆Σ architecture. Thus, a need to establish a moresubstrate noise aware design approach to mixed-signal ASIC. The presented noisemodels can be used to further direct research towards a substrate noise aware ASICdesign methodology.

38 Chapter 5. Conclusions

5.2 Future Work

The work presented in this thesis lays foundation for future research in a similartopic. Using the results obtained in this thesis one can assert that substrate noisecauses substantial degradation in the ∆Σ modulator. The presented models capturethe essence of substrate coupling yet are in no way a perfect representation and thereis ample room for improvements.

The noise blocks modelled in MATLAB and Virtuoso consider only the couplingpath intrinsic to the amplifier. Though this is one dominant path, there areother couplings that have not been considered for this work. The common modecorrection path used in given amplifier circuit is one such contributor to substratenoise. Including the effects of this path in the present models would give them amore realistic behaviour.

The simulation results provided in the thesis are obtained at the system andbehavioural levels. Though these results give an idea about the expected systembehaviour, they deviate from the reality. A more intensive simulation technique,such as Monte-Carlo, can be set-up to get a clearer insight into the topic.

The noise aggressor, in this thesis, has been modelled as a clock signal. Althoughthe clock contributes to a lot of substrate noise, owing to its high switching activity,there are other sources as well. A look could be taken into the noise imprintsprovided by different digital signals and how these affect the modulator. Thisconcept can further be extended to be integrated into the analog-digital co-design.Thus, a truly substrate noise aware design methodology can be developed in thismanner.

40 Appendix A. Appendix

Appendix A

Appendix

A.1 Schematic of the OTA

FIGURE A.1: Amplifier circuit used to implement integrators in thegiven ADC model

A.2. VerilogA code for Substrate noise generation 41

A.2 VerilogA code for Substrate noise generation

.module Sub2blk(sub,blk);parameter real Cc = 2.4p;parameter real Cs = 55p ;parameter real Rs = 3 ;parameter real Ls = 1n ;

input sub;output blk;electrical sub, blk, rs;ground gnd;

branch (sub,blk)Cc, (blk,gnd)Cs, (blk,rs)Rs, (rs,gnd)Ls;

analog beginI(Cc) < + Cc ∗ ddt(V(Cc));I(Cs) < + Cs ∗ ddt(V(Cs));V(Rs) < + Rs ∗ I(Rs);V(Ls) < + Ls ∗ ddt(I(Ls));endendmodule

A.3 VerilogA code for OTA with substrate sensitivity

.module OTA(Ainp, Ainn, VDDA, VSSA, CMtap, DYN, Aoutp, Aoutn, Substrate);

input Ainp, Ainn, VDDA, VSSA, CMtap, DYN,Substrate;output Aoutp, Aoutn;

electrical Ainp, Ainn, VDDA, VSSA, Aoutp, Aoutn, CMtap , N, P,Substrate;logic DYN;

parameter real Gain = 100, //dc gainVoff = 0, //input offset//ISR = 7∗1e−6, // slew-rate currenttrise = 20∗1e−9,tfall = 20∗1e−9,tdel = 0,Vsat = 0.2,Dybias = 0.33,Cgnd = 20∗1e−15,Cdif = 20∗1e−15,ISR = 2.6∗1e−6,Rsat = 100;real gm, rout, dVin;real Ip, In/∗, ISR∗/;real Vomax, Vomin, Vpse, Vnse;


real Vimax;real Ipclip, Inclip, dVpmax, dVpmin,dVnmax, dVnmin;real Imax, Gnom, Rnom;real ISRdyn, Gdyn, Rdyn;

initial beginGnom = 2*ISR/(0.04);Rnom = Gain/Gnom;

gm = Gnom;rout = Rnom;Imax = ISR;

Gdyn = 2∗ISR∗Dybias/(0.04);Rdyn = Gain/Gdyn;ISRdyn = ISR∗Dybias;

end

always @(posedge DYN) begin

Gdyn = 2∗ISR∗Dybias/(0.04);Rdyn = Gain/Gdyn;ISRdyn = ISR∗Dybias;

gm = Gdyn;rout = Rdyn;Imax = ISRdyn;end

always @(negedge DYN) begin

Gnom = 2∗ISR/(0.04);Rnom = Gain/Gnom;

gm = Gnom;rout = Rnom;Imax = ISR;end

analog begin

@(initial-step) beginVimax = 0.08; // Vomax = V(VDDA,VSSA)−Vsat;Vomin = V(VSSA)+Vsat;I(N,VSSA) < + 0;I(P,VSSA) < + 0;I(N,Aoutp) < + 0;I(P,Aoutn) < + 0;I(Ainp,VSSA) < + 0;I(Ainn,VSSA) < + 0;

A.3. VerilogA code for OTA with substrate sensitivity 43

end

I(Ainp,VSSA) < + Cgnd∗ddt(V(Ainp,VSSA));I(Ainn,VSSA) < + Cgnd∗ddt(V(Ainn,VSSA));I(Ainp,Ainn) < + Cdif∗ddt(V(Ainp,Ainn));

//normal operationdVin = V(Ainp,Ainn)+Voff;

if(dVin<Vimax) begin

if (dVin<(0−Vimax)) beginIp = Imax;In = 0−Imax;endelse beginIp = −gm∗dVin/2;In = gm∗dVin/2;endend

else beginIp = 0−Imax;In = Imax;end

//output modelingI(N,VSSA) < + transition ( Ip, tdel, trise, tfall);I(N,VSSA) < + (V(N,VSSA)−V(CMtap,VSSA))/(rout);//I(N,VSSA) < + ddt(V(N,VSSA)−V(CMtap,VSSA))∗100∗1e−15;I(N,Aoutp) < + V(N,Aoutp)/Rsat;I(Aoutp,VSSA) < + ddt(V(Aoutp,VSSA))∗100∗1e−15;I(P,VSSA) < + transition ( In, tdel, trise, tfall);I(P,VSSA) < + (V(P,VSSA)−V(CMtap,VSSA))/(rout);//I(P,VSSA) < + ddt(V(P,VSSA)−V(CMtap,VSSA))∗100∗1e−15;I(P,Aoutn) < + V(P,Aoutn)/Rsat;I(Aoutn,VSSA) < + ddt(V(Aoutn,VSSA))∗100∗1e−15;I(P,CMtap) < + V(Substrate)/(2∗rout);I(N,CMtap) < + V(Substrate)/(2∗rout);

Vpse = V(P,VSSA);Vnse = V(N,VSSA);

dVpmax = Vpse − Vomax;dVpmin = Vomin − Vpse;

dVnmax = Vnse − Vomax;dVnmin = Vomin − Vnse;

//voltage limiting


if ( dVpmax >= 0 ) Ipclip = gm∗dVpmax;else if (dVpmin >= 0 ) Ipclip=0−gm∗dVpmin;else Ipclip = 0;if ( dVnmax >= 0 ) Inclip = gm∗dVnmax;else if (dVnmin >= 0 ) Inclip = 0−gm∗dVnmin;else Inclip = 0;I(P,VSSA) < + transition(Ipclip, tdel, trise, tfall);I(N,VSSA) < + transition(Inclip, tdel, trise, tfall);end

endmodule

45

Bibliography

[1] D. Su, M. Loinaz, S. Masui, and B. Wooley, “Experimental results and modelingtechniques for substrate noise in mixed-signal integrated circuits,” IEEE Journalof Solid-State Circuits, no. 4, pp. 420–430, apr 1993. doi: 10.1109/4.210024

[2] G. E. Moore, “Cramming more components onto integrated circuits,” IEEESolid-State Circuits Newsletter, vol. 11, no. 5, pp. 33 –35, 2006. doi: 10.1109/N-SSC.2006.4785860

[3] J. Garcia, “Digitally Enhanced Continuous-Time Sigma-Delta Analogue-to-Digital Converters,” Ph.D. dissertation, School of Inform. and Commun.Technology, KTH Roy. Inst. of Technology, Stockholm, Sweden, 2012. [Online].Available: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-95447

[4] A. Afzali-Kusha, M. Nagata, N. Verghese, and D. Allstot, “SubstrateNoise Coupling in SoC Design: Modeling, Avoidance, and Validation,”Proceedings of the IEEE, vol. 94, no. 12, pp. 2109–2138, dec 2006. doi:10.1109/JPROC.2006.886029

[5] B. Stanisic, N. Verghese, R. Rutenbar, L. Carley, and D. Allstot, “Addressingsubstrate coupling in mixed-mode ICs: simulation and power distributionsynthesis,” IEEE Journal of Solid-State Circuits, vol. 29, no. 3, pp. 226–238, mar1994. doi: 10.1109/4.278344

[6] B. Brandt and B. Wooley, “A 50-MHz multibit sigma-delta modulator for 12-b2-MHz A/D conversion,” IEEE Journal of Solid-State Circuits, vol. 26, no. 12, pp.1746–1756, 1991. doi: 10.1109/4.104165

[7] O. Valorge, C. Andrei, F. Calmon, J. Verdier, C. Gontrand, and P. Dautriche,“A Simple Way for Substrate Noise Modeling in Mixed-Signal ICs,” IEEETransactions on Circuits and Systems I: Regular Papers, vol. 53, no. 10, pp. 2167–2177, oct 2006. doi: 10.1109/TCSI.2006.883172

[8] R. Gharpurey and R. Meyer, “Modeling and analysis of substrate coupling inintegrated circuits,” IEEE Journal of Solid-State Circuits, vol. 31, no. 3, pp. 344–353, mar 1996. doi: 10.1109/4.494196

[9] B. Owens, S. Adluri, P. Birrer, R. Shreeve, S. Arunachalam, K. Mayaram, andT. Fiez, “Simulation and measurement of supply and substrate noise in mixed-signal ICs,” IEEE Journal of Solid-State Circuits, vol. 40, no. 2, pp. 382–391, feb2005. doi: 10.1109/JSSC.2004.841039

[10] M. Nagata, K. Hijikata, J. Nagai, T. Morie, and A. Iwata, “Reduced substratenoise digital design for improving embedded analog performance,” Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEEInternational, pp. 224–225, 2000. doi: 10.1109/ISSCC.2000.839759

http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-95447

46 BIBLIOGRAPHY

[11] E. Charbon, P. Miliozzi, L. Carloni, A. Ferrari, and A. Sangiovanni-Vincentelli,“Modeling digital substrate noise injection in mixed-signal IC’s,” IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18,no. 3, pp. 301–310, mar 1999.

[12] Z. Gan, E. Salman, and M. Stanacevic, “Figures-of-Merit to Evaluate theSignificance of Switching Noise in Analog Circuits,” IEEE Transactions on VeryLarge Scale Integration (VLSI) Systems, vol. 23, no. 12, pp. 2945–2956, dec 2015.doi: 10.1109/TVLSI.2014.2386315

[13] J. Catrysse, “Measured distortion of the output-waveform of an integratedOPAMP due to substrate noise,” IEEE Transactions on ElectromagneticCompatibility, no. 2, pp. 310–312, may 1995. doi: 10.1109/15.385902

[14] Min Xu, D. Su, D. Shaeffer, T. Lee, and B. Wooley, “Measuring and modeling theeffects of substrate noise on the LNA for a CMOS GPS receiver,” IEEE Journalof Solid-State Circuits, no. 3, pp. 473–485, mar 2001. doi: 10.1109/4.910486

[15] T. Blalack and B. Wooley, “The effects of switching noise on an oversamplingA/D converter,” in Proceedings ISSCC ’95 - International Solid-State CircuitsConference, vol. 29, no. 3. IEEE, 1995. doi: 10.1109/ISSCC.1995.535522. ISBN0-7803-2495-1. ISSN 01936530 pp. 200–201,.

[16] F. P.-V. B. D. l. R. J. M. R.-V. Rio, R. del Medeiro, CMOS Cascade Sigma-DeltaModulators for Sensors and Telecom. Dordrecht: Springer Netherlands, 2006.ISBN 978-1-4020-4775-6

[17] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. IEEE,jul 2004, vol. 22, no. 4. ISBN 9780470546772

[18] F. Maloberti, Data Converters. Boston, MA: Springer US, 2007. ISBN 978-0-387-32485-2

[19] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, andA. Baschirotto, “Behavioral modeling of switched-capacitor sigma-deltamodulators,” IEEE Transactions on Circuits and Systems I: FundamentalTheory and Applications, vol. 50, no. 3, pp. 352–364, mar 2003. doi:10.1109/TCSI.2003.808892

[20] N. K. Verghese and D. J. Allstot, “Computer-aided design considerations formixed-signal coupling in RF integrated circuits,” IEEE Journal of Solid-StateCircuits, vol. 33, no. 3, pp. 314–323, 1998. doi: 10.1109/4.661197

[21] Stéphane Donnay; Georges Gielen, Substrate Noise Coupling in Mixed-SignalASICs, 2003rd ed., S. Donnay and G. Gielen, Eds. Boston, MA: Springer US,2003. ISBN 978-1-4020-7381-6

[22] N. K. Verghese, T. J. Schmerbeck, and D. J. Allstot, Simulation Techniques andSolutions for Mixed-Signal Coupling in Integrated Circuits. Boston, MA: SpringerUS, 1995. ISBN 978-1-4613-5942-5

[23] P. Heydari, “Characterizing the effects of the PLL jitter due to substratenoise in discrete-time delta-sigma modulators,” IEEE Transactions on Circuitsand Systems I: Regular Papers, vol. 52, no. 6, pp. 1073–1085, jun 2005. doi:10.1109/TCSI.2005.849118

BIBLIOGRAPHY 47

[24] A. Samavedam, A. Sadate, K. Mayaram, and T. Fiez, “A scalable substrate noisecoupling model for design of mixed-signal IC’s,” IEEE Journal of Solid-StateCircuits, vol. 35, no. 6, pp. 895–904, jun 2000. doi: 10.1109/4.845193

[25] R. Senthinathan and J. L. Prince, “Simultaneous switching ground noisecalculation for packaged CMOS devices,” IEEE Journal of Solid-State Circuits,vol. 26, no. 11, pp. 1724–1728, 1991. doi: 10.1109/4.98995

[26] J. Briaire and K. S. Krisch, “Substrate injection and crosstalk in CMOS circuits,”in Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999, 1999. ISBN0780354435. ISSN 08865930 pp. 483–486.

[27] E. Backenius and Linköpings universitet. Institutionen för Systemteknik,Reduction of substrate noise in mixed-signal circuits, 2007, vol. 39, no. 1094. ISBN9789185715121

[28] C. Schuster, G. Leonhardt, and W. Fichtner, “Electromagnetic simulationof bonding wires and comparison with wide band measurements,” IEEETransactions on Advanced Packaging, vol. 23, no. 1, pp. 69–79, 2000. doi:10.1109/6040.826764

[29] M. Ingels and M. Steyaert, “Design strategies and decoupling techniquesfor reducing the effects of electrical interference in mixed-mode IC’s,” IEEEJournal of Solid-State Circuits, vol. 32, no. 7, pp. 1136–1141, jul 1997. doi:10.1109/4.597306

[30] M. Badaroglu, K. Tiri, S. Donnay, P. Wambacq, I. Verbauwhede, G. Gielen, andH. De Man, “Clock tree optimization in synchronous CMOS digital circuitsfor substrate noise reduction using folding of supply current transients,” inProceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324). IEEE,2002. doi: 10.1109/DAC.2002.1012658. ISBN 1-58113-461-4 pp. 399–404.

[31] S. Mitra, R. Rutenbar, L. Carley, and D. Allstot, “A methodology forrapid estimation of substrate-coupled switching\nnoise,” Proceedings of theIEEE 1995 Custom Integrated Circuits Conference, pp. 129–132, 1995. doi:10.1109/CICC.1995.518151

[32] J. lundgren, “Behavioral level simulation methods for early noise couplingquantification in mixed-signal systems,” Ph.D. dissertation, Electronics DesignDivision,Dept. of Inform. Tech. and Media,Mid Sweden University, Sweden,2005. [Online]. Available: http://miun.diva-portal.org/smash/record.jsf?pid=diva2%3A28466&dswid=5698

[33] K. Makie-Fukuda and T. Tsukada, “On-chip active guard band filtersto suppress substrate-coupling\nnoise in analog and digital mixed-signalintegrated circuits,” 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat.No.99CH36326), pp. 4–7, 1999. doi: 10.1109/VLSIC.1999.797235

[34] Keiko, Kikuchi, and Hotta, “Measurement of digital noise in mixed-signalintegrated circuits,” in Symposium on VLSI Circuits, vol. 31, no. 5. IEEE, 1993.doi: 10.1109/VLSIC.1993.920521. ISBN 4-930813-76-X. ISSN 00189200 pp. 23–24.

[35] L. Di, Y. Yintang, S. Lichun, and W. Xiaofeng, “Design of a high-ordersingle-loop Σ∆ ADC followed by a decimator in 0.18 µm CMOS technology,”

http://miun.diva-portal.org/smash/record.jsf?pid=diva2%3A28466&dswid=5698

http://miun.diva-portal.org/smash/record.jsf?pid=diva2%3A28466&dswid=5698

48 BIBLIOGRAPHY

Journal of Semiconductors, vol. 30, no. 10, p. 105007, 2009. [Online]. Available:http://stacks.iop.org/1674-4926/30/i=10/a=105007

http://stacks.iop.org/1674-4926/30/i=10/a=105007

TRITA TRITA-ICT-EX-2017:193

www.kth.se

Modelling and Analysis of Substrate Noise in Delta Sigma...

Documents

Transcript of Modelling and Analysis of Substrate Noise in Delta Sigma...