Model BasedDesign ofDigital Communication Systems
Transcript of Model BasedDesign ofDigital Communication Systems
Model Based Design of Digital Communication Systems
‐Intro, Organization, Ressources
Prof. Dr.‐Ing. Marcus PuratBeuth Hochschule für Technik Berlin
2019
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• Module Content and Course Objective• Introduction to HW Platform components
– Overview Zync Board ZyBo– Overview Zync 7000– Overview Audio Codec
• Introduction to Workflow (first steps in lab)– Building a Reference Design and Integration into a Simulink‐Model– Generate an I²C Control IP core for audio codec chip configuration– Generate an I²S IP core for audio codec chip data transfer– Implementing a configurable audio filter IP core for signal processing
• Project Description• Course Organization and Assessment
Structure
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Implementation and deployment of complex embeddedsignal processing systems with HW/SW Co‐Design
Module Content
Compiler
Algorithm / Idea All DigitalPlatformwith I/O
SW/HW‐Split and Design
SW: µC, DSP
HW: ASIC, FPGA
Coding /Implementation
C, C++,Java, Python
VHDL,Verilog
Synthesis
Binaries
Bitstream
Programming
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DSP vs. FPGA / SW vs. HWDSP / SW:• 1 or 2 fast array multipliers and accumulator• MAC intensive algorithms (Filter, Correlation, Fourier Transform, …)• Speed only limited by speed of multiplier (with pipelining)• Fixed number representation (fixed MAC core, Floating / Fixed Point)• Typically lower cost than FPGA• Efficient programming (Sequential progr. like sequential processing)• Useful for complex, highly structured (if-then-else) algorithms
FPGA / HW:• Many IO pins for IO connections (e.g. ADC/DAC)• Multiple parallel MAC cells possbile / parallel processing possible• Number representation adaptable to algorithm needs• High-bandwidth algorithms (wireless, video)• Bit-oriented algorithms (error control, cryptography, scrambling, …)• Useful for front-end algorithms (Filtering, CORDIC, DFT), co-processor
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Efficient implementation and deployment of complex systemsusing model‐based design and SW/HW code generators
Module Content
Algorithm / Idea All DigitalPlatformwith I/O
SW/HW‐Split and Design
System Model
• Code Generation• Programming
Deployment
HW in the loop (HIL)
Optimization/Test
Integrated Toolchain (here: Mathworks Simulink)
SW
HW
HW Reference Design incl. I/O
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Model‐Based Design• Common framework for the design process supporting the
complete development cycle– Mathematically modeling a system– Simulating, analyzing and optimizing the system performance– Testing and verifying the system and its interfaces using HW in the
loop– Deployment of the system on a SW/HW‐Platform
• Advantages– Common design environment for communication, data analysis, and
system verification between various (development) groups.– Early location and correction of errors in system design– Design reuse, for upgrades and for derivative systems– Less time‐consuming for implementation and debugging– Less prone to coding errors, very good documentation– Reduced complexity by visual hierarchies of individual design blocks
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Model‐Based Design• Disadvantages
– Porting model between different platforms may be more time consuming (reference designs, coverall approach), and sometimes not possible at all due to missing tool chain support
– Hidden compilation tool chain is causes non‐transparency and difficulties to combat post errors (such as compilation errors)
– Care needs to be taken in real world production environments because of reliance on a given toolchain can with significant rework and possibly compromising engineering approaches.
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Platform
ZyBo (Zync Board) with the Xilinx Zynq 7000 all programmable System‐on‐Chip (AP SoC)
Implementation and deployment of an audio processingsystem on a all programmable digital platform
Course Objective
[Mathworks]
[Digilent]
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Overview Zync 7000 AP SoC
[Xilinx]
References• zync/userguide.pdf
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[Xilinx]
Overview Zync 7000 AP SoC
ARM NEON technology is an advanced SIMD (single instruction multiple data) architecture extension for the ARM Cortex A series. NEON technology accelerates digital signal processing algorithms and functions to speed up audio and video processing applications.
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[Xilinx]
Overview Zync 7000 AP SoC
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• High quality stereo audio codec for portable applications• Stereo 24‐bit analog‐to‐digital and digital‐to‐analog converters• SNR 90‐100 dB• Various configurable sampling rates from 8 kHz to 96 kHz• Programmable gain amplifier PGA
References• codec/datasheet.pdf
Overview Audio Codec SSM2603
[Analog Dev.]
I²CI²S
Analog IN Analog OUT
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Overview Zync Board ZyBo
[Digilent]
ETH
Audio Connectors(Codec on the back)
Logic LEDs and Switches Zync AP SoC
µSD card slotPower Switch
UART/JTAG
References• zybo/ref_manual.pdf• Zybo/zync_book_tutorial.pdf
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Introduction to Workflow
1. Building a Reference Design and Integration into a Simulink‐Model
References• mathworks/Ref_design.html Follow and carry out in practice the
steps to learn how to integrate the SoC in MATLAB• mathworks/AXI.html Read and understand• mathworks/HWSW_codesign.html Follow and carry out in
practice the steps to learn how to integrate the SoC in MATLAB
[Mathworks]
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Introduction to Workflow
2. Generate an I²C Control IP core for audio codec chip configuration
References• mathworks/audio_i2c.html Read and understand
[Mathworks]
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Introduction to Workflow
3. Generate an I²S IP core for audio codec chipdata transfer
References• mathworks/audio_i2s.html Read and understand
[Mathworks]
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Introduction to Workflow
4. Implementing a configurable audio filter IP corefor signal processing
References• mathworks/audio_filter.html Follow and carry out in practice the
steps to learn how to integrate the SoC in MATLAB
[Mathworks]
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Project Description
Switchable 3‐Band parametric equalizer
LP
Bypass
BP
Bypass
HP
Bypass
IN OUT
Shelving Peak Shelving
H [dB]
f
On‐board switch
GLPGBP GHP
fC,LP fC,HPfC,BP
BWLBP
G: Filter Gain, fC,LP/HP: cut‐off frequency, fC,BP: center frequency, BWBP: Bandwidth
LED LED LED
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Dashboard in Simulink
Project Description
Dashboard control via Simulink and Processing System
References• filter/extract_dafx.pdf
G, fC,LP/HP, fC,BP, BWBP
Parametric EQin PL
IN OUT
Filter CoefficientCalculation in PS
Digital Filter Coeff.
Gain Frequency
PC
Zybo / Zync
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• Build project groups with maximum three students per workstation
• Reading and working through workflow introduction in groups, appr. 4‐5 weeks
• Organize project work within groups– Who does what and when?– Split work (theory, model filter, dashboard, …)– Set milestones
• In case of any questions – ask supervisor!
Course Organization
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• Attendance is mandatory every week• Active contribution and engagement in course• Functionality of the System• Documented Model and Sources for proper re‐use• Short report (5‐10 pages) per group about the project including
– describing the theory to convert parameters into filter coefficients– verifying the functionality of both the model and the system deployment
using appropriate measurements and diagrams
• Project deadline: last week of lecture period (CW 5, 2019)• Report to be provided
– by 26 January 2020 for 1st assessment period, or alt.– by 15 March 2020 for 2nd assessment period
Course Assessment