Model 925 Maintenance Manual
93
Model 925 Maintenance Manual o® 1£1eVideo Systems, Inc.
Transcript of Model 925 Maintenance Manual
Model 925 Maintenance
Manual
o® 1£1eVideo Systems, Inc.
TELEVIDEO® 925 VIDEO DISPLAY TERMINAL MAINTENANCE MANUAL
Document 120036-00-A 26 July 1985
Copyright
Copyright (c) 1985 by TeleVideo Systems, Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of TeleVideo Systems, Inc., 550 East Brokaw Road, P.O. Box 6602, San Jose, CA 95150-6602.
Disclaimer
TeleVideo Systems, Inc. makes no representations or warranties with respect to this manual. Further, TeleVideo Systems, Inc. reserves the right to make changes in the specifications of the product described within this manual at any time without notice and without obligation of TeleVideo Systems, Inc. to notify any person of such revision or changesc
TeleVideo is a registered trademark of TeleVideo Systems, Inc.
TeleVideo Systems, Inc., 550 East Brokaw Road, P.O. Box 6602, San Jose, CA 95150-6602 408/971-0255
TABLE OF CONTENTS
1 .
2.
Service and Warranty Information Regional Sales Offices statement of Limited Warranty
Ordering Spare Parts PCB A.ssembly Control Board PCB A.ssembly Control Board Gate PCB A.ssembly Video Monitor PCB ~ssembly Power Supply Detachable Keycaps
Array
3. Installation and User's Guide
4. Theory of Operation Overview Operating Clocks A.ddress Decoding Terminal Memory Display Fundamentals Interrupt Signals Video Generation Communications Data Sheets
5. Schematics
6.
NOTE! Video Monitor/Power Supply schematics are contained in Section 6 of tbis manual.
Video Monitor/Power Supply Video Monitor Tube Specification Shock Hazard Power Supply Video Monitor and Power Supply Modules TR Waveforms and Voltages Power Supply/Video Monitor Schematics
7. Troubleshooting Guide
8. Bulletins and A.ddenda
iii
1-1 1-2 1-3
2-1 2-3 2-5 2-7 2-9 2-11
4-1 4-1 4-2 4-2 4-3 4-4 4-5 4-6
6-1 6-3 6-5 6-6 6-7 6-8 6-9
LIST OF FIGURES
Section 4
4-1 925 control Board Block Diagram
Section 6
1 . 2.
Spar'k Gaps Discharging Voltages
LIST OF TABLES
4-1 925 Memory Map
iv
4-8
6-3 6-5
4-9
SERVICE AND WARRANTY INFORMATION
If your terminal has technical problems, TeleVideo's Technical Support Department will assist you. The toll-free numbers are 800/821-3774 {inside California} or 800/521-4897 (outside California). International customers can telex 4745041. Or you can call your regional sales office, listed in this section.
~ repairs price list is in the last section of this manual.
SERVICE UNDER WARRANTY
TeleVideo products are covered by a limited warranty, found in this section. For service under warranty you must return products to TeleVideo's factory repair facility.
Return Procedures
1. To return a terminal or part for service, call Customer Service for a Return Material ~uthorization (RM~) number.
2. Have the following information ready:
Your name and your company's name, address and telephone number. Give a street address, since freight delivery services do not deliver to a post office box.
Your terminal's model number and serial number.
A brief but accurate description of the problem. If you have more than one problem, list each problem separately. ~ separate RM~ will be issued for each item. Televideo can repair only the problems described- on an RMA.
3. Taq each i tern to be returned wi th the RMA number and your description of the problem. This is especially important if you plan to ship more than one part in the same container. See the Operator's Manual for information about packing the terminal for shipment.
4. Write the RM~ number on the shipping label. TeleVideo will refuse any item delivered without an RMA number on the outside of the shipping carton and return it to the sender~
5. Use the RMA number if you call to ask about your terminal while it is being repaired.
6. If the item is under warranty, it will be returned to you via best way. All express shipments will be at the customer's expense and must be requested when receiving the RMAe
1-1
REGIONAL SALES OFFICES
East 6900 Jericho Turnpike Suite 100 LL Syosset, NY 11791 (516) 496-4777
West 18662 MacArthur Blvd. Suite #107 Irvine, CA 92715 (714) 476-0244
Southcentral 5525 High Point Drive Suite #101 Irving, TX 75062 (214) 258-6776
Southeast 6075 The Corners Parkway Suite #208 Norcross, GA 30092 (404) 447-1231
Northern Europe Dorna House, Guildford Rd., West End Surrey GU249PW England Phone: 011-44-9905-6464 Telex: 858922
1-2
Northeast 1601 Trapelo Road Reservoir Place Waltham, MA 02154 (617) 890-3282
Northwest 550 East Brokaw Road P.O. Box 6602 San Jose, CA 95150-6602 (408) 971-0255
Midwest 1002 E. Algonquin Road Suite #112 Schaumburg, IL 60195 (312) 397-5400
Central Europe Saturnusstraat 25 2132 HB Hoofdorp The Netherlands Phone: 011-31-2503-35444 Telex: 74615 TLVDO NL
Southern Europe 3 bis rue leCorbusier bat. Berne Silic 244 94568 Rungis Cedex, France Phone: 011-33-1-687-34-40 Telex: 205l91F
(TVIVID 205191F)
STATEMENT OF LIMITED WARRANTY
TeleVideo Systems, Inc. ("TeleVideoU) warrants to its distributors, systems houses, end users, and OEMs ("Buyer"), that products manufactured by TeleVideo are free from defects in materials and workmanship. TeleVideo's obligations under this warranty are limited to repairing or replacing, at TeleVideo's option, the part or parts of the products which prove defective in material or workmanship within IS months after shipment by TeleVideo. Buyer must pass along to its initial customer or user ("Customer") a minimum of 12 months' coverage within this IS-month warranty period, provided that Buyer gives TeleVideo prompt notice of any defect and satisfactory proof thereof.
Products may be returned to Buyer only after a Return Material Authorization number (URMA") has been obtained from TeleVideo by telephone or in writing. Buyer will prepay all freight charges to return any products to the repair facility designated by TeleVideo and include the RMA number on the shipping container. TeleVideo will, at its option, either repair the defective products or parts or deliver replacements for defective products or parts on an exchange basis to Buyer, freight prepaid to the Buyer. Products returned to Te1eVideo under this warranty will become the property of TeleVideo. With respect to any product or part thereof not manufactured by TeleVideo, only the warranty, if any, given by the manufacturer thereof, applies.
Exclusions
This limited warranty does not cover losses or damage which occur in shipment to or from Buyer, or are due to, (1) improper installation or maintenance, misuse, neglect, or any cause other than ordinary commercial or industrial application, or (2) adjustment, repair, or modifications by other than TeleVideo-authorized personnel, or (3) improper environment, excessive or inadequate heating or air conditioning and electrical power failures, surges, or other irregularities, or (4) any statements made about TeleVideo's products by salesmen, dealers, distributors or agents, unless confirmed in writing by a TeleVideo officer.
If the firmware or hardware is altered or modified by the Buyer, this firmware and hardware is not covered within this limited warranty and the Buyer bears sole responsibility and liability for that firmware and hardware.
1-3
THE FOREGOING TELEVIDEO LIMITED WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES, WHETHER ORAL, WRITTEN, EXPRESSED, IMPLIED, OR STATUTORY. IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE DO NOT APPLY. TELEVIDEO'S WARRANTY OBLIGATIONS AND DISTRIBUTOR'S REMEDIES HEREUNDER ARE SOLELY AND EXCLUSIVELY AS STATED HEREIN.
TELEVIDEO'S LIABILITY, WHETHER BASED ON CONTRACT, TORT, WARRANTY, STRICT LIABILITY, OR ANY OTHER THEORY, SHALL NOT EXCEED THE PRICE OF THE INDIVIDUAL UNIT WHOSE DEFECT OR DAMAGE IS THE BASIS OF THE CLAIM. IN NO EVENT SHALL TELEVIDEO BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE OF FACILITIES OR EQUIPMENT, OR OTHER INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
SERVICE OUT OF WARRANTY
If your terminal is out of waranty when it needs service, follow the same procedure to receive an RMA. You will be responsible for all shipping costs.
If your company requires a purchase order for out-of-warranty repairs, let us know the purchase order number when you call in. One purchase order may cover several repairs, but we will give each unit its own individual RMA number. This allows us to return each unit quickly without holding up the entire purchase order for one unit.
EXTENDED WARRANTY
TeleVideo offers an Extended Warranty Agreement, which extends the terms of the above-stated Limited Warranty for an additional year. To take advantage of this Extended Warranty, you must sign the Extended Warranty Agreement and return it; together with full payment, to TeleVideo before the Limited Warranty expires. Shippng charges are not included in the Extended Warranty. This is normally the only expense you incur. Please contact the Customer Service department or your sales representative for details. To renew the Extended Warranty for another year, follow the same procedure.
1-4
ORDERING SPARE PARTS
Parts may be ordered by telephone, written p'urcnase order or telex, or through Regional Sales Office electronic bulletin board systems. You may direct orders to the TeleVideo Regional Sales Office in your area or to the TeleVideo Corporate Spare Parts Order Ent~y Department at the following address:
Te1eVideo Systems, Inc. 550 E. Brokaw Road
P.O. Box 6602 San Jose, CA 95150-6602
or call
San \.Jose: CA Watts: u.s. Watts: Telex: Fax:
TWX
408-971-0255 800-821-3774 800-521-4897 474-5041 408-734-1927 or 408-998-2092 910-338-7633
All orders are shipped F.O.B. our designated site.
2-1
PCB ASSEMBLY CONTROL BOARD
Part Number Description Location
120302-00 IC NE555 TIMER 1\46 120358-00 IC 2114ICB RAM 150ns. A41, 42 180000-16 IC ROM CHAR GEN 910 A31 120492-00 IC 6116 RAM 2Kx8 150ns. 1\47 120496-00 IC 6502A MICROPROCESSOR A60 123443-00 IC CRT CNTRL 6845R A59 120530-00 IC SY6551A/l
2-MHz SYN/AMI 1\32, 33 120242-00 IC 74LSOO A3, 28, 55 120416-00 IC 74LS02 A4 120246-00 IC 74S04 1\16 120248-00 IC 74LS04 A27, 35 120348-00 IC 7406 A5 120252-00 IC 74LS08 1\10, 13, 18, 54 120254-00 IC 74LSI0 1\2 120258-00 IC 74LS32 All, 12, 14, 23, 26,
36, 38 120266-00 IC 74LS74 1\1, 6 120268-00 IC 74LS86 A15 120410-00 IC 74LS138 A29 120272-00 IC 74LS139 1\37 120274-00 IC 74LS157 1\56-58 120276-00 IC 74LS163 1\24 120278-00 IC 74LS166 1\30 120280-00 IC 74LS173 A19-21 120282-00 IC 74LS174 1\22 120442-00 IC 74LS244 A43, 51-53 120362-00 IC 74LS245,N8T245N A40 120376-00 IC 74LS273 A44, 45 120290-00 IC 74LS374 A39 120292-00 IC 75188 4X LINE DRVR A25, 34 120294-00 IC 75189A 4X LINE RCVR A9, 17 120315-00 RES CF 1M OHM 1/4W 5% R19 120335-00 RES CF 22 OHM 1/4W 5% R2 120511-00 RES CF 68 OHM 1/4W 5% R3 120513-00 RES CF 270 OHM 1/4W 5% R8 120515-00 RES CF 330 OHM 1/4W 5% R15, 24-26 120517-00 RES CF 470 OHM 1/4W 5% R13 120317-00 RES CF 750 OHM 1/4W 5% R7, 12 120521-00 RES CF 1000 OHM 1/4W 5% R4, 5, 9 120523-00 RES CF 1800 OHM 1/4W 5% R14 120531-00 RES CF 4700 OHM 1/4W 5% Rl, 10, 11, 17, 23,
27 120337-00 RES CF 47K OHM 1/4W 5% R21 120323-00 RES CF 51K OHM 1/4W 5% R16 120413-00 RES PK 4.7K OHM lOP SIP RPl-5 120287-00 CA.P CER .01uF 16V 20% C2, 5, 7, 14-17, 19,
23B, 24-26, 28-30, 33-40, 43-46, 48, 49, 52-55, 60
120289-00 CAP MONO .01uF 50V 10% C6, 27, 47, 50, 51
PCB ASSEMBLY CONTROL BOARD
Part Number
120279-00 120275-00 120273-00 120257-00 120241-00 120291-00 120271-00 120475-00 120527-00 120455-00 120986-02 120986-05 120968-00
120984-01 120984-02 120984-04 120984-00 120979-00 120988-02
180000-31 180000-33
Description
CAP ELEC luF 16V 10% CAP TANT 4.7uF 16V 10% CAP ELEC 10uF l6V 20% CAP ELEC 22uF l5V 20% C~P MICA 10pF 50V 5% CAP CER 330pF 50V 20% CAP TANT 10uF 25V 10% DIODE lN914 RES CF 3300 OHM 1/4W 5% TRAN 2N440l NPN/SILICON CRY 1.8432-MHz CRY l3.6080-MHz SWITCH lOP DIP/20P SIDE ADJ SOCKET 24P IC DIP SOCKET 40P IC DIP SOCKET 28P IC DIP SOCKET l8P IC DIP CONN 4P MOD JK RJll CONN 4P HDR WT (SP W/#2P OUT) IC EPROM SYS PROG 925 IC EPROM SYS PROG 925
Location
C4 Cl, 3 C41, 61 C56-58 C18 C8-13, 20-23, 62-70 C42 CRl, 2 R20 Ql, 2 Yl OPT, Y5 OPT Y2
Sl-3 A31-47-50 A59, 60 A32, 33 A41, 42 PI
P2, 5 }\50 A49
PCB ASSEMBLY CONTROL BOARD GATE ARRAY
Part Number Description Location
120496-00 IC 6502~ MICROPROCESSOR All 123443-00 IC SRT CRT CNTRL 6845R A28 120530-00 IC SY6551A/1 2-MHz
SYN/AMI A4, 5 130181-00 IC GATE ARRAY TELEPRT C A39 180000-31 IC EPROM SYS PROG 925 1\14 180000-33 IC EPROM SYS PROG 925 A15 120492-00 IC 6116 STAT RAM 150ns. A32 180000-16 IC ROM CHAR GEN 910 A17 120358-00 IC 2114-ICB RAM 150ns. A9, 10 120242-00 IC 74LSOO 1\35 120246-00 IC 74S04 A40 120248-00 IC 74LS04 A36 120252-00 IC 74LS08 A8, 37 120258-00 IC 74LS32 A24, 30, 42, 43 120266-00 IC 74LS74 A7 120272-00 IC 74LS139 A38 120274-00 IC 74LS157 A20-22 120278-00 IC 74LS166 A12 120290-00 IC 74LS374 A18 120292-00 IC 75188N
4X LINE DRIVER 1\16, 23 120294-00 IC 75189A
4X LINE RECEIVER 1\1, 2 120302-00 IC NE555 TIMER A6 120348-00 IC 7406 A31 120362-00 IC 74LS245, N8T245N A19 120376-00 IC 74LS273 A26, 27 120410-00 IC 74LS138 A13 120442-00 IC 74LS244
8X BFR/L DRVR/L RCV A3, 29, 34, 41 120276-00 IC 74LS163 4-BIT CNTR 1\25 120345-00 RES CF 33 OHM 1/4W 5% R9 120513-00 RES CF 270 OHM 1/4W 5% R5 120515-00 RES CF 330 OHM 1/4W 5% R22-24, 27 120517-00 RES CF 470 OHM 1/4W 5% R28 120521-00 RES CF 1000 OHM 1/4W 5% R7, 11, 16 120523-00 RES CF 1800 OHM 1/4W 5% R26 120527-00 RES CF 3300 OHM 1/4W 5% R18 120531-00 RES CF 4700 OHM 1/4W 5% R3, 4, 10, 12-15, 21 120315-00 RES CF 1M OHM 1/4W 5% R20 120317-00 RES CF 750 OHM 1/4W 5% R6, 25 120323-00 RES CF 51K OHM 1/4W 5% R2 120335-00 RES CF 22 OHM 1/4W 5% Rl 120337-00 RES CF 47K OHM 1/4W 5% R19 120341-00 RES CF 10K OHM 1/4W 5% R8 120413-00 RES PK 4.7K OHM lOP SIP RPI-4 120241-00 CAP MICA 10pF 50V 5% C31 120271-00 CAP TANT 10uF 25V 10% C32 121969-00 C1\P MYLAR .001uF
50V (OPC) C34
PCB ASSEMBLY CONTROL BOARD GATE ARRAY
Part Number Description Location
120251-00 CAP MICA 150pF 500V 1% C35
120257-00 CAP ELEC 22uF 16V +20% C24-26 120273-00 CAP ELEC 10uF 16V 20% C28, 30 120275-00 CAP TANT 4.7uF 16V 10% C18 120279-00 CAP ELEC 1uF 16V 10% C18A, 33 120287-00 CAP CER .01uF 16V 20% UNMARKED C20 120289-00 CAP MONO .01uF 50V 10% C27 120293-00 CAP MONO 330pF 100V 20% Cl-17, 19
UNMARKED 120301-00 CAP CER .1uF 50V 10% C29 120475-00 DIODE 1N914 CRl, 2 120455-00 TRAN 2N4401 NPN/SI Ql, 2 120986-02 CRY 1.8432-MHz Y1 (OPT. ) , Y3 120986-05 CRY 13.6080-MHz Y2 121754-00 TAPE FOAH DBL/S
1/16 x 1/4 11 WD Yl (OPT.) , Y2, Y3 120968-00 SWITCH lOP DIP/20P
SIDE ADJ SW-1-3 120984-00 SOCKET 18P IC DIP XA9, 10 120984-01 SOCKET 24P IC DIP XA14, 15, 17, 32, 33 120984-02 SOCKET 40P IC DIP XAl1, 28, 29 120984-04 SOCKET 28P IC DIP XA4, 5 121746-01 SOCKET 16P IC DIP
LO PROF XP6 121653-00 CONN 25P D-SUB MTL P3, 4 120979-00 CONN 4P MOD JK RJll PI 120988-02 CONN 4P HDR WT
(5PW/#2P OUT) P2, 5
2-6
PCB ASSEMBLY VIDEO MONITOR
Part Number
120257-00 120273-00 120275-00 120289-00 120305-00 120309-00 120321-00 120531-00 120337-00 120339-00 120377-00 120383-00
120387-00 120391-00 120395-00 120513-00 120515-00 120517-00 120531-00 121771-00 121776-00 121777-00
121778-00
121779-00
121801-00 121802-00 121803-00 121860-00 121862-00 121863-00 121864-00 121959-00 121960-00
120261-00 121961-00 121962-00 121967-00 121968-00
121970-00
121971-00
121970-00 121973-00
Description
CAP ELEC 22uF 16V +20% CAP ELEC 10uF 16V 20% CAP TANT 4.7uF 16V 10% CAP MONO .01uF 50V 10% CAP MONO .039uF 50V 5% CAP CER 1.0pF 1KV SG RES CF lOOK OHM 1/4W 5% RES CF 4.7K OHM 1/4W 5%
Location
C203 C201 C202, C503 C307 SG501 R202 R208
204
RES CF 47K OHM 1/4W 5% R209, 505 RES CF 150 OHM 1/4W 5% R211 RES CF 47 OHM 1/4W +/-5% R501 RES CF 2.7K OHM 1/4W +/-5% RES CF 2.2K OHM 1/4W 5% RES CF 6.8K OHM 1/4W 5% RES CF 56K OHM 1/4W 5% RES CF 270 OHM 1/4W 5% RES CF 330 OHM 1/4W 5% RES CF 470 OHM 1/4W 5% RES CF 4700 OHM 1/4W 5% RES WW 0.6 OHM 2W RES CF 90 OHM 1/4W POT TRIM lOOK SIDE A.DJ PCMT POT TRIM VERTICAL LINEARITY POT TRIM 5K OHM S I DEADJ PCMT A. POT FOCUS 2M OHM POT OCNTRAST THERMISTOR OPC lK OHM RES CF 220 OHM 1/2W 5% RES CF 820 OHM 1/2W 5% RES CF 1.5K OHM 1/2W 5% RES CF 10K OHM 1/2W 5% CAP CER 220pF 50V CAP ELEC 100uF 10V
R201, R203 R207 R504 R214 R210 R301 R208
R205
R204, 212, 213 R502
SFR1, 4
SFR2
SFR3 VR2 VR1 TH201 R506 R206, 503 R507, 509 R508 C501
+/-20% C205 CAP 22uF 25V C206 CAP ELEC 22uF 100V C505 CAP ELEC 220uF 10V (OPC) C207 CAP ELEC 4.7uF 16V (OPC) C301 CA.P MYLAR .0068uF 200V (ope) CAP MYLAR .01uF 50V (OPC) CAP MYLAR .47UF 50V (ope) CAP MYLAR .01uF 50V CAP MYLAR .1uF 600V (ope)
C303
C302
C208 C502
C504
PCB ASSEMBLY VIDEO MONITOR
Part Number
121972-00
121975-00
121993-00 122008-00
122009-00
122010-00 122012-00 130745-00 122018-00 122017-00
120475-00 122022-00 122136-00
122800-00 130745-00 130116-00 120455-00 120465-00 121997-00 122021-00 120455-00 120473-00
Description
CAP MYLAR .47uF 50V (OPC) CAP MYLAR .47uF 400V (OPC) CAP ELEC 220uF 16V YOKE DEFLECT W/CONN KYS-00060 COIL LINEARITY NON ADJ LC-36 COIL INDCTR 27uF .3PIE TNFR HORIZ DR HDT-19 TNFR FLYBACK KYS-20708 DIODE 1N920/KD8513A DIODE DS113A/MR1-1000 (DAMPER) DIODE 1N914 DIODE 1N4004 MOT COIL LINEARITY ADJ IC-014631 CAP ELEC 16V (NON-P) TNFR FLYBACK KYS-20708 TRAN KTC 2229Y TRAN 2N4401/2SC1166 TRAN 2N3904/KTC1815 TRAN 2N6121/2SC1173 TRAN 2N6124/2SA473 TRAN 2N4401/2SC1166 TRAN 2SC2373
2-~8
Location
C506
C304 C305
L202
L201 L302 T301 T302 D201, 202 301
D302 D501 D502
L201 C306 T302 Q103 Q201 Q202 Q203 Q204 Q301 Q302
PCB ASSEMBLY POWER SUPPLY
Part Number Description Location
121982-00 CAP 470uF 35V (OPC) Cl16 121981-00 CAP TANT .33uF 35V (OPC) Cl14, 115 121:966-00 C~P ELEC 4700uF 16V
(OPC) Cl17 121965-00 C~P EIJEC 3300uF 35V
(OPC) Cl13 121964-00 CAP ELEC 22uF 160V C120 121963-00 CAP ELEC 100uF 160V C119 120287-00 CAP CER .01uF 16V 20% C101-109 122006-00 DIODE IN5391/DS135D DI01, 102, 109, 113,
114 130098-00 DIODE BY251 3A 200V 0103-108 122016-00 DIODE 1N759A/RD12EB
ZENER 0111, 112 121931-00 FUSE 3A 125V 3AG FI02, 103 121268-00 VOLT REG LAS 1605 2A/5V IC2 121269-00 VOLT REG LAS 16CB
2A/13.8V GEN IC1 121766-00 RES CF 390 OHM 1/2W 5% RI02 121774-00 RES CF 3.9K OHM 1/4W RI07 121373-00 RES CF 27K OHM 1/4W
+/-5% R108 120531-00 RES CF 4700 OHM 1/4W 5% R105, 106 120393-00 RES CF 30K OHM 1/4W 5% RllO 120383 .... 00 RES CF 2.7K OHM 1/4W
+/-5% RI09 121779-00 POT TRIM 5K OHM
SIDE ADJ PCMT SFR3 120471-00 TRAN 2N5551
NPN/HIGH VOLTAGE QI03 120467-00 TR~N KTC1627/MPSA06
NPN/SIL Q102
2-9
DETACHABLE KEYCAPS
Sculptured Description Printed Blank Degree
1X1 LG BLANK 121616-00 0 1X1 LG NO SCROLL/SETUP 120887-00 0 1X1 LG F1 120850-00 0 1X1 LG F2 120851-00 0 1X1 LG F3 120852-00 0 1X1 LG F4 120853-00 0 1X1 LG F5 120854-00 0 lX1 LG F6 120855-00 0 1X1 LG F7 120856-00 0 1X1 LG F8 120857-00 0 1X1 LG F9 120858-00 0 lX1 LG FlO 120859-00 0 1X1 LG F11 120860-00 0 1X1 LG CHAR INSERT 120861-00 0 1X1 LG CHAR DELETE 120862-00 0 lX1 LG LINE INSERT 120863-00 0 1X1 LG LINE DELETE 120864-00 0 lX1 DG BLANK 121617-00 +14 DG ESC/LOC ESC 120842-00 +14 1X1 DG 1/1 120778-00 +14 lXl DG 2/@ 120779-00 +14 1X1 DG 3/# 120780-00 +14 IX1 DG 4/$ 120781-00 +14 1X1 DG 5/% 120782-00 +14 1X1 DG 6/"- 120783-00 +14 lXl DG 7/& 120784-00 +14 IX1 DG 8/* 120785-00 +14 lX1 DG 9/( 120786-00 +14 lX1 DG 0/) 120787-00 +14 1Xl DG -/ 120788-00 +14 lXl DG =/+ 120789-00 +14 1X1 DG '/- 120790-00 lX1 DG BACK SPACE 120792-00 +14 1X1.5 DG TAB 120845-00 +7 1X1.5 DG BLANK 121618-01 +7 lX1 DG BLANK 121618-00 +7 1X1 DG Q 120806-00 +7 1X1 DG W 120807-00 +7 lX1 DG E 120808-00 +7 1X1 DG R 120809-00 +7 1X1 DG T 120810-00 +7 1X1 DG Y 120811-00 +7 IX1 DG U 120812-00 +7 1Xl DG I 120813-00 +7 1X1 DG 0 120814-00 +7 1X1 DG P 120815-00 +7 1X1 DG [/J 120816-00 +7 1Xl.S DG LINE FEED 120844-00 +7 1X1.25 LG CLEA.R SPACE 120896-00 +7 lX1 LG CTRL 120869-00 0
~.~, ,
DETACHABLE KEYCAPS
Sculptured Description Printed Blank Degree
lXl DG ALPHA LOCK 120818-00 0 lXl DG A 120819-00 0 lXl DG S 120820-00 0 lXl DG D 120821-00 0 lXl DG BLANK 121616-01 0 lXl DG F 120822-00 0 lXl DG G 120823-00 0 lXl DG H 120824-00 0 lXl DG J 120825-00 0 lXl DG K 120826-00 0 lXl DG L 120827-00 0 lXl DG . / . , . 120828-00 0 IXI DG '/" 120829-00 0 LG ilL" RETURN 120894-00 lXl LG BREAK 120870-00 0 lXl DG BACK TAB 120817-00 -7 lXl.5 LG SHIFT 120847-00 -7 lXl DG Z 120830-00 -7 IXI DG X 120831-00 -7 lXl DG C 120832-00 -7 lXl DG V 120833-00 -7 lXl DG B 120834-00 -7 lXl DG N 120835-00 -7 lXl DG M 120836-00 -7 lXl DG BLANK 121619-00 -7 lXl DG ,/< 120837-00 -7 lXl DG ./> 120838-00 -7 lXl DG //? 120839-00 -7 lXl DG {/I 120840-00 lXl LG DELETE 120871-00 -7 IXI LG PRINT (LP) 120893-00 0 lXl LG FUNCT (LP) 120890-00 a lX8 DG SPACE BAR 120897-00 lXl LG HOME (LP) 120891-00 0 IX1 LG CURSOR ARROW (T.JP) 120892-00 0 lXl LG LINE ERASE 120865-00 0 lXl LG PAGE ERASE 120866-00 0 lXl LG SEND 120885-00 0 lXl DG 7 120799-00 0 lXl DG 8 120800-00 0 lXl DG 9 120801-00 0 lXl DG 4 120796-00 0 IXI DG 5 120797-00 0 lXl DG 6 120798-00 0 lXl DG 1 120793-00 0 lXl DG 2 120794-00 0 lXl DG 3 120795-00 0 lXl DG , 120804-00 0 IXI DG 0 120802-00 0 IXl DG . 120805-00 0
DETACHABLE KEYCAPS
Description
lXl.S LG ENTER lXl DG -
Sculptured Printed Blank
120848-00 120803-00
Degree
o o
SECTION
MAIN LOGIC BOARD
925 THEORY OF OPERATION
4.1 Overview ------------------------------4.2 Operating Clocks
4.3 Address Decoding
4.4 Terminal Memory
4.5 Display Fundamentals
4.6 Interrupt Signals
4.7 Video Generation
4.8 Communications
4.1
OVERVIEW
The TeleVideo Model 925 terminal is the third member of a family of terminals based on the 6502A microprocessor. Circuitwise, it is very similar to the Model 910; the main differences being increased program ROM space, serial keyboard interface, and more complex attribute and communications sections. Functionally, the 925 is designed to be halfway between the more sophisticated Model 950 and the conversational 910.
As in the 950 and 910, the microprocessor is totally interrupt driven. This operation provides the most efficient and error free means for asynchronous reception and transmission of data.
4.2
OPERATING CLOCKS
There are three clocks of the 925 control board. Two of these are synchronized; shift clock and character clock, while the third, the receive and transmit clock, is totally independent of the other two. The basic clock on the board is the Video or Dot clock. It's frequency range is 13.608 megaHertz and is produced by a crystal controlled oscillator which is made up of the crystal, Y2, part of chip A16, and several passive feedback components (see Sheet 7 of schematic). This clock is used to shift video data out of a shift register for display on the CRT. It is also used to clock a counter, A24, to create the system clock. The system clock is designated 'Character Clock' on the 925 schematic. It is used for two purposes; character clock input to the CRT control chip (A59, Sheet 2) and as the system clock (00) input to the 6502A microprocessor (A60 Sheet 1).
A 74LS163 presettable 4 bit binary counter A24, Sheet 7) is used to divide the shift clock by eight; providing a frequency of 1.701 megaHertz. The 74LS163, which is normally a divide by 16 counter, is forced to divide by eight by loading a count of eight into the counter when it reaches it's highest count (15).
In this mode, the QC output of the counter is low for 4 clocks and high for 4, making it suitable for use as a symmetrical clock.
The two Asynchronous Communications Interface Adapters (ACIA #1 and ACIA #2, Sheet 5) have internal clock oscillators and require only that the external crystal be added. The circuitry of the 925 allows the two ACIA's to share one crystal, Yl.
Internal to each ACIA, the basic frequency of 1.8432 megaHertz is divieded down by a factor determined by a firmware controllea register. ACIA # 2, which is used for receiving keyboard data, is always set for 1200 baud (bits per second). ACIA # 1 is
4-1
shared by the Host Communications port (P3), and the printer port (P4). The baud rate for ACIA # 1 depends on the baud rate switch settings for the two ports.
4.3
ADDRESS DECODING
The 65,536 byte address field of the 6502A microprocessor (MPU) is divided as follows. The two highest address lines (A14 & A15) are decoded by a 1 of 4 decoder (half of A37, Sheet 1) to divide it into four 16,384 (16K) byte sections. The highest 16K bytes (COOO - FFFF )are used for program Read Only Memory
16 16 (ROM).
The program ROM contains a program which controls the microprocessor, causing it to process data fed to it by the Keyboard or the host computer. The 16K block is divided further into two 8,192 (8K) byte sections. When the MPU is addressing the higher 8K bytes, the chip located at A50 is selected. When the MPU is addressing the lower 8K bytes, the chip located at A49 is selected.
The next lower 16K bytes, 8000-BFFF is used to access I/O devices. This output of A37 is connected to a 1 of 8 decoder (A29, Sheet 1) and the other section of A37 where, using lower order address lines, 12 individual locations are decoded. Each I/O device is treated as if it were an individual byte within the memory map.
The output labeled 4000-7FFF from A37 defines the second lowest 16K clock within the address range. This signal is 'OR led with 02 low (A54, Sheet 1) to select two 6116, 2K by 8 bit RAM chips. (A47 and A48, Sheet 2).
These chips are used to store data to be displayed on the CRT (Display RAM). A48 contains data for one screen (page 1) and A47 the other (page 2).
The output labeled 0000-3FFF is true (low) when the MPU is addressing any location within that range. It is used to select two 2114, lK X 4 bit RAM chips. These RAMS are used to store variable data that is processed by the MPU during program execution. (System RAM).
4.4
TERMINAL MEMORY
Memory in the 925 terminal consists of ROM and RAM. As stated in Section 4.3, Program (or System) ROM is located within the range COOO-FFFF. It is further broken down into two 8K byte
4-2
sections, COOO-DFFF and EOOO-FFFF. Each of these sections is represented by a socket capable of accepting a 2K (2048) byte ROM, a 4K (4096) byte ROM or an 8K (8192) byte ROM. This allows expansion of program ROM from 2K bytes to 16K bytes in 2K byte increments. Each socket is selected using the COOOFFFF output of A37 'ANO'ed with the high (EOOO-FFFF) or low (COOO-DFFF) condition of address line A13.
The standard configuration of the 925 is 4K bytes located from DOOO-DFFF and another 4K bytes located from FOOO-FFFF.
System RAM consists of lK (1024) bytes of static random access (read/write) memory. (A4l & 42, Sheet 1). The 0000-3FFF output of A37 is used to select these two chips. Since there are no other devices located in this section, further decoding is not required. System RAM is used as a buffer for characters received from and transmitted to the host computer and printer; 'Flags' used by the program for decision making, and for storing the states of various software 'timers'.
4.5
DISPLAY FUNDAMENTALS
The circuitry required to display data on the CRT other than the video circuitry, which is covered in Section 4.7 is made up of three parts; display memory, character generation memory and the CRT controller chip (A59, Sheet 2).
The display memory consists of 4K bytes of high speed static RAM (A47 & A48, Sheet 2). The screen contains 25 rows of 80 characters each for a total of 2000 characters. Therefore, each 6116 RAM (2048 bytes each) is capable of storing an entire screen of characters.
The address lines of the two 6ll6's are controlled by the outputs of three 2 to 1 multiplexers (A56, A57 & A58, Sheet 2). The sources for the inputs of the multiplexers are the address lines of the MPU (AO-All) and the memory address outputs of the CRT controller (MAO-MAIO). The multiplexers' inputs are switched by the 01 output to the MPU. This operation allows the CRT controller memory address lines to drive the display RAM address lines when 01 is high, while the MPU address lines are enabled during 01 low. The MPU accesses the display RAM to update a location due to keyboard input or transmission from the host (Write), or to READ a location for transmission to the host during a block mode transmit.
Display memory accesses from the MPU occur while 01 is low. Data from the display RAM is gated to and from the main Data Bus (00-07 lines of the MPU) by a byte wide bi-direction of 01. This buffer is selected if the MPU is addressing a location in Display RAM. The direction of the data is controlled by the R/W signal from the MPU during 02 high.
4-3
During the high portion of 01 (02 low), the CRT controller accesses the location specified by its memory address lines. The display RAM is always selected during 02 low and the R/W line of the display RAM is always high at this time. Because of this, any access of display RAM during 02 low will cause a read of the location being addressed. This data is latched by DC Carry (A39, Sheet 3) and used as address lines A3-A9 of the character generator ROM (A31, Sheet 3). AD, AI, and A2 address lines 'of the character generator ROM are controlled by the RAO, RAl, and RA2 lines from the CRT controller. These ,define which line of the 10 line character cell is in effect. The data to be displayed for the character and line being -addressed is loaded into a parallel in/serial out shift register (A30, Sheet 2). During the next eight cycles of the shift clock this data is shifted out one bit at a time and combined with other signals to create the video output to the video amplifier in the monitor.
The MPU is capable, using address line All, of writing to or reading from any of the 4096 bytes of display RAM. The CRT controller can only access a maximum of 2048 bytes (using MAO-MAIO). To allow the second page to be displayed (providing that a chip is installed in A47), the program, in response to an ESC K, sets a bit in one of the control latches labeled 'Display Page Two'. This connects to the highest order line on the CRT controller side of the multiplexers. Thus, when 01 is high, this bit will be high and A47 will be accessed by the CRT controller.
4.6
INTERRUPT SIGNALS
As mentioned in Section 4.1, the MPU is interrupt driven in the 925. An interrupt is an input to the MPU which causes it to complete its present instruction r save the contents of its internal registers and go to a predetermined location in the program. The MPU will respond to an interrupt within a maximum of 8 system clock cycles of 4.7 microseconds.
The 6502A MPU has two interrupt inputs, IRQ and NMI. IRQ is a maskable interrupt which can, under program control, be ignored. NMI is non-maskable interrupt that cannot be ignored by the MPU.
The Model 925 uses the NMI for interrupts generted by the Keyboard ACIA (A33, Sheet 5). IRQ has two possible sources; the communications ACIA (A32, Sheet 4) and the vertical sync interrupt. The interrupts generated by the ACIA's indicate that data has been received or that the transmitter section is ready to accept a new character. The vertical sync interrupt is used by the program to increment timing registers used to keep track of the time of day, blink the cursor, time the bell, etc. When an interrupt occurs, the firmware (program ROM) must determine which source caused the interrupt and act accordingly.
4-4
4.7
VIDEO GENERATION
Control signals for the CRT monitor are generated by the CRT controller, the attribute logic and the shift register mentioned in Sectin 4.5.
The CRT controller produces vertical sync, horizontal sync, display enable and cursor signals. Horizontal and vertical sync are buffered and sent directly to the monitor. Display enable and cursor are used along with the attributes and serial data from the shift register to produce the video signal for the monitor.
Because of the character address latch (A39, Sheet 2), the character generator ROM, and the shift register, it takes two character clock times for a character addressed by the CRT controller to be displayed on the screen. The display enable and cursor signals simultaneously with the memory address coinciding with the position on the screen. Because of this the cursor and display enable signals must be delayed by two character clock times. This is accomplished by a hex D flipflop (A22, Sheet 4).
The remaining two stages are used to provide a 1 character time delay for the attribute signal and half intensity signal (an additional delay is provided by the character address latch).
The 925 visual attributes are achieved in the following manner:
The high order bit coming out of the character address latch (Chad 7) is used to indicate a protected (half intensity) character. This is the only attribute which is done on a character by character basis. The remaining four attributes, blinking, blank (hidden characters), reverse video and underline, are produced by special characters written into the display RAM by the firmware in response to a special 3 character sequence. (See operators manual). These special characters are decoded to provide a signal labeled 'Attribute' (see pin 4 of A22, Sheet 3). This signal is used to gate DC Carry to the data input of a 'D' flip-flop (pin 2 of AI, Sheet 3) which is clocked on the rising edge of shift clock while DC Carry is low. As long as the character in the character address latch is an attribute character, the data input will be low when the flip-flop is clocked. This keeps the 'Q' output low, enabling the outputs of one of three quad tri-state latches (AI9, Sheet 3). This latch is used to carry the existing attributes through a new attribute character, and its outputs are used only during the time that an attribute character is being displayed. (An attribute character is displayed as a half intensity blank). As soon As a non-attribute character is decoded, the 'Q' output of the D flip-flop (pin 5 of AI) is clocked high, disabling the outputs of A19. At the same time, Q output (pin 6) goes low. This is connected to one of the
4-5
output enable inputs of another quad tri-state latch (A20). The other output enable input of A20 is controlled by the Q output of another D flip-flop (pin 8 of AI) that goes low approximately 35 nanoseconds after pin 6 of AI. This operation ensures that the outputs of only one of the latches are active at any given time.
The purpose of the second latch is to contain the most recent attributes on the present scan line. The third quad tri-state latch (A21) is used to remember the last attribute character encountered. Unlike the first two latches, which are reset by horizontal sync (once each scan line) the third latch is reset only once each frame by vertical sync. In this manner, the attributes are allowed to continue from one character row to another. The outputs of this third latch are enabled when both D flip-flops mentioned earlier are reset (Q outputs low). The time during which these outputs are enabled is defined as; from the beginning of a new character row that was preceded by a character row containing an attribute character; until a new attribute character is found, i.e., if the only attribute character is character number 62 on character row 10, the outputs of A21 will be enabled at the start of character row 11 and remain enabled until the end of the frame (vertical sync).
The attribute signals, underline, reverse video, blink and blank, are combined with other signals pertinent to the video output (see upper left side of sheet 4), to create a stream of pulses used by the video amplifier to control the electron beam within the CRT.
4.8
COMMUNICATIONS
Data from the Keyboard is received via a standard RJll connector located on the rear of the board. ACIA # 2 (A33, Sheet 5) is used to convert the serial data into parallel form. When the ACIA receives a character, it interrupts the MPU via the NMI input. The MPU, during the NMI routine, reads the contents of the receive buffer of the ACIA. The keyclick is produced automatically by the hardware, requiring no firmware overhead. The IRQ output of the ACIA also connects to the trigger input of a simple one-shot circuit used to produce a pulse which drives the speaker located in the Keyborad (see lower left section of sheet 5).
The terminal connects to the host computer through P3 (sheet 5) which is a standard 25 pin D type connector located on the rear of the board. In half or full duplex, (conversational) mode, data is sent to the host one character at a time as it is typed on the keyboard. In block mode, data is not sent to the host unless a send command of some sort is entered on the keyboard. These modes of data transmission are completely under control of the firmware.
4-6
The 925 also has a separate connector which can be connected to a printer with a serial communications port. The connector for the printer port is P4. Data sent to the printer can come from two selectable sources; the host computer or the terminal screen (display RAM). To enable data from the Host to the printer, the control latch output labeled 'EXTENSION' is used. This gates data received on P3 pin 3 to P4 pin 3 via or gate A26 (pins 4,5,6). It also allows two possible control lines, DTR (P4-20) and Handshake (P4-11) to go to the host.
Another control latch output labeled 'BI-DIR' allows data from the printer (P4-2) to be sent to the host (P3-2). Data from the printer is not received by the 925 terminal.
During transmission from the host to the printer, the screen may (normal) or may not (transparent) be updated. Another mode of printer operation is page print. In this mode, text is entered on the screen (either page or display RAM) and, when the desired text is entered and properly edited, the data can be sent to the printer by depressing the 'PRINT' key. The data on the screen will be sent to the printer from the 'HOME' position to the cursor position. During page print, the data is not sent to the host. This is done by disabling the data to the host through another gate (A26 pin 8,9,10).
4-7
~ I
00
NOTE:
SEL =DEVICE SELECT
PARALLEL KEYBOARD
DATA
DATA
SEL
MAIN PORT PRINTER (HOST) PORT
SYS
RAM
MPU
DATA BUS
SEL
ADDRESS
DECODE
ItO CLOCK
DATA BUS
MPU ADDR BUS
R/WIEL
SYS
ROM
C'HARACTER CLOCK CIRCUITRY I-_____ ....:;:.;.,-=:K¥I: ___ -I
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RAO-RA2
I:~ O)to Z~ - )to .... n 0 .... ~m ~
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925 CONTROL BOARD BLOCK DIAGRAM
Figure 4-1
DISPLAY
RAM
TO VIDEO AMP
925 MONITOR
Read Unused ROM # 1 Only
ROM # 2
Unused ROM # 2
Unused I/O
Write Control Latch # 2
Read Dipswitch Port # 2
Read Dipswitch Port # 1
Write Control Latch # 1
-- Soare
Read/Wr Control Register
Read/Wr Command Register
Read/Wr Status Register
Read/Wr Transmit or Receive Data
Read Dipswitch Port # 5
Write Reset IRQ
Read/Wr Control Register
Read/Wr Command Register
Read/Wr Status Register
Read/Wr Transmit or Receive Reg.
Read/Wr Read or Wr ite Regs 0-31
Write Address Register (Contains Reg. Number)
Read Dipswitch Port # 4
Read Dipswitch Port # 3
Unused Display RMl
Page 2
Page 1
Unused Sys. RAN
FFFF
mno .. EFFF EDOO DFFF 0000
~ BFFF QOO4
9003
9002
9001
9000
A070
8063
8062
8061
8060
8050
R040
8033
8032
8031
8030
8021
8020
8010
8000
7FFF
4COO
4BFF
4800
47FF
4000
3FFF
0400
03FF
0000
Table 4-1
~ ... ........
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PROGRAM DATA
Displa\ BOW/ Timeout Keyclick Mode WOB Bell Blank On/Off
SP/MK OlE Pur. BOWl Baud WOB Rate 3
Stop Word 9251 Baud Bits Edit LenQth 920 Rate 3 CPU Bi- 925/ 60/ Reset Exten. Direc. 920ATT 50Hz
Stop Word Word Rcvr- Clk Baud Bits Lnth 1 Lnth a Source Rate 3
Par.2 Par .1 Par.O Norm/ Xmit 1 Fcho
Read: Status Register Write:
Read: Receive Register Write:
Not Used Cursor Cursor DTR 1 a
NO UAA Stop Word Word Rcvr ell<. l13aud Bits Lnth 1 Lnth a Source Rate 3
Par.2 Par.1 Par.O Norm/ Xmit 1 Echo
Read: Status Register Wr ite:
Read: Receive Register Write:
1 DISPLAY PARAMETERS
I I
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VARIABLE
1
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D1 D0
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Baud -Salla Baud Rate 2 Rate 1 Rate a Xmit 0 RCV OTR
IRO Program Reset(No Data)
Transmitter Register
SRTS Not Used
Baud Baud lSaua Rate 2 Rate 1 Rate 0
Xmit a Rcv DTR IRO
Program Reset(No Data)
Transmit Register
Test Not Used
CRt COf!IT1 Comm CR-LF Mode 1 Mode a
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5 4 3 1 REVISIONS
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APPROVED
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925 GATE ARRAY CONTROL BOARD. REV A
VIDEO MONITOR
The video monitor contains two sections: the vertical amplifier and the horizontal amplifier. These amplifiers provide the voltages necessary to drive the CRT yoke, which deflects the electron beam across the CRT.
The electron beam, which is generated by the CRT electron gun, sweeps across and down the screen to create scan lines (see section on character generation). The beam's movement is driven by vertical and horizontal sweep rates, which are determined by the display circuitry on the logic board. The horizontal sweep is approximately 16 KHz, the vertical sweep 60 Hz for domestic and 50 Hz for European applications.
The horizontal synch pulses coming into the video monitor are inverted and amplified by transistor Q30l. This signal is then coupled across the drive transformer T30l and applied to the base of the ouptut transistor Q302. Q302's output drives both horizontal yoke windings, as well as the step-up transformer that produces the anode voltage and the grid voltage for the CRT grid in the neck of the CRT. Since high-frequency magnetic fields are produced and then broken, the flyback transformer is necessary to provide high voltages for the horizontal scans.
These horizontal scans start in the upper left corner and scan across to the upper right corner. Once the scan reaches the end of the line, a blank appears where the video beam is turned off and retraced to the beginning of the next scan line.
The vertical synch pulses coming into the video monitor are converted to a sawtooth waveform. Initially, this pulse goes from a negative leading edge to a positive falling edge and passes through transistor Q202, which inverts it to its usable form.
At that point, the pulse goes from a +2-volt leading edge to a -2.5-volt falling edge. Timing is critical since 250 horizontal scan lines (which comprise the total number of horizontal scan lines on the CRT) occur within one sawtooth pulse. Therefore, the sawtooth pulse has to be proportional to all previous pulses or the timing will be off for the vertical as well as the horizontal sweep.
When the vertical sweep is negative, Q20l conducts and C202 discharges. During the positive portion, Q20l cuts off and allows C202 to charge. While C202 is charging, the electron beam scans.
The vertical sweep scans from top to bottom. Once it reaches the bottom of the page, a blank occurs when the video beam is turned off and is retraced to the top of the screen. At that point, C202 discharges. After the retrace, the beam turns off again and begins its scan routine.
Adjusting SFRI (vertical height) and SFR2 (vertical linearity) changes the rate of C202's charge, and therefore the slope of the sawtooth pulse.
6-1
TUBE SPECIFICATION
12 INCH 90 DEGREE, HIGH RESOLUTION
DISPLAY TUBE
3l0KGB 31
The 3l0KGB3l is a 12 inch 90 degree high resolution, rectangular display tube primarily intended for use as a alpha-numerical and graphic display tube for computer peripheral devices. The tube is provided with banded type integral implosion protection (with mounting lugs). The tube features a low reflectance high contrast screen.
ELECTRICAL DATA
Heating Indirect by AC or DC:
Heater voltage •••••• Heater current. • • • •
• • .12.0 volts • •• 75 nA
Focusing Method. • • • Electrostatic
Deflection Method •• . . . . • Magnetic
Deflection Angles (Approx.) Diagonal. • • Horizontal. • Vertical. • •
• •• 90 degrees • 78 degrees
• •• 61 degrees
Anode voltage ••••• 15,000 max. volts 8,000 min. volts
Using high voltage with this tube internal flash-overs may which may cause damage to the cathode of the tube and to circuit components on the video monitor board. Therefore necessary to provide protective circuits using spark-gaps etc. should be connected as illustrated in figure II below.
TO CIRCUITS ~ • : SHORT COK>ECTl"
. -cpf---+I---+I---<....----.... : TO ELECTRODES
(RES T STORS l_------J ---------- (SPARK GAPS)
TO Cflf\SS I S
SHORT CONNECTI01\ TO EXTERi\AL
------------ COt-iDUCTIVE COATI:\G
Figure 1.
occur, various it is These
No other connections between external conductive coating and chassis permissible.
6-3
are
OPTICAL DATA
Faceplate. • • • • • • • • •• • • • • • • Filterglass Anti-reflection treatment • · . . . . • • • • No
Screen • • • • • •••• · . . . • • • Aluminized Appearance. • • • • • • • • • • • • • • • • Low Reflective
A: The dark-colored screen, in combination with the filterglass, produces the low reflectivity (equivalent to a 20% light transmission filterglass) for easy-to-see display.
MECHANICAL DATA
Tube Dimensions:
Overall length. · · · · · · · · · · · · · · · 278.8 max. mm Greatest dimensions of tube (excluding lugs)
Diagonal. · · · · · · · · · · · · · · · · · · · 318.5 +/- 2.7 Width . · · · · · · · · • · • • · · · · · · 279.6 +/- 2.7 Heigth. · · · · · · · · · · · · · · · · · · · · 218.7 +/- 2.7
Useful screen dimensions (projected) Diagonal. · · · · · · · · · · · · · · · · · 295.0 min. mm Width . · · · · · · · · · · · · · · · · · · 257.0 min. mm Heigth. · · · · · · · · · · · · · · 195.0 min. rom
mm mm mm
Pin Position Alignment • • • • • • • • • • • • • • • • Pin No 5 aligns
Operating Position • • Weight (approx.) • • Implosion Protection • •
GENERAL CONSIPERATIONS:
approx. with anode contact.
• • • • • • • • • • • • • • Any • •••••••••••••• 3.2 kg
• • Tension band (with mounting lugs)
1. ~ handling. Care should be taken not to scratch the tube.
2. Impact. The tubes should never be exposed to impacts of more than 30G during handling or transportation.
3. Grounding. The external conductive coating of the tube should be grounded with multiple contacts (e.g. a contact plate having many fingers.) Poor contact might cause local heating resulting in tube leakage.
WARNING
SHOCK HAZARD:
The high voltage at which the tube is operated may be very dangerous. Design of the equipment should include safeguards to prevent the user from coming in contact with the high voltage. Extreme care should be taken in the servicing or adjustment of any high voltage circuit.
Caution must be exercised during the replacement or servIcIng of the tube since a residual electrical charge is stored within the· tube. Before handling the tube remove any undersible residual high voltage charge from the tube, by shorting the anode contact button to the frame of the terminal as illustrated in figure '2. Discharging the high voltage to isolated metal parts sucha as cabinets and control brackets may produce a shock hazard.
CRT ANODE
INSULATED HANDLE SCREWDRIVER
~---METAL FRAME
924MM-2
Figure 2
6-5
POWER SUPPLY
Voltages are created and regulated as follows: A 9.8 AC voltage is rectified by diodes 0105 and 0108, resulting in a 9-volt output. These 9 volts are then filtered through Cl17 and applied at the 5-volt regulator IC2.
The raw AC voltages for the positive and negative 12 DC voltage are derived from the center top of the secondary winding of 0101. The diodes 0101 and 0102 form a full-wave rectifier that converts the 37-volt AC waveform to a 20-volt DC level. This DC voltage is then filtered by Cl16 and stabilized to -12 volts by a zener-regulated circuit that consists of a resistor (Rl02) and the zener diode (0112).
Diodes 0103 and 0104 also form a full-wave rectifier that converts the 37-volt AC waveform to a +20-volt DC level.
This DC voltage is filtered by Cl13 and applied to the 13.8-volt regulator ICI. The 13.8 output, in turn, is dropped 1.6 volts across diodes 0113 and 0114 to achieve the desired +12 volts DC.
A 79-volt AC waveform is applied to the half-wave rectifier 0109, which is filtered by Cl19. The resulting 95-volt DC level is then regulated by a series voltage regulator. The reference element is the positive l2-volt zener diode 0111. The sensing and control elements are transistors QI03 and QI02.
The high voltages needed to drive the CRT tube V50l are derived from the flyback transformer T302 on the video module.
6-6
TO POWER SUPPLY MODULE-P11 DRIVE TRANSFORMER
TO DEFLECTION YOKE-P12
TO CONTROL BOARD (SIGNAL)-p10
0
0
FOCUS VERT LINEARITY
VERT HEIGHT
BRIGHT
VIDEO MONITOR MODULE
0
0-~. 0 0
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FLY BACK TRANSFORMER
H. V ANODE CAP
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DC 13.8V (LAS 16CB ) DC 5V (LAS 1605)
UNREGULATED DC OUTPUT
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VIDEO B+ ~ d:JJ ADJUST POT I jt.
Ie F102 F103 •
FUSE (3A) FUSE (3A) (+13,8V) (+5V)
POWER SUPPLY MODULE
TO t VIDEO MODULE (POWER)-J11
TO POWER TRANSFORMER -P13
TR WAVEFORM and VOLTAGE
Transistor Bas~(l n) Collector (Out, Emit t~r( GND)
Locat Funct vtg' Wav~ Vtg' Wave vtg' Wave e_ ion
Parts -ion DC AC Form DC AC Form DC AC Form V Vp.p V Vp.p V Vp.p
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Horiz V1J A 0)02 25C2233 -o,oe 6 12.8 121. 0.0 0,0 Ou~
OS01 25C9E3 Video
0.1. 3 lJLf 76.8 25 LnJ -0,8 2.8 UlJ Amp
D302 OS-lOA DamplN!: 12.8 132 A DC Voltag~ reading token with VTVM from point indicated to ChaSSiS ground.
AC Voitoge reading token With Oscillos.cope from point Indicated to ChaSSIS ground
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2 1 REVISIONS
DESCRIPTION APPROVED
1. ALL RESISTANCE VALUES IN OHM K=LOOO M=LOOO,OOO.
2. ALL CAPACITOR VALUES IN FARAD U=10-5 P=10~12
3. UMLESS OTHERWISE STATED, WORKING VOLTAGES OF CAPACnORS ARE 50 VOLTS.
4. THIS SCHE'1ATIC DIAGRAM COVERS BASIC OR REPRESENTATIVE CHASSIS ONLY. THERE MAY BE SOME COMPONE"!T DR PARTIAL SCHEMATIC D IFFERErICE BEnIEEN ACTUAL CHASSIS AND nlE SCHEr-1ATIe DIAGRAM.
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1. ALL RESISTA~CE VALUES II! OHM KsLOOO roFLOOO.OOO.
2. All CAPACITOR VALUES [IC FARAD lJzIO-6 P-IO:12
3. U!'II..ESS OTHERWISE STATED. IIJRKING VOLTAGES OF CAPAC lTORS .'RE 50 VOLTS.
4. THIS SCHP.1ATlC DIAGRN! COVERS BASIC OR REPRESHHATlVE CHASSiS GNU. THERE MY BE SOME COI'"PDNENT OR PARTIAl SCfIE."ATlC D IFFERErlCE BET'rIWt ACTUAL CHASSIS A/iD THE SCH£l'lATIC llIAERAPl.
DClCUMENT NO. 29000 047 REVISION 1" OCT. 1978
PART NUMBER R6522
'1' Rockwell R6500 Microcomputer System
DATA SHEET
VERSATILE INTERFACE ADAPTER (VIA)
SYSTEM ABSTRACT The 8-bit R6500 microcomputer system is produced with N
channel, silicon-gate, depletion-load technology. Its perform
ance speeds are enhanced by advanced system architecture.
Its Innovative architecture results in smaller chips - the semi
conductor threshold to cost-effectivity. System cost-effectivity
is further enhanced by providing a family of 10 software-<:om
patlble microprocessor (CPU) devices, memory and 1/0 devices ...
as well as low-cost design aids and documentation.
DESCRIPTION The R6522 VIA adds two powerful, flexible Interval Timers,
a serlal-to-parallel/parallel-to-serial shift register and input latch
ing on the peripheral ports to the capabilities of the R6520
Peripheral Interface Adapter (PIAl device. Handshaking capa
bility is expanded to allow control of bidirectional data trans
fers between V lAs 10 multiple processor systems and between
peripherals.
Control of peripherals is primarily through two 8-bit bidirectional
ports. Each of these ports can be programmed to act as an input
or an output. Peripheral I/O lines can be selectively controlled
by the Interval Timers to generate programmable-frequency square
waves and/or to count externally generated pulses. Positive con
trol of V IA functions is gained through its internal register organi
zation: Interrupt Flag Register, Interrupt Enable Register, and
two Function Control Registers.
Ordering Information
Order Number
R6522P R6522AP R6522C R6522AC R6522PE R6522APE R6522CE R6522ACE R6522CMT
A BIT DAT A BUS
TO 6)00 CPU
R'w
02 (LOO:
REGISTER AND CHIP 5f:.ltCT5
IRQ
Package Type
Plastic Plastic Ceramic CeramiC Plastic Plastic Ceramic Ceramic Ceramic
Temperature Frequency Range
1 MHz OOC to +700 C 2 MHz OOC to +700C 1 MHz OOC to +700C 2 MHz OOC to +700 C 1 MHz -40
0C to +85
0C
2 MHz -40o
C to +850
C 1 MHz -40
0C to +85
0C
2 MHz ·400
C to +850~ 1 MHz -55
0C to +125 C
CONTROL
8 BIT TO R6S22 OAT A PORT PERIPHERALS
Basic R6522 I nterface Diagram
@ Rockwell Inlernallonal Corporation 1978 All Rights Reserved
FEATURES • Organized for simplified software .. ontral of many functions
• Compatible with the R650X and R651 X family of microprocessors (CPUs)
• Bi-directional, 8-bit data bus for communication wIth microprocessor
• Two Bi-directional, 8-bit input/output ports for interface with peripheral devices
• CMOS and TTL compatible input/output periphpral ports
• Data Dlfection Registers allow each peripheral pin to act as either an input or an output
• Interrupt Flag Register allows the microprocessor to readily
determine the source of an interrupt and provides convenient
control of the interrupts within the chip
• Handshake control logic for input/output peripheral data transfer operations
• Data latching on peripheral input/output ports
• Two fully-programmable interval timers/counters
• Eight-bit Shift Register for serial interface
• Forty-pin plastic or ceramic DIP package,
VSS 1 CAl PAO 2 CA2 PAl 3 RSO PA2 4 RSl
PA3 5 RS2
PA4 6 RSJ
PA5 7 RES
PA6 8 DO
PA7 9 01
PBO 10 02
PBl 11 03
PB2 12 04
PB3 13 05
PB4 14 06
PB5 15 07
PB6 16 1/>2 PB7 17 CSl
CBl 18 CS2
CB2 19 R/W
VCC 20 21 IRO
Pin Configuration
Specifications subject to ,..h .. _-.a .. ~;-.h,..., ••• ftn'tir:a
:rJ 0) UI N N
< m :rJ en » -I -rm -Z -I m :rJ ." » o m » c » -C -I m :rJ
........ < -» ""-'
OPERATION SUMMARY Registe, Select Lines CRSO, RS1. RS2, RSl)
The four Register select lines are ncrmally connected to the processor address bus lines to allow the processor to select the internal R6522 register which is to be accessed. The six teen possible combinations access the registers as follows:
RS3 RS2 RSl RSO Register Remarks RS3 RS2 RSl RSO Register Remarks
L l l l ORB H L l L T2L-L Write latch
L l l H ORA Controls Handshake T2C-L Read Counter
L L H L DDRB H L L H T2C·H Triggers T2L-LlT2C·L Transfer
L l H H DORA H L H SR
L H l L T1L·L Write Latch H L H H ACR TlC·L Read Counter
H H L L PCR l H L H TlC-H Trigger Tl L-LlT1C·L
Transfer H H L H IFR
H H H L IER L H H L Tl L-L
H H H H ORA No Effect on L H H H Tll·H Handshake
Note: L" O.4V DC. H = 2.4V DC.
Timer 2 Control
RS3 RS2 RSl RSO RIW-L RIW-H
H L L L Write T2l·L Read T2C·L Clear Interrupt flag
H L L H Write T2C·H Read T2C·H Transfer T2L-L to T2C·L Clear Interrupt flag
Writing the Timer 1 Register
The operat;ons which take place when writing to each of the four Tl addresses are as follows:
F RS3 RS2 RSl RSO Operation CRIW - L)
L H L L Write into low order latch
Write into high order latch I Write into high order counter
l H L H Transfer low order latch into 'ow order counter Reset Tl interrupt flag
l H H L Write low order latch
X H H H Write high order latch Reset Tl interrupt flag
Reading the Timer 1 Registers
For reading the Timer 1 registers, the four addresses relate directly to the four registers as follows:
RS3 RS2 RSl RSO Operation (R/W - H)
l H l l Read Tl low order COUnter Reset Tl interrupt flag
L H L H Read T 1 high order counter
L H H L Read Tl low order latch
L H H H Read Tl high order latch
TIMING CHARACTERISTICS
Read Timing Characteristics (loading 130 pF and one TTL load)
Parameter
Delay time, address valid to clock positive transition
Delay time, clock positive transition to data valid on bus
Peripheral data setup time
Data bus hold time
Rise and fall time for clock input
PHASE TWO CLOCK
Symbol Min Typ
TACR 180
TCDR
TpCR 300
THR 10
TRC TRF
k---~--~--~--~~-------------~4V
ADDRESS ---~!!: ,.~--+--t---+-----------O.4V
PERIPHERAL DATA
w--------~--+---------------2.4V
T OAV !r---""I- - _H~_ - - _ - __ -2.4V
DATA BUS
- - - - - -- O.4V Read Timing Characteristics
Write Timing Characteristics
Parameter
Enable pulse width
Delay time, address valid to clock positive transition
Delay time, data valid to clock negative transition
Delay time, read/write negative transition to clock positive transition
Data bus hold time
Delay time, Enable negative transition to peripheral data valid
Delay time, clock negative transition to peripheral data valid CMOS (VCC - 30%)
PHASE lWO CLOCK
ADDRESS
READJWRITE
DATA BUS
PERIPHERAL DATA
Symbol Min Typ
TC 0.47 -
TACW 180 -
TDCW 300 -
TWCW 180 -
T HW 10 -
TCpW - -
TCMOS - -
- .... ------O.4V J----I~
,.......---;.;;;..-.------- 2.4V
- - - - - - - - - O.4V -----VCC
"WO--------2.4V
Write Timing Characteristics
Max Unit ~ nS
395 nS
nS
nS
25 nS
Max Unit
25 ",S
- nS
- nS
- nS
- nS
1.0 ",S
2.0 IlS
1/0 Timing Characteristics
Characteristic Symbol Min Typ
Rise and fall time for CA 1, CB 1, CA2 and CB2 input signals TRF - -Delay time, clock negative transition to CA2 negative TCA2 - -transition (read handshake or pulse model
Delay time, clock negative transition to CA2 positive T RSl - -transition (pu'lse model
Delay time. CA 1 active transition to CA2 positive transition TRS2 - -(handshake model
Delay time. clock positive transition to CA2 or 'CB2 negative TWHS - -transition (write handshake)
Delay time, pertpheral data valid to CB2 negative transition TDC 0 -
Delay time. clock positive transition to CA2 or CB2 positive TRS3 - -transition (pulse model
Delay time, CBl active transition to CA2 or CB2 positive TRS4 - -transition (handshake mode)
Dt=lay time, peripheral data valid to CA 1 or CBl active TIL 300 -transition (input latching)
Delay time CB 1 negative transition to CB2 data valid TSRl - -(Internal SR clock, shift out)
Delay hme, negative transition of CBl input clock to CB2 data TSR2 - -valid (external clock, shift out)
Delay time, CB2 data valid to positive transition of CBl clock TSR3 - -(shift In, internal or external clock)
Pulse Width - PB6 Input Pulse TIPW 2 -
Pulse Width - CBl Input Clock T ICW 2 -Pulse Spacing - PB6 Input Pulse liPS 2 -Pulse Spacing - CSl Input Pulse IICS 2 -
_~c
PB6 INPUT PULSE COUNTING MODE
cT-=x-_-_-_-_-_-_-_:: CB2 SERIAL _____________ --'~--___ 2.4V DATA IN ~
t----T.CW----t
CBl CLOCK
t--_ ...... T SR2 -------------~ ~---------------~4V
CB2SERIAL DATA OUT --------- -,...--------O.4V
I/O Timing Characteristics
Max Unit
1.0 lAS
1.0 lAS
1.0 lAS
2.0 lAS
1.0 lAS
1.5 lAS
1.0 lAS
2.0 lAS
- ns
300 ns
300 ns
300 ns
- lAS
- lAS
- lAS
- liS
Timer 1 Operating Modes
Two bits are provided in the Auxiliary Control Register to allow selection of the Tl operating modes. These bits and the four possible modes
are as follows:
ACR7 ACR6
Output "Free-Run"
Enable Enable Mode
0 0 Generate a single time-out interrupt each time Tl is loaded
0 1 Generate continuous interrupts
1 0 Generate a single interrupt and an output pulse on PB7 for each Tl load operation
1 1 Generate continuous interrupts and a square wave output on PB7
FUNCTION CONTROL Control of the various functions and operating modes within the R6522 is accomplished primarily through two registers, the Peripheral Con·
trol Register (PCR), and the Auxiliary Control Register (ACRI. The PCR is used primarily to select the operating mode for the four peripheral
control pins. The Auxiliary Control Register selects the operating mode for the I nterval Timers (Tl, T2), and the Serial Port (SR).
Peripheral Control Register
The Peripheral Control Register is organized as follows:
Bit (I 7 I 6 I 5 4 3 I 2 I 1 0
Function CB2 Control CBl CA2 Control CAl Control Control
Typical functions are shown below:
peR3 peR2 peRl Mode
0 0 0 Input mode - Set CA2 interrupt flag (lFRO) on a negative transition of the input signal. Clear IF RO on a read or write of the Peripheral A Output Register.
0 0 1 I ndependent interrupt input mode - Set I FRO on a negative transition of the CA2 input sig·
nal. Reading or writing ORA does not clear the CA2 interrupt flag.
0 1 0 Input mode - Set CA2 interrupt flag on a positive transition of the CA2 input signal. Clear
IFRO with a read or write of the Peripheral A Output Register.
0 1 1 Independent interrupt input mode - Set IFRO on a positive transition of the CA2 input sig-
nal. Reading or writing ORA does not clear the CA2 interrupt flag.
1 0
I 0 Handshake output mode - Set CA2 output Iowan a read or write of the Peripherai A Output
Register. Reset CA2 high with an active transition on CA 1.
1 0 1 Pulse output mode - CA2 goes low for one cycle following a read or write of the Peripheral
A Output Register.
1 1 0 Manual output mode - The CA2 output is held low in this mode.
1 1 1 Manual output mode - The CA2 output is held high in this mode.
Auxiliary Control Regist.r
Many of the functions in the Auxiliary Control Register have been discussed previously. However, a summary of this register is presented here as a convenient reference for the R6522 user. The Auxiliary Control Register is organized as follows:
Bit' 7 I 6 5 4 I 3 f 2 1 0
T2 PB PA Function Tl Control Control Shift Register Control Latch Latch
Enable Enable
Shift Register Control
The Shift Register operating mode is selected as follows:
ACR4 ACA3 ACR2 Mode
0 0 0 Shift Register Oisabled.
0 0 1 Shift in under control of Timer 2.
0 1 0 Shift in under control of system clock.
0 1 1 Shift in under control of external clock pulses.
1 0 0 Free-running output at rate determined by Timer 2.
1 0 1 Shift out under control of Timer 2.
1 1 0 Shift out under control of the system clock.
1 1 1 Shift out under control of external clock pulses.
T2 Control
Timer 2 operates in two modes. If ACR5 '" O. T2 acts as an interval timer in the one-shot mode. If ACR5 '" 1, Timer 2 actS to count a pre· determined number of pulses on pin PB6.
PART NUMBER R6545-1
'l'Rockwell . R6500 Microcomputer System
DATA SHEET
CRT CONTROLLER (CRTC)
DESCRIPTION
The R6545-1 CRT Controller (CRTC) .is designed to interface an &-bit microprocessor to CRT raster scan video displays, and adds an advanced CRT controller to the established and expanding line of R6500 prodUcts.
The R6545-1 provides refresh memory addresses and character generator row addresses which allow up to 16K characters with 32 scan lines per character to be addressed. A major advantage of the R6545-1 is that the refresh memory may be addressed in either straight binary or by row/column.
Other functions in the R6545-1 include an intemal cursor register which generates a cursor ou1put when its contents are equal to the current refresh address. Programmable cursor start and end registers allow a cursor of up to the full character scan in height to be placed on any scan lines of the character. Variable cursor display blink rates are provided. A light pen strobe input allows capture of the current refresh address in an intemallight pen register. The refresh address lnes are configured to provide direct dynamic memory refresh.
All timing for the video refresh memory signals is derived from the character clock input. Shift register, latch, and multiplex control signals (when needed) are provided by external high-speed timing. The mode control register allows noninterlaced video display modes at 50 or 60 Hz refresh rate. The internal status register may be used to monitor the R6545-1 operation. The RES input allows the CRTC-generated field rate to be dynamically-synchronized with line frequency jitter.
ORDERING INFORMATION
Part Package Number Type
R6545-1P Plastic R6545-1AP Plastic R6545-1C Ceramic R6545-1AC CeramiC
c RodlweII 1nIem8lJon8l Corporation 1980 All RighIa ResenIed Prineed in U.S.A
Frequency
1 MHz 2 MHz 1 MHz 2 MHz
Temperature Range
O"C to +70°C O°C to + 70°C O°C to +70°C O°C to +70°C
FEATURES
• Compatible with 8-bit microprocessors
• Up to 2.5 MHz character clock operation
• Refresh RAM may be configured in row/column or straight binary addressing
• Alphanumeric and limited graphics capability
• Up and down scrolling by page. line, or character
• Programmable Vertical Sync Width
• Fully programmable display (rows, columns, character matrix)
• Non-interlaced scan
• SOI60 Hz operation
• Fully programmable cursor
• Light pen register
• Addresses refresh RAM to 16K characters
• No external DMA required
• Internal status register
• 4O-Pin ceramic or plastiC DIP
• Pin-compatible with MC6845
• Single + 5 ± 5% Volt Power Supply
vss i!ift LPEN CCO/MAO
CC1/MA1
CC2/MA2
CC3/MA3 CC4IMA4
CC51MA5
CC8/MAS
CC7/MA7
CRO/MAS
CR1/MA9
CR2/MA10
CR3/MA11
CR4IMA12
CR6/MA13 DISPLAY ENABLE
CURSOR
VCC
R6545-1 Pin ConflgUl1ltlon
VSYNC
HSYNC
RAO
RA1
RA2
RA3 RA4
00
0' 02 03 04 06 OS
07
Ci RS
~2
Rlii CCLK
SpecilCIIIIOne ~ 10 change wtthcM noIIce Ooou..,.. No. ~ DI7
DIC ..... '.
n :a -t n o z ~ :u o rrm :u ~
o :a -4 o ~
INTERFACE SIGNAL DESCRIPTION
CPU INTERFACE
_2 (Ph ... 2 Clock)
The input clock is the system Phase 2 (~) ctock and is used to trigger all data transfers between the system processor (CPU) and the R6545-1. Since there is no maximum limit to the allowable _2 clock time, it is not necessary for it to be a continuous clock. This capability permits the R6545-1 to be easily interfaced to non-65OO compatible microprocessors.
R/W (Read/Write)
The R/W input signal generated by the processor is lJS8I'I to control the direction of data transfers. A high on the R/W pin allows the processor to read the data supplied by the R6545-1, a Iowan the R/W pin allows data on data lines DO-D7 to be written into the R6545-l.
CS (Chip Select)
The Chip Select input is normally oonnected to the processor address bus either directly or through a decoder. The R6545-1 is selected when· ~ is low.
RS (Register Select)
The Register Select input is used to access internal regiSters. A low on this pin permits writes (RiW.= low) into the Address Register and reads (R/W = high) from the Status Register. The contents of the Address Register is the identity of the register accessed when RS is high.
DO-D7 (Data Bus)
00-07 are the eight data lines used to transfer data between the processor and the R6545-1. These lines are bidirectional and are normally high-impedance except during read cycles when the chip is selected (~ = low).
VIDEO INTERFACE
HSYNC (Horizontal Sync)
The HSYNC signal is an active-high output used to determine the horizontal position of displayed text. It may drive a CRT monItor directly or may be used for composite video generation. HSYNC time position and width are fully programmable.
VSYNC (Vertical Sync)
The VSYNC signal is an active high output used to determine the vertical position of displayed text. Like HSYNC, VSYNC may be used to drive a CAT monitor or composite video generation circuits. VSYNC time position and width are both programmable.
DISPLA Y ENABLE (Display Enable)
The DISPLAY ENABLE signal is an active-high output used to indicate when the R6545-l is generating active display information. The number of horizontal display characters per row and the number of vertical display rows are both fully programmable and together are used to generate the DISPLAY ENABLE signal. OISPLA Y ENABLE can be delayed one character time by setting bit 4 of AS equal to 1.
CURSOR (Cursor CoincldenC8)
The CURSOR signal is an active-high output used to indicate when the scan coincides with the programmed cursor position. The cursor position may be programmed to be any character in the address field. Furthermore, within the character, the cursor may be programmed to be any block of scan lines, since the start scan line and the end scan line are both programmable. The cursor position may be delayed by one character time by setting Bit 5 of RS to A "1".
LPEN (Ught Pen Strobe)
The LPEN signal is an edge-sensitive input used to load the internal Ught Pen Register with the contents of the Refresh Scan Counter at the time the active edge occurs. The active edge of LPEN is the low-ta-high transition.
CCLK (Clock)
The CClK signal is the character timing clock input and is used as the time base for all internal count! control functions.
REI The ~ signal is an active-low input used to initialize all intemal scan counter circuits. When RES is low, all intemal counters are stopped and cleared. all scan and video outputs are low, and control registers are unaffected. RES must stay low for at least one CCLK period. An scan timing is initiated when ~ goes high. In this way, RE'S can be used to synchronize display frame timing with line frequency. RES may also be used to synchronize multiple CRTC's in horizontal and/or vertical split screen operation.
REFRESH RAM AND CHARACTER ROM INTERFACE
MAD-UA13 (Refresh RAM Address Unes)
These 14 signals are active-high outputs used to address the .Refresh RAM for character storage and display operations. The starting scan address is fully programmable and the ending scan address is determined by the total number of characters displayed, which is also programmable. in terms of charactersl line and !enes/f!'"a.rne.
There are two selectable address modes for MAO-MA 13:
In the straight binary mode (RS, Mode Control, bit 2 = "0"), characters are stored in successive memory locations. Thus, the software must be designed such that row and column character coordinates are translated into sequentially-numbered addresses. In the rOW/column mode (RS, Mode Control, bit 2 = "1"), MAO-MA7 become column addresses CCO-CC7 and MASMA13 become row addresses CAO-CAS. In this case, the software can manipulate characters in terms of row and column locations, but additional address compression circuits are needed to convert the CCO-CC7 and CAO-CAS addresses into a memory-effiCient binary address scheme.
RAG-RA4 (Raster Address Lines)
These 5 signals are active-high outputs used to select each raster scan within an individual character row. The number of raster scan lines is programmable and determines the character height. including spaces between character rows.
INTERNAL REGISTER ORGANIZATION
Addr .. Register RNd Write Regist ... Bit Reg. (RIW- (RIW-
CS RS 4 3 2 1 0 No. Register Name Rigister Units High) Low) 7 6 5 4 3 2 1 0
1 X X X X X X X / V V V / V / 0 0 X X X X X X Address Register Register No. V / / V 4 3 2 1 0 0 0 X X X X X X Status Register -. V :/ 6 5V 1,/ V V 0 1 0 0 0 0 0 RO Horizontal Total Char No. of Characters/Row V 7 6 5 4 3 2 1 0 0 1 0 0 0 0 1 Rl Horizontal Displayed Char No. of Characters/Row V 7 6 5 4 3 2 1 0 0 1 0 0 0 1 0 R2 Horizontal Sync Position Character Position V 7 6 5 4 3 2 1 0 0 1 0 0 0 1 1 R3 YSYNC, HSYNC Widths No. of Scan Lines, Characters V 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 R4 Vertical Total Rows No. of Character Rows V / 6 5 4 3 2 1 0 0 1 0 0 1 0 1 R5 Vertical Total Adiust Lines No. of Scan Lines V / V V 4 3 2 1 0 0 1 0 0 1 1 0 R6 Vertical Displayed Rows No. of Character Rows V / 6 5 4 3 2 1 0 0 1 0 0 1 1 1 R7 Vertical Sync Position No. of Character Rows V V 6 5 4 3 2 1 0 0 1 0 1 0 0 0 RS Mode Control - V 7 6 5 4 3 2 1 0 0 1 0 1 0 0 1 R9 Scan Line No. of Scan Lines V V V V 4 3 2 1 0 0 1 0 1 0 1 0 Rl0 Cursor Start Line Scan Line No. V V 6 5 4 3 2 1 0 0 1 0 1 0 1 1 Rll Cursor End Line Scan Line No. V .v ./ V 4 3 2 1 0 0 1 0 1 1 0 0 R12 Display Start Address (HI - V V / 5 4 3 2 1 0 0 1 0 1 1 0 1 R13 Display Start Address (U - V 7 6 5 4 3 2 1 0 0 1 0 1 1 1 0 R14 Cursor Position Address (H) - V V V V 5 4 3 2 1 0 0 1 0 1 1 1 1 R15 Cursor Position Address (LI - V V 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 R16 Light Pen Register (HI - V V 1/ 5 4 3 2 1 0 0 1 1 0 0 0 1 R17 Light Pen Register (U - V 7 6 5 4 3 2 1 0
Table 1. Overall Register Structure and Addressing
GND STATUS REGISTER (SR)
VIDEO ifF
DO-D7 ---.......... ---.... ~-........... HSYNC
This 8-bit register contains the status of the CATC. Only two bits are assigned, as follows:
02--"RM ---I ... CS--'" RS--~~~ ____ -.~
MAO-MA 13 RAO-RA4
VSYNC DISPLAY ENABLE CURSOR LPEN CCLK RES
REFRESH RAM AND CHARACTER ROM
R6545-1 Interface Diagram
INTERNAL REGISTER DESCRIPTION
ADDRESS REGISTER
This 5-bit write-only register is used as a "pointer" to direct CATC/CPU data transfers within the CATC. Its contents is the number of the desired register (0-17). When CS and AS are low, then this register may be loaded; when CS is low and AS is high, then the register selected is the one whose identity is stored in this address register.
\ ) v
L.I ----NOT USED
Vertical R. TrKe (VAT) o - Scan is not currMtly in its venal ,.trKe time. 1 - Scan is cur ... ntly in its vena ,.trKe time.
Not. t .... this bit Ktu.l.y goes to a ", •• when veniAl ,.tr_ 1UrU. but goes to • "0" five charKter dock time. before __ a' ... ·tr_ en.. 10 that critic:lll timings for ref...... AAM operatioftl .... avoided.
L----LPEN Aegist..- Full (lAFI
o - A •• r R16 or A17 h. been ... 8d by the CPU.
, • lPEN strobe h_ been ... ceived.
L-____ Not lJaa:1
NOTE: The StatuI Register t8k" the State. I -I 0 11 I -1-1 -I -1 - I immediately after power IVec' turn-()n.
Ao-HOAIZONTAL TOTAL CHARACTERS
This &-bit write-only register contains the total of displayed and non-displayed characters, minus one, per hortzontaJ line. The frequency of HSYNC is thus determined by this register.
R1-HOAIZONTAL DISPLAYED CHARACTERS
This &-bit write-only register contains the number of displayed characters per horizontal line.
R2-HOAlZOHTAL SYNC POsmoN
This 8-bit wrlte-only register contains the position of the h0rizontal SYNC on the horizontal line, in terms of the character location number on the tine. The position of the HSYNC determines the left to right location of the displayed text on the video screen. In this way, the side margins are adjusted.
A3-HORIZONT AL AND VERnCAL SYNC WIDTHS
1'Ns 8-bit wfile:-9n1y register contains the widths of both HSVNC and VSYNC, as follows:
The width of eM horizon ... sync puIM CHSYHCt in the ....... of dlMecter cIocIl __ fCCLKI.
~------- VSYHC "'_ Width The width of the wert_ sync
pulle fVSYNC. in the ........ of -=an Ii... When' bits .. 7 .. ' eI' "0", VSYNC will be , ..... linea wide.
Control of these parameters allows the R654S-1 to be interfaced to a variety of CRT monitors, since the HSVNC and VSYNC timing signals may be accommodated without the use of external one shot hming.
R4-VERnCAl TOTAL ROWS
The Vertical Total Register is a 7-bit register contairingthe total number of character rows in a frame, minus one. This register, along With RS. determines the overall frame rate, which should be dose to the line frequency to ensure flicker-free appearance. " the frame time is adjusted to be longer than the period of the line frequency. then RES may be used to provide absolute synchronasm.
tiS-VERTICAL TOTAL LINE ADJUST
The Vertical Total Line Adjust Register (RS) is a 5-bit write-only regl~ter containing the number of additional scan lines needed to complete an entire frame scan and is intended as a fine adjustment for the video frame time.
R6-VERTICAl DISPLAYED ROWS
ThiS 7-blt write-only register contains the number of displayed character rows in each frame.
R7-VERTlCAL SYNC POSITION
ThIs 7-b1 Wf'ite.()nIy register is used to I8Iect the character raw time at which the verticaJ SYNC pulse Is desired to occur and, thuI, Is uaed to position the dsp1ayed text in the Y8IticaI drection.
Rl-IIODE CONTROL (MC)
This 8-bII write-onIy register selects the operating modes of the R8545-1, as follows:
, _,. • a I 1 •
IleJ lICe lICe IICt
- - CIIC oat
IICJ
• Ilea 1le1 .. .AO _
0
~ ... ~IO·o_VIM
~ .... -. .. , -... __ .... I"AOI .......... -" ..... ~
~- .... _10 ......
0...... _ .... 1011' .... .. -.. ...." ....".,....._---c...- ..... ICIIlI . -.. -...." , ... _c...- ___ .
}--Rt-ROW SCAN UNES
This 5-bit writ&-anly register contains the number of scan lines. minus one, per character row, including spacing.
R1D-CURSOR START UNE A11-CURSOR END UNE
These 5-bit write-only registers select the starting and ending acan lines for the cursor. In addition, bits 5 and 6 of R10 are
. used to select the cursor blink mode, as follows:
Bit ..!...
o o 1 1
Bit i
o 1 o 1
CurlOr Blink Mode
Display Cursor Continuously Blank Cursor Continuously Blink Cursor at 1/16 Field Rate Blink Cursor at 1/32 F 'eld Rate
R12-DlSPLA Y START ADDRESS HIGH R13-DlSPLAY START ADDRESS LOW
These registers form a 14-bit register' whose contents is the memory address of the first character of the displayed scan (the character on the top left of the video display, as in Figure 1). Subsequent memory addresses are generated by the R6S45-1 as a resutt of CCLK input pulses. Scrolling of the display is ac· compIished by changing R 12 and R13 to the memory address associated with the first character of the desired line of text to be displayed first. Entire pages of text may be scrolled or changed as well via R12 and R13.
N~R OF HORIZONTAL TOTAL CHARACTERS (ROI
r~----------------------A~------------__ ~--~, .-ER OF HORIZONTAL DISPLAYED CHARACTERS (R11
r_--------------JA~--------------_, DISPLAY START ADDRESS HIGH (R121-
L'D1SPLAY START ADDRESS LOW (R131-
11I1I1i1l1l1l1l1l1!1I1I1I1I1I1I~lIlIlIlIlIiI~l N~R~ r SCAN LIND (RII
~ ,;: _~ ITAIIT LINE (1111.
~ ~CU~DR END LINE '"11)
NU_EROF VERTICAL DISPLAV ROWS
\~I IIMnIl POSITION ADDRESS HIGH 'R141 CURSOR POSITION ADDRESS LOW (R11t
NUMBER OF VERTICAL TOTAL ROWS (R41
(R81
DISPLAY PERIOD
HORIZONTAL RETRACE PERIOD CNON-DISPLA VI
VERTICAL RETRACE PERIOD (NON-DISPLA Yt
Figure 1. Video Display Format
R14-CUASOR POSITION HIGH R15-CUASOR POsmON LOW
These registers fonn a 14-bit register whose contents is the memory address of the current cursor position. When the video display scan counter (MA lines) matches the contents of this register. and when the scan line counter (RA lines) falls within the bounds set by R10 and R11. then the CURSOR output becomes active. Bit 5 of the Mode Control Register (RS) may be used to delay the CURSOR output by a full CCLK time to accommodate slow access memories.
R16-UGHT PEN HIGH A17-UGHT PEN LOW
These registers fann a 14-bit register whose contents is the light pen strobe position, in terms of the video display address at which the strobe occurred. When the LPEN input changes from low to high. then. on the next negative-going edge of CCLK, the contents of the internal scan counter is stored in registers R16 and R17.
REGISTER FORMATS
Register pairs R12/R13, R14/R15, and R16/R17 are formatted in one of two ways:
(1) Straight binary, if register AS, bit 2 = "0".
(2) Row/Column, if register RS, bit 2 = "1". In this case the low byte is the Character Column and the high byte is the Character Row.
DESCRIPTION OF OPERATION
VIDEO DISPLAY
Figure 1 indicates the relationship of the various program registers in the R6545-1 and the resultant video display.
Non-displayed areas of the Video Display are used for horizontal and vertical retrace functions of the CRT monitor. The horIzontal and vertical sync signals, HSYNC and VSYNC, are programmed to occur during these intervals and are used to trigger the retrace in the CRT monitor. The pulse widths are c0nstrained by the monitor requirements. The time position of the pulses may be adjusted to vary the display margins (left, right. top, and bottom).
REFRESH RAM ADDRESSING
Shared Memory Mode (A8, bit 3 = "0")
In this mode, the Refresh RAM address lines (MAO-MA 13) directly reflect the contents of the internal refresh scan charader counter. Multiplex control, to pennit addressing and selection of the RAM by both the CPU and the CRTC, must be provided external to the CRTC. In the Row/Column address mode, lines MAQ-MA7 become character column addresses (CCO-CC7) and MA8-MA13 become character row addresses (CRO-CR5).
ADDRESSING MODES
Row/Column
In this mode, the CRTC address Hnes (MAo-MA13) are generated as 8 column (MAo-MA7) and 6 row (MA8-MA13) addresses. Extra hardware is needed to compress this addressing into a straight binary sequence in order to conserve memory in the refresh RAM.
Binary
In this mode, the CRTC address lines are straight binary and no compression circuits are needed. However, software complexity is increased since the CRT characters cannot be stored in tenns of their row and column locations, but must be sequential.
USE OF DYNAMIC RAM FOR REFRESH MEMORY
The R6545-1 permits the use of dynamic RAMS as storage devices for the Refresh RAM by continuing to increment memory addresses In the non-display intervals of the scan. This is 8 -viable technique, since the Display Enable signal controls the actual video display blanking. Figure 2 iHustrates Refresh RAM addressing for the case of binary addressing for 80 co~mns and 24 rows with 10 non-displayed columns and 10 non-displayed rows.
TOTAL-to
DISPLAY -10
0 1 2 J 76 71 78 79 80 81 89
80 81 82 83 156 157 158 159 160 161 169
160 161 162 237 238 239 240 249
240 241 242 317 318 31g 320 329 t---r---~'
I I
1680 1681 1682 1757 11758 1759 1760 1769
1760 1761 1762 I 1837 1838 1839 1840 1849
1840 1841 1842 1917 1918 1919 lt20 1929
1920 1921 1922 1997 1998 15199 2000 2009
2000 2001 2002 2077 2078 2079 2080 2089
2640 2641 164' 2?~ l' 2718 2120 2729
Figure 2. Memory Addressing Example (SO x 24)
CURSOR OPERAnON
A one character wide cursor can be controlled by storing values Into the Cursor Start Line (R10) and Cursor End Une (R11) registers and into the Cursor POSition Address High (R14) and Cursor Position low (R15) registers.
I
BIts 5 and 6 In the Cursor Start Line High Register (R10) control the cursor dlaplay and blink rate 88 follows:
BitS Bit 5 Cu~r Operat" Mode I 0 0 Dtspley Cursor Continuously
I 0 , Blank Cursor ContinuC"ISly 1 0 Blink Cursor at 1/16 Field Rete 1 1 Blink Cursor et 1/32 Field Rete
The cursor of up to 32 characters in height can be displayed on and between the scan lines as loaded into the Cursor Start Une (R10) and Cursor End Une (R11) Registers.
The cursor is positioned on the screen by loading the Cursor Position Address High (R14) and Cursor Position Address Low (R15) registers with the desired refresh RAM address. The cursor can be positioned in any of the 16K character positions. Hardware paging and data scrolling is thus allowed without loss of cursor position. Figure 3 is an example of the display cursor scan i08.
UNDERLINE CURSOR
OVERLINE CURSOR
o o~~++~~ 1 1~""~~ 2 2-H~++~~ 3 3-H~++~-4 4-H~++~-6 &-H .... 4H-6 6-H~++4H~ 7 7-H~++4H-8 8-H~++~-9 9-rr+++~-
10 10-+-r+++~-11 11 -+-+-+++-+-I~
CURSOR START CURSOR START LINE .. 9 LINE - 1
CURSOR END LINE - 9
CURSOR END LINE .. 1
BOX CURSOR
CURSOR START LINE - 1
CURSOR END LINE - 9
Figure 3. Cursor Display Scan Une Control Examples
MPU WRITE TIMING CHARACTERISTICS
(V cc·· 5.0V ±5", T A • 0 to 70°C, unless otherwise noted)
1 MHz 2 MHz
Ch8racteriltic Symbol Min Max Min Mex Unit
Cycle Time TCYC 1.0 - 0.5 - 1'1 .2 Pulse Width TC 440 - 200 - ns
Addresl Set-Up Time TACW 180 - 90 - ns
Address Hold Time TCAH 0 - 0 - ns
RtW Set-Up Time TWCW 180 - 90 - nl
RNi Hold Time TCWH 0 - 0 - ns
Oata Bus Set-Up Time TOCW 265 - 100 - ns
Data Bus Hold Time THW 10 - 10 - nl
Itr end t f • 10 to 30 ns)
WRITE CYCLE
TCYC
TC
2.0V 2.0V 2.0V 4>2
TACW TCAH
2.0V 2.0V CS. RS
O.IV O.8V
TWCW
RNi
TOCW THW
00-07
MPU READ TIMING CHARACTERISTICS
IV cc :: 5.0V ±5%. T A .. 0 to 70°C. unless otherwise noted)
1 MHz 2 MHz
Charachlristic Symbol Min Max Min Max Unit
Cycle Time TCYC 1.0 - 0.5 - ,",S
02 Pulse Width TC 440 - 200 - ns
Address Set-Up Time TACR 180 - 90 - ns
Address Hold Time TCAR 0 - 0 -- ns
RIW Set-Up Time TWCR 180 - 90 - ns
Read Access Time TCDR - 340 - 150 ns
Read Hold Time THR 10 - 10 - ns
Data Bus Active Time (Invalid Data) TCOA 40 - 40 - ns
Ctr and tf "" 10 to 30 ns)
READ CYCLE
MEMORY AND VIDEO INTERFACE CHAAACTERISncs
'Wi :
eur-.ic8 5.,...... Min .... 0. .... Clock Cycle Time TCCY 0.4 40
Char. ClOCk Pulse Wodth TCCH 200 -MAO·MA 13 Propagation Delay T
MAO - 300
RAO·RA4 Propagation Oelav TRAO - 300
DISPLAY ENABLE Prop. Delay TOTO - 450
HYSNC PropagatIon Delay THSD - 450
VSYNC Propagation TVSD - 450
Cursor ProPagation Delay TCDD - 450
LPEN Strobe Width T LPH 150 -LPEN to CCLI( Delay T LPI 20 -CCLI( to LPEN Delay T LP2 0 -
fr. tf - 20 ns (mad
SYSTEM TIMING DEFINITIONS
~------------TCCY--------------~
CClK
SIGNAL" (See Belowl
2.0V
• SIGNAL
MAO-MAl 3
RAO-RA4
DISPLAY ENABLE
HSYNC
VSYNC
CURSOR
LIGHT PEN STROBE TIMING DEFINITIONS
CClK
LPEN
SEE NOTE
SIGNAL SYMBOL 1)(1
TMAD
TRAD
TOTO
THSo
TV SO
TCOD
~iooiHz
Min .... Uftita
0.4 40 JlI
200 - nl
- 300 ns
- 300 ns
- 450 ns
- 450 nl
- 450 ns
- 450 ns
150 - ns
20 - ns
0 - ns
,'--
MAO-MA13---,~,---_n+1-----....11,---_n+_2 _[
NOTE:
SLASH AREA DEFINES THE "WINDOW" IN WHICH AN LPEN POSITIVE EDGE WILL CAUSE ADDRESS N+2 TO LOAD INTO LIGHT PEN REGISTER. TRANSITIONS ON EITHER SlOE OF THIS ''WINDOW'' WILL RESULT IN UNPREDICTABLE VALUES BEING LOADED INTO THE LIGHT PEN REGISTER
SPECIFICATIONS
~aximum Ratings
Rating Symbol Value Unit
Supply Voltage Vee -0.3 to +7.0 Vdc
Input Voltage Y,N -0.3 to +7.0 Vdc
Operating Temperature Range TOp o to ... 70 °e
Storage Temperature TSTG -55 to 150 °e
All inputs contain protection circuitry to prevent damage due to high static discharges. Care should be taken to prevent unnecessary applica' tion of voltages in excess of the allowable limits.
Electrical Characteristics
IV ce = 5.0V .15%. T A = 0·7 oOe. unless otherwise noted)
Characteristic Symbol Min Max Unit'
Input High Voltage V1H 2.0 Vee Vdc
Input Low Voltage V1L 0.3 0.8 Vdc
Input Leakage (1)2. RtW. ~. es-. RS. LPEN. eeLK) liN - 2.5 #'Adc
Three·State Input Leakage (00·07)
(V IN = 0.4 to 2.4V) 'TS1 - 10.0 IJAdc
Output High Voltage
ILOAo • 205 JJAdc (00·07) VOH 2.4 - Vdc
ILOAO
= 100 IJAdc (all others)
Output Low Voltage
I LOAD - 1.6 mAde VOL - 0.4 Vde
Power Dissipation Po - 1000 mW
Input Capacitance
02.RAN.RES,CS,RS,LPEN,CCLK e lN - 10.0 pF
00·07 - 12.5 pF
Output Capacitance e OUT - 10.0 pF I I I I I
TEST LOAD
Vee
2.4Kll
R8M5-1 PIN
130pF I R
R-11KQ FOR 00·07
-24KO FO~ ALL OTHER OUTPUTS
PART NUMBER R6551
'1' Rockwell R6500 Microcomputer System
DATA SHEET
Asynchronous Communication Interface Adapter (ACIA) The R6551 Asynchronous Communication Interface Adapter
(ACIA) provides a program-controlled interface between B-bit
microprocessor·based systems and serial communication data
sets and modems.
With its on-chip baud rate generator, the R6551 is capable of
transmitting at 15 different program-selectable rates between
50 baud and 19,200 baud, and receiving at either the transmit
rate or at 16 times an external clock rate. The R6551 has pro
grammable word lengths of 5, 6, 7, or 8 bits; even, odd or no
parity; 1, 1·1/2 or 2 stop bits.
With the R6551, a crystal is the onlV required external support
component - eliminating the multiple-component support that
is typically needed.
In addition, the R6551 is designed for maximum programmed
control from the CPU, to simplify hardware implementation. A
control register and a separate command register permit the CPU
to easily select the R6551's operating modes and check data,
parameters and status.
Ordering Information
Order Package Temperature Number Type Frequency Range
R6551P Plastic 1 MHz OOC to +700 C
R6551AP Plastic 2MHz OOC to +700 C
R6551C Ceramic 1 MHz OOC to +700 C
R6551AC Ceramic 2 MHz OOC to +700 C
VSS ANi
CSO tl2 CS1 IAQ
RES 07 AxC 06 XTLI 05 XTLO 04 A'fS 03
CTS 02 TxO 10 01
OTA 11 DO AxO 12 DSA ASO 13 OeD
AS1 14 vce
R6551 Pin Configuration
(t) Rockwell International Corporation 1981 All Rights Reserved Printed In U S.A
FEATURES
e Compatible with B-bit microprocessors
e Full duplex or half duplex operation with buffered receiver and transmitter
e 15 programmable Baud Rates (50 to 19,200)
e Receiver data rate may be identical to baud rate or may be 16 times the external clock input
e Data set/modem control functions
e Programmable word lengths, number of stop bits, and parity bit generation and detection
e Programmable interrupt control
e Software reset
e Program-selectable serial echo mode
e Two chip selects
• 2 MHz or 1 MHz clock rate
e Single +5V ±.5% power supply
e 2B-pin plastic or ceramic DIP
e Full TTL compatibility
00-07 <::8
IRQ
RIW
CSO
CS1
RSO
RS1
912
RES
VCC
VSS
DATA BUS BUFFERS
110 CONTROL
TIMING & CONTROL LOGIC
TRANSMIT DATA & SHIFT REGISTERS
RECEIVE DATA & SHIFT REGISTERS
"--CTS
I---I~ T.xD
~--DCD
"--DIR ......... -tI~ RxC
"--XTLI
~-"'XTLO
0T1f
RTS
RxD
R6551 Interface Diagram
Speclf,callons subJecl 10 change Wllhout nOllce
Document No_ 29000 053 Rev_ 1, Jenuary 1981
:t:-en < ::J n ::r .. o ::J o c: en n o 3 3 c: ::J _. n i» :!'. o ::J -::J r+ CD ::l. C» n CD
» c. C» 'a r+ CD .. ~ n -» -
INTERNAL ORGANIZATION
ill
0001 hO
lAO OCD
Oii
AM 'bC
CSO XTlI
CS. XTLO
ASO eTA
AS' ATi
'1 A.O
AE~
R6551 BI')ck Diagram
Transmitter /Receiver
B,ts 0-3 of the Control Register select the divisor used to generate the
baud rate for the Transmitter- If the Receiver clock is to use the same
baud rate as the Transmitter, then RxC becomes an output pin and
can be used to slave other circuits to the R6551.
.... ~_--R.D
~~--------------------- R.e
XTLI
XTLO ~-~ ___ ~
REGISTER
Transmitter/Receiver Clock Circuits
Transmit and Receive Data Registers
These registers are used as temporary data storage for the 6551 Trans
mit and Receive circuits. The Transmit Data Register is characterized as follows:
• Bit 0 is the leading bit to be transmitted.
• Unused data bits are the high-order bits and are "don't care" for transmission.
The Receive Data Register is characterized in a similar fashion:
• Bit 0 is the leading bit received.
• Unused data bits are the high-order bits and are "0" for the receiver.
• PariTy bits are not contained in the Receive Data Register, but are stripped-off after being used for external parity checking. Parity and ail unused high-order bits are "0".
Control Register
The Control Register selects the desired baud rate, frequency source, word length, and the number of stop bits.
5 l' G
1"'---_____ SElECTED 84UO 114T£ 'YII'
32 10 ii Ii ii Ii 0001 00 10 00 1 1 01 00 0' 01 o 1 1 0 01 1 1 , 000 '0 0 1 10 I U 10 1 I 1 I 00 I I 01 , 1 10 1111
1&. 10' ..... , ClOd< 50 ...... 15 ...... 101.2 .. wei 13ol.51 ...... 150 ...... 300 ...... - ...... 1200 ...... 1_ ...... 2400 ...... 3100 ...... ......... 1200 ...... .......... ".200 .......
'---------- IIECEIVEA CLOCK IOUfICE IIICII
O· £._ ... 1"-1:_ I· .......... .
"'----------------------- WOAD LENGTH CWLI
Il! 00 • e •• 01 7 ... . 10 III .. . 11 5 ... .
L-_____________________ STOI' .IT NUMBEII laNI
0·' $0 ...... 1·;ZSooto •••
• III Sooto .... IF .... WL .5_No,.. .. yl
.,$0 .... .. IF ... WL •• _ ,.. .. yl
R6551 Control Register
Command Register
The Command Register controls specific modes and functions.
~DAT"TI_"L .. IADYlDT .. 1
o· Dele T ...... ,... ......,. 1M'll......, I • Dele T_......,. tGTW L8wt
wrl .... ~ IlIOUUT DIlAaLIO IIIIDI
0·11101_ I·IIIO~
TIllAlll8lltTTI .. INTI""~ COIIITIIOL !TICI
II iifI.H ... T, ____ ~
o I 11ft. L_. T'--~ I_ I 0 In'I. LGw. T ___ E_
I I IITI·L_.Tr_ ......... ~ T'_ ....... T""
'-------------- IIKEIVEII ECHO MODE IIIIMI
0· ...... - .... ' ........ E_ ....
'--------------- ""RITY MODE ENAaUD ..... ' O·,....,. .... D_ No ..... ..,. •• a-..t ".y~O_
' ... ..,. .... 1_
'----------------- '''"ITY MODE COIIfTIIOL If'IICI
I I
71543210
I~I~I~I:I: I: 1:1:1 ::.-=:= (J(ft
o 0 O",.. .. yT'~_ o I E_ "'.y T,---..", 0 _ "'.y.iI T, __ ,.. ..... ~O_ 1 I .... ,.. .. y ... T,_
"'.yC_D_1Id
R6551 Command Register
Status Register
The Status Register reports the status of various R6551 functions
l I 1 1 1 I I I. I L
o ,. No Partly Error 1 • P_tty Error Ol'leclad
F'." .... Error·
a • No FrJft'l'ng error 1 ,. fr~n .. ", Error Detected
O •• rrun·
O· No Overrun ~ • Overrun HM Occurred
Race,,,., Oll~ RergtS,er Full
O· No. FuM 1· Full
Troll"s"""., 011. Aeg,ster EmPty
O' No. Empty 1 • Empty
0 .. " Car,.., Detect ,i5Ci))
o • OeD 10 ... (OelOC,J 1 • oeD h.,.h INo. O ••••• odJ
D ••• Set R_y (OSRJ
o • OSR low (R_yl 1 • OSR hogh (No. R_yl
In ... ,up. IIROI
o • No In,errupt 1 • Int ..... upl Has Occu,,«t
It No tnt.fru," occurs for thew condlltO"'
R6551 Status Register
INTERFACE SIGNAL DESCRIPTION
REs (Resed
During system initialization a low on the RES input will cause internal registers to be cleared.
12 (Input Clock)
The input clock is the system 02 clock and is used to synchronize all data transfers between the system microprocessor and the R6551.
R/W (Read/Write)
The R/Iii is generated by the microprocessor and is used to control the direction of data transfers. A high on the R/iii pin allows the processor to read the data supplied by the R6551. A low on the Rm pin allows a write to the R6551.
IRQ (Interrupt Requesd
The T'Rn pin is an intJrrupt output from the interrupt control logic. It is an open drain output, permitting several devices to be connected to the common iRa microprocessor input. Normally a high level, iRa goes low when an interrupt occurs.
00-07 (Data Bus)
The 00-07 pins are the eight data lines used to transfer data between the processor and the R6551. These lines are bi-directional and are normally high-impedance, except during Read cycles when the R6551 is selected.
CSO, CSl (Chip Selects)
The two chip select inputs are normally connected to the processor address I ines either directly or through decoders. The R6551 is selected when CSO is high and CS1 is low.
RSO, RSl (Register Selects)
The two register select lines are normally connected to the processor address lines to allow the processor to select the various R6551 internal registers. The following table indicates the internal register select coding:
RSl RSO Write Read
0 0 Transmit Data Receiver Data Register Register
0 1 Programmed Status Register Reset (Data is "Don't Care")
1 0 Command Register
1 1 Control Register
Note that only the Command and Control registers are read/write. The Programmed Reset operation does not cause any data transfer, but is used to clear Bits 0 through 4 in the Command Register and Bit 2 in the Status Register.· The Programmed Reset is slightly different from the Hardware Reset (RES); these differences are described in the individual register definitions.
ACIA/Modem Interface Signal Description
XTLI. XTLO (Crystal Pinsl
These pins are normally directly connected to the external crystal (1.8432 MHz) used to derive the various baud rates. Alternatively, an externally generated clock may be used to drive the XTLI pin, in which case the XTLO pin must float. XTLI is the input pin for the transmit clock.
TxD (Transmit Data)
The TxD output line is used to transfer serial NRZ (non-return-tozero) data to the modem. The LSB (least significant bitl of the Transmit Data Register is the first data bit transmitted and the rate of data transmission is determined by the baud rate selected, or under control of an external clock (as selected by the Control Register).
RxD (Receive Data)
The RxD input line is used to transfer serial NRZ data into the ACIA from the modem, LSB first. The receiver data rate is e-ither the programmed baud rate or the rate of an externally generated receiver clock (as selected by the Control Registeri.
RxC (Receive Clock)
The RxC is a bi-directional pin which serves as either the receiver 16x clock input or the receiver 16x clock output. The latter mode results if the internal baud rate generator is selected for receiver data clocking.
RTS (Request to Send)
The RTS output pin is used to control the modem from the processor.
The state of the RTS pin is determined by the contents of the Com·
mand Register.
CTS (CI.ar to Sendl
The CTS input pin is used to control the transmitter operation. The
enable state is with CTS low. The transmitter is automatically dis
abled if CTS is high_
DTR (Data Terminal Ready)
This output pin is used to indicate the status of the R6551 to the
modem. A low on DTR indicates the R6551 is enabled and a high
indicates it is disabled. The processor controls this pin via bit 0 of
the Command Register.
READ/WRITE CYCLE CHARACTERISTICS
(Vec = 5.0V ±5%, T A = 0 to 700 C. unless otherwise noted)
Characteristic Symbol Min
Cycle Time tCYC 1.0
02 Pulse Width tc 400
Address Set-Up Time tAC 120
Address Hold Time tCAH 0
R/W Set-Up Time twc 120
RNi Hold Time tCWH 0
Data Bus Set-Up Time tDCW 150
Data Bus Hold Time tHW 20
Read Access Time (Valid Data) tCDR -Read Hold Time tHR 20
Bus Active Time (Invalid Datal tCDA 40
(tr and tf = 10 to 30 ns)
DSR (Data Set Ready)
The DSR input pin is used to Indicate to the R6551 the status of the
modem. A low indicates the "ready" state and a high, "not-ready".
DSR is a high-impedance input, and must be connected. If unused, it should be driven high or low, but not switched.
DCD (Data Carrier Detect)
The DCD input pin is used to indicate to the R6551 the status of the
carrier-detec~ output of the modem. A low indicates that the modem
carrier signal is present and a high, that it IS not. Like 5SR, DCD is a high-impedance input, and must be connected.
1 MHz 2MHz
Max Min Max Unit
40 0_5 40 J,JS
- 200 - ns
- 70 - ns
- 0 - ns
- 70 - ns
- 0 - ns
- 60 - ns
- 20 - ns
200 - 150 ns
- 20 - ns
- 40 - ns
1---------- tCYC --------.., tc I
~2
CSO, CS1. RSO. RSl
RM
Write Timing Characteristics
Read Timing Characteristics
.r-----V'H
V'l
~~~"""""V'H
~~~"",,~v'l
I.----------V'H
v'l
TRANSMIT/RECEIVE CHARACTERISTICS
1 MHz 2MHz
Characteristic Symbol Min Max Min Max Unit
Transmit/Rece.ive tCCY 400· - 400· - ns Clock Rate
T ransm it/Receive tCH 175 - 175 - ns Clock High Time
T ransm it/Receive tCL 175 - 175 - ns Clock Low Time
XTlI to Txo too - 500 - 500 ns Propagation Oelay
RTS Propagation t oLY - 500 - 500 ns Delay
IRO Propagation tiRO - 500 - 500 ns Delay (Clear)
hr' t f = 10 to 30 "s)
-The baud rate with external clocking is: Baud Rate = 16 T x CCY
PACKAGE OUTLINES
28 LEAD CERAMIC
t:::r:::J::::ll
XTLI (TRANSMIT CLOCK INPUT)
I -tCL - 1
too :L TXD ____ ---JX __ _
</>2
IRQ (CLEAR)
RxC (INPUT)
NOTE: TxD rate is 1/16 TxC rate
Transmit Timing with External Clock
_ -------..J
tIRQ
}---
Interrupt and Output Timing
1----------tcCy---------,
-tCL-
NOTE: RxD rate is 1/16 RxC rate
Receive External Clock Timing
28 LEAD PLASTIC
I 1.5501
~~Tr~~~~~~~~~~~ (.1601
11.4701 --1 (1401
I" ".... 11 :I:f: 1-~~~ '.'51 I-j U Itl.0651 _ I I ~T LI.7OOI---i (.0081
I -J (0451 --1 t- \ "\ (.6001 1.0851 1.0231 032 REF. (.:.!...!!!I (.1501 1.0601
(,0651 1.0151 1.0901 1.1251 1.0201
Intel 8048H/S048H-1 IS035H Ll8035H L-1 HMOS SINGLE COMPONENT 8-BIT MICROCOMPUTER
• S04SH/S048H-1 Mask Programmable ROM • S035HL/S035HL:-1 CPU Only with Power Down Mode
• a-BIT CP.U, ROM, RAM, I/O in Single • 1K x a ROM Package 64 x a RAM
• High Performance HMOS 27 I/O Lines
• Interval Timer/Event Counter
• Reduced Power Consumption • Easily Expandable Memory and I/O
• 1.4 usee and 1.9 usee Cycle Versions • Compatible with 8080/8085 Series All Instructions 1 or 2 Cycles. Peripherals
• Over 90 Instructions: 70% Single Byte • Two Single Level Interrupts
The Intel@) 8048H/8048H-,/8035HL/8035HL-' are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips using Intel's advanced N-channel silicon gate HMOS process.
The 8048H contains a 1 K X 8 program memory. a 64 X 8 RAM data memory. 27 I/O lines, and an 8-bit timer/counter in addition to on-board oscillator and clock circuits. For systems that require extra capability the 8048H can be expanded using standard memories and MCS-80T-/MCS-85 T
- peripherals. The 8035HL is the equivalent of the 8048H without program memory and can be used with external ROM AND RAM.
To reduce development problems to a minimum and provide maximum flexibility, a logically and functionally pin compatible version of the 8048H with UV-erasable user-programmable EPROM program memory is available. The 8748 will emulate the 8048H up to 6 MHz clock frequency with minor differences.
The 8048H is fully compatible with the 8048 when operated at 6 MHz.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have extensive bit handling capability as well as facilities for bOLh binary and BCD arithmetic. Efficient use of program memory results from an instruction set consisting mostly of single bit instructions and no instructions over 2 bytes in length.
PIN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM
TO Vec
ITAL 1 T1 PORT c 1
ITAL 2 P27 CLOCK 1024 WORDS 64 WORDS PROGRAM DATA
usn MEMORY MEMORY
fi P25 PORT
INT P24 = 2
EA P17
AD P16
;'SE" .. P15 I041H WA P14 I035HL
ALE P13 I04IH-1 I035HL-1
080 P12
08 , P11
082 P10
083 Voo
/\. 1 I • BIT
A
CPU ~ t V OB4 PAOG
085 P23
08. P22 BUS
I BIT 27 TIMER 1/0 LINES
EVENT COUNTER
OB7 P21
VSS P20
Inlel COlpOllhon anumes no lesponSlblllty fOl I"e use of Iny CirCUItry Ol"el Ihan ClrCUllry embodIed In an Inlet product No other CIrCUlI patent lIcenses arc Implied
intel S04SH/S04SH-1/8035H L/S035H L-1 ~rru~[LO[M]O~&~~
PIN DESCRIPTION
Designation Pin = Function Designation Pin = Function
VSS 20 Circuit GND potential testable with conditional
VOD 26 Low power standby pin jump instruction.
VCC 40 Main power supply; +5V (Active low)
AD during operation. 8 Output strobe activated during a BUS read. Can be
PAOG 25 Output strobe for 8243 I/O used to enable data onto the expander. bus from an external device.
P10-P17 27-34 8-bit quasi-bidirectional Used as a read strobe to Port 1 port. external data memory. P20-27 21-24 8-bit quasi-bidirectional (Active low) Port 2 port.
RESET 4 Input which is used to 35-38 P20-P23 contain the four high order program counter initialize the processor.
bits during an external pro- (Active low)
gram memory fetch and (Non TTL VI H)
serve as a 4-bit I/O expander WR 10 Output strobe during a bus bus for 8243. write. (Active low)
OB~DB7 12-19 True bidirectional port Used as write strobe to BUS whi.ch can be written or read externai data memory.
synchronously using the ALE 11 Address latch enable. This RD. WR strobes. The port signal occurs once during can also be statically each cycle and is useful as a latched. clock output. Contains the 8 low order The negative edge of ALE progr~m counter bits during strobes address into ex-an ex~ernal·program ternal data and program memory fetch, and receives memory. the addressed instruction
~ 9 Program store enable. This under the control of PSEN. Also contains the address output occurs only during a
and data during an external fetch to external program
RAM data store instruction, memory. (Active low)
under control of ALE, AD, SS 5 Single step input can be and WR. used in conjuhction with
TO Input pin testable using the ALE to "single step" the
conditional transfer in-processor through each
structions JTO and JNTO. TO instruction. (Active low)
can be designated as a clock EA 7 External access input which output using ENTO ClK forces all program memory instruction. fetches to reference external
T1 39 Input pin testable using the memory. Useful for emu la-
JT1, and JNT1 instructions. tion and debug, and
Can be designated the essential for testing and
timer/counter input using program verification.
the STRT CNT instruction. (Active high)
INT 6 Interrupt input. Initiates an XTAL1 2 One side of c"rystal input for
interrupt if interrupt is internal oscillator. Also
enabled. Interrupt is dis- input for external source.
abled after a reset. Also (Non TTL VIH)
XTAL2 3 Other side of crystal input.
intel 8048H/S048H-1 IS035H L-1 IS035H L-1 [?J rru [g ~ 0 fi1] 0 ~£OO'\1
INSTRUCT~ON SET
Accumulator Subroutine
Mnemonic De.crlpllon Bytu Cycl •• Mnemonic Description Bytes Cycle.
ADO A, R Add register to A 1 1 CALL addr Jump to subroulme 2 2 ADO A. @R Add data memory to A 1 , RETR Return
ADO A. "dala Add Immediate to A 2 2 RETR Return and res lore stalus
AOOC A. R Add register with carry , AOOC A. @R" Add data memory with carry 1 1
AOOC A. "data Add Immediate with carry 2 2 Flag.
ANl A. R And register 10 A , Mnemonic De.crlption Byl •• Cycle.
ANL A. @R And data memory to A , 1 CLR C Clear carry ANL A. "dala And Immediate to A 2 2 CPL C Complemenl carry ORL A. R Or register to A CLR Fa CLear flag 0 ORl A @R Or data memory to A 1 ,
CPL Fa Complement Ilag 0 ORL A. , dala Or Immediate to A 2 2 CLR Fl Clear lIag 1 XRL A. R ExclUSive or register to A 1 CPL FI Complement lIag , XRL A. @R ExclUSive or data memory to A 1 1
XRL. A. , data ExclUSive or Immediate 10 A 2 2 INC A Increment A Data Moves DEC A Decrement A
Mnemonic Description Byte. Cycles ClR A Clear A MOV A. R Move register to A 1 ,
CPl A Complement A MOV A. @R Move data memory to A 1 ,
OA A DeCimal adiusl A MOV A. "dala Move Immediate to A 2 2 SWAP A Swap nibbles 01 A MOV R. A Move A to register RL A ROlate A let! MOV@R. A Move A to data memory 1 1 RLC A ROlale A left through carry MOV R. "dala MOlle Immediate to register 2 2 RR A ROlate A FIght MOV @R. 'data Move Immediate to dala memory 2 2 RRC A Rotate A fIght through carry MOV A. PSW Move PSW to A MOV PSW. A MOlle A 10 PSW
Input/Output XCH A. R EXChange A and reglsler XCH A. @R Exchange A and dala memory
Mnemonic Description Byte. Cycle. XCHO A. @R Exchange nibble 01 A and IN A. P Input port 10 A 1 2 register OUTL P. A Output A to port 1 2 MOVX A @R Move external data memory to A 2 ANl p. " dala And Immediate 10 port 2 2 MOVX@R. A Move A to el(lernal data memory ORL p. "data Or Immediate to port 2 2 MOVP A. @A Move to A from current page 2 INS A. BUS Input BUS to A 1 2 MOVP3 A, @ Move to A from page '3 2 oun BUS. A Output A to BUS 1 2 ANl BUS. " data And Immediate to BUS 2 2 ORL BUS "data Or Immediate to BUS 2 2 Timer/Counter MOVO A.P Input expander port to A 2 MOVO P. A Output A to expander port 2 Mnemonic Description Byte. Cycle.
ANLD p. A And A to expander port 2 MOVA. T Read timer/counter
ORlD P. A Or A to expander port 2 MOV T. A Load timer/counter STRT T S'ejii iimei
STRT CNT Start counter Aegl.ters STOP TCNT Stop timer/counter
Cycl.s EN TCNT, Enable timer/counter Interrupt
Mnemonle De.crlptlon Bytes DIS TCNTl Disable timer/counter Interrupt
INC R Increment register 1 , INC@R Increment data memory DEC R Decrement register Conlrol
Mnemonic Descrlpllon Byles Cycles
Branch EN , Enable external Interrupt 1
DIS 1 Disable external interrupt Mnemonic Description Byle. Cycl •• SEL RBO Select register bank 0 JMP addr Jump unconditional 2 2 SEL RBI Select register bank 1 JMPP@A Jump indirect 1 2 SEL MBO Select memory bank 0 DJNZ R. addr Decrement register and skip 2 2 SEL MBI Select memory bank 1 JC addr Jump on carry = 1 2 2 ENT 0 CLK Enable clOCk output on TO JNC addr Jump on carry = 0 2 2 Jl addr Jump on A zero 2 2 JNZ addr Jump on A not zero 2 2 Mnemonic Description Bytes Cycles JTO addr Jump on TO = , 2 2 NOP No operallon 1 JNTO addr Jump on TO = 0 2 2 JTl addr Jump on T1 = 1 2 2
JNT 1 addr Jump on Tl = 0 2 2 JFO addr Jump on FO = 1 2 2 JFl addr Jump on Fl = , 2 2 JTF addr Jump on Ilmer lIag 2 2 JNI addr Jump on !NT = 0 2 2 JBb addr Jump on accumulator bll 2 2
S04SH/S04SH-1 /S035HL/S035H L-1
A.C. CHARACTERISTICS (PORT 2 TIMING) TA = ooe to 70°C, vee = SV± 10%. VSS = ov I I 8048H I 8048H-1 I
a035Hl 803SHl-1
Symbol Parameter 6 MHz 8 MHz 11 MHz Unit Min. Max. Min. Max. Min. Max.
tcp Port control Setup Before Falling 110 , lOS ns Edge of PROG. I
tpc Port Control Hold After Falling lOa 90 ns Edge of PAOG.
tpA PAOG to Time P2 Input Must Be Valid 810 700 650 ns
tpF Input Data Hold Time 0 1S0 0 150 0 lS0 ns
top Output Data Setup Time 250 210 200 ns
tpD Output Data Hold Time 65 35 20 ns
tpp PROG Pulse Width 1200 970 700 ns
tpL Port 2 1/0 Data Setup 3S0 I 300 2S0 ns
tLP Port 2 1/0 Data' Hold 150 65 20 ns
PORT 2 TIMING
ALE ~ \ V '\ ~'CAr-1 i I
EXPANDER IIPL_I~llP.1 ---lOp _-_lpD~ PORT I I
: ! i
i I OUTPUT PCH PORT 20 3 DATA PORT CONTROL OUTPUT DATA
EXPANDER PORT ,- IpR
I INPUT PCH PORT 20 3 DATA PORT CONTROL
! 'I ,-.. ___ Ipp __ _
PROG -----------------------;\1 V _I ______ --1,
BUS TIMING AS A FUNCTION OF TCY *
SYMBOL
TLL TAL TLA TCC (1) TCC (2) TOW TWO TOA
FUNCTION OF TCV
7/30 TCY MIN 1/10 TCY MIN 1/15 Tey MIN 1/2 Tey MIN 2/5 TCV MIN 2/15 TCY MIN 1115 TCY MIN 0 MIN
T CC (1) : ADIWR Tee (2) : PSEN
• APPROXIMATE VALUES NOT INCLUDING GATE DELAYS.
SYMBOL
TAD {1} TRD (2)
TAW TAD {1} TAD (2)
TAFC TCA
FUNCTION OF Tey
11/30 TCY MAX 3/10 TCY MAX 3/10 TCY MIN 112 TCY MAX 1/3 TCY MAX 1/30 TCY MIN 1115 TCY MIN
TAD (1): AD TRD (2) : PSEN
TAD (1): AD TAD (2) : PSEN
"FN-01491"-05
S048H/S04SH-1 /S035H L/S035 H L-1
WAVEFORMS
~--------- ICy----------_·1
ALE
PSEN
BUS FLOATING
IADDRESS 1
1-----
L
Instruction Fetch From External Program Memory
ALE J J L L -ICC -I leA l.. 1- ! I
--------------~1~ ____ ~F-----------~
BUS
Write to External Data Memory
ALE J "----__ J i-ICC --1 ICA I-
I
L RD -----------) ~---------
'AFC ~ f--- --I ~ lOR
i FLOATING i
BUS FLOATING ~ FLOATING
I ~IRD.: 1--- -IAO------:
Read From External Data Memory
2.4\1 ---- ~------......
O.45V ____ --JX~~;- TEST POINTS:~~X,-______ __
Input and Output for A.C.Tests,
A.C. CHARACTERISTICS TA = ooe to 700 e vee = voo = 5V ± 10%, VSS = OV
Symbol Parameter
tLL ALE Pulse Width
tAL Address Setup to ALE
tLA Address Hold from ALE
tcc Control Pulse Width (PSEN, RD, WR)
tDW Data Setup before WR
two Data Hold after WR
-tey Cycle Time
tOR Data Hold
tRD PSEN, RD to Data In
tAW Address Setup to WR
tAD Address Setup to Data In
tAFC Address Float to RD, PSEN
tCA Control Pulse to ALE
NOTE 1: Controloutputl BUS outputl
Cl = 80 pF Cl = 150 pF
8048H 8048H-1 8035HL 803SHL-1
6 MHz 8 MHz 11 MHz Conditions
Min. Max. Min. Max. Min. Max. Unit (Note 1)
400 270 150 ns
75 75 70 ns
65 65 50 ns
700 490 300 ns
370 370 280 ns
80 80 40 ns CL = 20pF (NOTE 2)
2.5 1.875 1.36 Jls
0 200 0 150 a 100 ns
500 340 200 ns
230 210 200 ns
950 650 400 ns
0 0 -1 ns
10 10 0 ns
NOTE 2: BUS High Impedance load: 20 pF
