Mobile Phone RF Front End Integration...

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Mobile Phone RF Front End Integration Roadmap March 17, 2015 James P Young

Transcript of Mobile Phone RF Front End Integration...

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Mobile Phone RF Front End

Integration Roadmap

March 17, 2015

James P Young

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Agenda

Market Dynamics

Smartphone Front End Block Diagram

Block By Block Performance Analysis (SOC vs. SIP) – RF Switch – PA – Analog and Mixed Signal – MIPI: Gate Level – ESD

Isolation Requirements

Top Level Tools and Simulation Requirements

Summary

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Market Dynamics

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28B Devices by 2020

Connect Everything

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32

320

3,200

32,000

1996 2000 2004 2008 2012 2016 2020

PC Smartphones loT

loT Emerging as the Next Big Mega-trend

Source: IDC, Ericsson, Goldman Sachs Global Investment Research

Y-axis is on a logarithmic scale

Inst

alle

d B

ase

(m

n)

200mn

100mn

1bn

6bn

2bn

6bn

28bn

Connected Devices Are Exploding

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1.5 EB

2.6 EB

4.4 EB

7.0 EB

10.8 EB

15.9 EB

0

2

4

6

8

10

12

14

16

2013 2014 2015 2016 2017 2018

Exabytes Per Month

61% CAGR 2013–2018

Source: Cisco VNI Mobile, 2014

Global Mobile Data is Exploding

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Increasing Front End Requirements

2012 2014 2016 2017 2016E 2020E

LTE Rel

# CA Bands

MIMO

CA Band Combos

LTE Rel-11 LTE Rel-X LTE Rel-12 5G

2 3 3 5

8x8 8x8 8x8 64X8

25 172 75+ 300

Peak/Max DL 1.2Gbps 6Gbps 3Gbps 18Gbps

Proposed New Bands 5+ 24 50

Increasing Front End Complexity

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Expanding Band Count

2 2 3 6

10 14

21 25 26

8

8

11 15

0

5

10

15

20

25

30

35

40

45

Rel 99,1999

Rel 4,2001

Rel 5,2002

Rel 6,2004

Rel 7,2007

Rel 8,2008

Rel 9,2009

Rel 10,2011

Rel 11,2012

4G

3G

(Ban

ds)

3GPP 3G and 4G Bands by Year/Release

More Data = More Bands

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Cellular Smartphone Front End Block Diagram

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Mobile Handset Front End Block Diagram

Smartphone

2, 3, and 4G

14 + Bands Typ. – LB 699 to 960 MHz – MB 1428 to

2170 MHz – HB 2300 to

2690 MHz

Assumes High Band Module is Separate, but Could be Integrated 2, 3, 4G

Module

LB GGE

MB GGE

B1

B4

B25

B3

B8

B20

B26

B12

PA Bias and Control

MIPI Interface Switch Bias

and Control

Load Line

Match

Load Line

Match

3

High Band

Ext. Bands

LB In

MB In

MB Out

HB Out

LB Out

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Mobile Handset FE Circuit Blocks

RF Switch

Switch Control

PA – 4 to 6 – Harmonic

terminations – Load line match

PA Control

MIPI RFFE – 26 to 52 MHz SPI 2, 3, 4G

Module

LB GGE

MB GGE

B1

B4

B25

B3

B8

B20

B26

SOI

B12

PA Bias and Control

MIPI Interface Switch Bias

and Control

Load Line

Match

Load Line

Match

3

High Band

Ext. Bands

LB In

MB In

MB Out

HB Out

LB Out

Everything in Blue Could Be in SOI, But Should It Be?

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RF Switch

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RF Switch Complexity in LTE World: Increasing Number of Bands

LB Arms MB Arms HB Arms Total Arms

Nu

mb

er

of

TRX

Po

rts

Total Switch Arms Required are Increasing

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Inter-band Carrier Aggregation Simultaneous Transmission of Multiple Bands

Low/Mid, Low/High, Mid/High, Low/Low, Mid/Mid Low/Mid/High

RF Switch is Partitioned by Band to Allow for Diplexing of Bands

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Front End Block Diagram

CA the Three Bands

LB

– 699 to 960 MHz

MB

– 1428 to 2170 MHz

HB

– 2300 to 2690 MHz

J. Young “Carrier Aggregation, Quantifying Front End Losses,” IWPC Chicago Meeting Sept. 16, 2014

2, 3, 4G Module

LB GGE

MB GGE

B1

B4

B25

B3

B8

B20

B26

B12

PA Bias and Control

MIPI Interface Switch Bias

and Control

Load Line

Match

Load Line

Match

3

High Band

Ext. Bands

LB In

MB In

MB Out

HB Out

LB Out

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Number of FETs in Stack – GSM Max. Pout and VSWR

• ≈53Vp

– 3/4G Max. Pout and VSWR • ≈25Vp

– Each FET Can Sustain? • Technology dependent

• Sub parasitics cause voltage imbalance

Antenna Switch/Tuner Design

Peak RF Voltage Determines the FET Stack

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Antenna Switch/Tuner Design

Having established the number of FETS in the stack

Minimize Coff to achieve specified off isolation – Use minimum L and scale W to specified Coff – Typically we will maintain around 30dB of isolation

This determines Ron which is the dominate factor in insertion loss – Wα Ron

Optimize Coff

This Sets Insertion Loss

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2012 2013 2014 2015 2016 2017 2018

SOI Ron*Coff Process Improvement Lowers Insertion Loss

An

ten

na

Swit

ch In

sert

ion

Lo

ss

SOI Provides The Best Performance and Lowest Cost Solution

MEMS

SOI

PHEMT

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SOI Substrate: RF 2nd Harmonic

Loss Decreases with Increasing Substrate Resistance – Typically use 1–10 kΩ/□

Adding a Trap-rich Layer Reduces Loss and Improves Linearity

p substrate

Buried Oxide (BOX) Metal Metal

Managing and Reducing Substrate Parasitics Reduces Harmonics and IMD

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RF Switch Summary

SOI Provides The Best Cost and Performance Solution

SOI CMOS pHEMT MEMS

Insertion Loss Acceptable High Acceptable Best

Linearity Acceptable Acceptable? Maybe Better

Best

Integration Best Best Need an External

CMOS Die

Requires MEMS on

CMOS

Cost Acceptable Best Higher Very Expensive

Today

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PA

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PA Loadline Design A Voltage Transformation

Converting the Battery Voltage to RF Output Power

Out V2

+

- In V1

+

-

Vcc = Vbatt = 3.5 V

Pout = +34.6 dBm 50 Ohm V2 = 33.6 Vp-p

7 Vp-p

V1 V2

N1 N2

N1/N2 = transformer turns ratio Pin = Pout (lossless transformer) =

P= V2

R

R= V2

P

Vrms= Vp-p/(2*√2) Vp-p= 2Vcc

R= Vcc2

2Pout

= transistor load line

Output Match Steps Up RF Voltage

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SOI Transistor PA Scaling

Stacking Devices

– Based on the device breakdown voltage

– Shorter gate length: more devices

Scale Width

– To support peak current

Vcc = Vbatt = 3.5 V

Voltage Current or Power

Output Array Size Does Not Scale with Gate Length

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PA Loadline Design

Zopt

P = V I R = V I

Zs’ Zo’ Short Open

C

L

PA Output Match

Zs ZL

RL= Vcc2

2Pout

= transistor load line Vcc = 3.5 V battery

Pout is saturated output power

Impedance Transformed with LPF

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$-

$0.01

$0.02

$0.03

$0.04

$0.05

$0.06

$0.07

$0.08

$0.09

10

100

1000

90 23 12 6.5 7.0 3.6 2.8

Ind

uct

or

Q

Metal Thickness (µm) vs. Inductor Q

Metal Thickness vs. Inductor Q 2 GHz and 2–3 nH

Al

Cu Al-Cu

Cu Cu Cu

Au

SOI PCB Metal Thickness (µm)

Co

st ($)

On Die SOI Match is Costly and Provides Low Performance Relative to PCB

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Output Match Network (OMN) Loss vs. Inductor Q

MCM Laminate

On Die Thick Copper

865 MHz, 3 Ohm Load Line Capacitor ESR = 0.05 Ohms

Q

Inse

rtio

n L

oss

(d

B)

Q of the Inductor Determines the Loss

IL vs. Inductor Q for Constant Q Match

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ηM2 G2 G1

ηC1 ηC2

ηM1

PIN POUT

PC1

PB2

PC2

Technology Drain or Col. Eff.

ηC2

Output Match Loss ηM2 (dB)

G2 Inter-stage

Loss ηM2 (dB)

Driver Eff. ηC1

PA PAE Point A

GaAs HBT 89% -0.65 14 -0.5 50% 71%

Measured HBT 66%

SOI 75% -0.65 14 -0.5 40% 60%

Measured CMOS Amalfi[4] 50%

Reported CMOS Nujira [5] 57% 14 -0.5 40% 54%

SOI Carrara, Presti, et al. [6] 72% -0.65 14 -0.5 40% 57%

CMOS 65nm [7] 70% -0.65 14 -0.5 40% 56%

Peregrine SOI PA [9] 72% -0.65 14 -0.5 40% 57%

SOI+on Die Match 75% -0.8 14 -0.5 40% 58% Max. Vcc, Peak Saturated Eff

SOI/CMOS vs. GaAs HBT PAE

J. Young “Mobile Handset PA Performance. ET vs. APT & GaAs HBT vs. SOI/CMOS”, 2014 International RF-SOI Workshop, Sept. 23, 2014, Shanghai, China; IWPC Chicago Meeting Sept. 16, 2014

SOI Device PA PAE Must Improve to Compete with GaAs HBT

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SOI/CMOS GaAs HBT

Pout Acceptable Acceptable

PAE OK? ≈10% Better

Linearity Challenging Best

OMN Loss Higher External – Low Loss

Integration Best Requires External CMOS Controller

Die Size 3–5X 1X

PA Solution Cost High Low

PA Summary

GaAs HBT Provides the Lowest Cost with the Highest Performance

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Mixed Signal

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Digital and Analog Sections PA Support

Analog / Mixed Signal Section RF Switch Example – Band gap – Voltage regulator – A/D – V to I – Temp. sensor – Power detector

MIPI – ≈ 5K gates – Needs a fine geometry to

minimize size (<0.18 u)

ESD Protection

MIPI RFFE

Vio

Data

Clock

Regulator

V/I

Logi

c &

Lev

el

Shif

ters

Ibias

+V

Temp Sense

A/D

ESD

Power Detector

PA

Protection

Many Analog and Mixed Signal Circuits Required Place in a Low Cost CMOS Process

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Digital and Analog Sections RF Switch Support

Analog / Mixed Signal Section RF Switch Example

– Oscillator

– Band gap

– Voltage regulator

– Negative voltage generator

MIPI RFFE

Vio

Data

Clock

Regulator

NVG

Logic & Level Shifters

Source Drain Bias

Gate Bias

-V +V

FET Stack – One/Switch

On the Die with the SOI Switch

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Filters

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B25 RX Band Pass Filter Analysis

Band 25

– Passband RX 1930–1995 MHz

– Rejection 1850–1915 MHz, >40 dB

Calculation – W1=1930, W2=1995, Wt=1915

– W’/W1’= (2/ω)((Wt -W0)/W0)=1.45

– Where ω=2(W2-W1)/(W2+W1)=3.3%

– And W0=(2*W2*W1)/(W2+W1)=1961.96

Filter

– 8 section 0.2 dB Tchebyscheff (0.5 dB Ripple 7 Section Filter)

• Tx rejection = 44 dB

B25 Rx

65 MHz

B25 Tx

1915 MHz

Ins Loss Tx Rejection

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Conclusion

Using a MEMS Capacitor and Inductor Tunable Filter – Unloaded combined Q of 100

SAW Filters Provide the Q Necessary for a Low Insertion Loss

0

5

10

15

20

25

50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050

PCB

MEMS

SAW= 1.3 dB

4 Section Tchebyscheff Filter

BST

Inse

rtio

n L

oss

(d

B)

Filter Unloaded Resonator Q

SAW or FBAR Filters are Required Today

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Isolation

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Clock Isolation

Clock / Oscillator Noise – Can be conducted or radiated

noise

– Intermodulated clock noise onto the RF signal must be <110 dBm within the Rx passband

MIPI RFFE

Vio

Data

Clock

Regulator

NVG

Logic & Level Shifters

Source Drain Bias

Gate Bias

-V +V

FET Stack – One/Switch

Osc

Freq.

Sig.

Tx Rx

Clock

Clock Must Not be Present in the RF Switch

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2, 3, 4G Module

LB GGE

MB GGE

B1

B4

B25

B3

B8

B20

B26

B12

PA Bias and Control

MIPI Interface Switch Bias

and Control

Load Line

Match

Load Line

Match

3

Ext. Bands

LB In

MB In

MB Out

HB Out

LB Out

Tx to Antenna Isolation

Duplexer Tx to Ant Typically has >55 dB of Isolation

SOI IC Should Have >65 dB of Isolation

Typically Only Accomplished with a Flipped Chip Package and Careful Design of Routing

This is Only One of Many RF Isolation Requirements in the Design

SOI

PCB

>65 dB

TX to Antenna Isolation Must be >65 dB to Avoid Desense

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2, 3, 4G Module

LB GGE

MB GGE

B1

B4

B25

B3

B8

B20

B26

B12

PA Bias and Control

MIPI Interface Switch Bias

and Control

Load Line

Match

Load Line

Match

3

Ext. Bands

LB In

MB In

MB Out

HB Out

LB Out

Tx to Antenna Isolation

PA B12 3Fo is B4 Rx Band

Need >120 dB of Isolation

SOI SOC?

Integrated Shielding in the Package

PA IC

PCB

RF Sw IC

PA to Antenna Isolation Must be >120 dB to Avoid Desense

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Design, Simulation and Test with High Integration

Interconnect Flip Chip On Substrate Integrated Shield Transmission Lines

Functions PA RF Switch Power Control and MIPI Analog/Mixed Signal Filters ESD Protection

Sim. and Des. Tools Harmonic Balance Transient 2D/3D EM RTL Compiler NCSIM (Digital Sim.)

SOI Process Ron*Coff Thick Metal Linear Substrate High Isolation

Layout DRC, LVS, Antenna Auto Router, Digital and Analog

Full Functional RF Test Automated Automated Data Analysis

2, 3, 4G Module

LB GGE

MB GGE

B1

B4

B25 B3

B8 B20 B26 B12

PA Bias and Control

MIPI Interface Switch Bias and

Control

Load Line Match

Load Line Match

3

High Band

Ext. Bands

LB In

MB In

MB Out

HB Out

LB Out

Extremely Difficult and Time Consuming to Design, Test, and Analyze

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Customer’s Expectation

1 • First Skyworks Engagement

2 • First Samples in ~6 Months

3 • Total Functional Maturity in First Sample

4 • Spec Compliant in 10 Months (or Less)

5 • Production Ramp in 12–14 Months (or Less)

Design Efficiency Must Be High: Design, Simulate, Fab, and Test SIP Provides the Fastest Time to Market

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SOI is Clearly a Big Part of the Growing Mobile Market

Shipped > 150M CMOS Cellular PAs

RF SOI, RF CMOS, and BiCMOS Skyworks Shipments

0

1

2

3

4

FY09 FY10 FY11 FY12 FY13 FY14 FY15

Un

its

(Bill

ion

s)

CMOS + SOI

BiCMOS

Shipped > 2B Silicon BiCMOS PAs (Wi-Fi)

Shipped > 6.5B RF SOI Devices

Experienced RF CMOS or SOI Leader

Long History of Development Activity

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Block Technology of Choice

Primary Reason

PA GaAs HBT PAE and Cost

PA OMN PCB Low Loss/ High Q

PA Controller CMOS Cost

RF Switch SOI Cost/Performance

Switch Controller CMOS/SOI Cost

MIPI RFFE CMOS Cost

Filters SAW/FBAR High Q

Summary – The Best Solution

SIP Wins Based on Cost, Performance and Time to Market

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References

[1] F. Raab, P. Asbeck, S. Cripps, P. Kenington, Z. Popovic, N. Pothecary, J. Sevic, N Sokal, “Power Amplifiers and Transmitters for RF and Microwave”, IEEE Transactions on Microwave Theory and Techniques, Vol. 50 No. 3, March 2002

[2] F. Raab, “Maximum Efficiency and Output of Class-F Power Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, Vol. 49, NO. 6, June 2001.

[3] J. Young, N. Cheng, “MULTIMODE MULTIBAND POWER AMPLIFIER OPTIMIZATION FOR MOBILE APPLICATIONS” IEEE VLSI_TSA CONFERENCE, APRIL 23 2013

[4] Hee-Soo Lee, Andy Howard, “RF Power Amplifier Design Series Part 4: RF Module Design using Amalfi CMOS PA” 2012 Agilent Technologies, Inc., Webcast

[5] “Envelope Tracking: Unlocking The Potential Of CMOS PAs In 4G Smart Phones” Nujira White Paper, Feb. 2013

[6] F.Carrara, C.D. Presti, G. Palmisano, A Scuderi “Power Transistor Design Guidelines and RF Load-Pull Characterization of a 0.13-um SOI CMOS Technology”

[7] S. Leuschner, et al. “A 31dBm, High Ruggedness Power Amplifier in 65nm Standard CMOS with High-Efficiency Stacked-Cascode Stages”, 2010 IEEE Radio Frequency Integrated Circuit Symposium, RTU1C-3

[8] J. Young, D. Ripley, P. Lehtola, “Envelope Tracking Power Amplifier Optimization for Mobile Applications”, 2013 IEEE S3S Conference

[9] N Comfoltey, D Kelly, D Nobbe, . Olson, “State-of-the-Art of RF Front-End Integration in SOI CMOS”, 2013 IEEE S3S Conference

[10] L. Formenti “ST H9SOI_FEM: 0.13 RFSOI Technology for Front End Module Monolithic Integration”, International RF SOI Workshop, Sept . 2014

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