MMIC Design Project (Small Signal Amplifier)
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Transcript of MMIC Design Project (Small Signal Amplifier)
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MMIC Design Project
Small Signal AmplifierThomas Neu
11/ 24/ 2005
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Abstract
This paper cove rs the design, results and c onc lusions of the M MIC fina l projec t. The go a l
for this p rojec t was to design a sma ll signa l am plifier (SSA) using a TriQuint MM IC proc ess.The SSA is part of a larger system d esigned to rec eive and transmit signa ls from 5.15 to
5.85GHz. Our Ga AS substrate was defined by the TriQuint MMIC p rocess and the design
was to fit on a 60 by 60 mil area.
The a mp lifier was designed using the Ad vanc ed Design System (ADS) softw a re from
Agilent w hich inc luded the TriQuint eleme nts lib ra ry and was laid out in a 60 by 60 mil
Anac hip. The a mp lifier is intende d to be used in the transmit as we ll as rec eive c hain a nd
will be used in a c onjunc tion w ith othe r p rojec ts designed in this c lass.
Spec ific a tion Goa l Ac tua l Result
Frequency:
Bandwidth:
Gain (small signal):
Gain Ripple:
Outp ut IP3:
VSWR, 50Ohm:
Supp ly Voltag e:
5.150 to 5.875 GHz
>800 MHz
>15 dB (16dB, goa l)
+/ - 0.5 dB
>20 dB
< 1.5:1 inp ut & o utp ut
+/ - 5V (+5 V go a l)
4.7 to 6.1 GHz
1.4 GHz
17.7 dB
+/ - 0.05 dB
~30 dB
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Introduction
Circuit Description
The sma ll signa l amp lifier is part of a larger system a s show n below and the refo re w as
designed to c ove r a very wide frequenc y rang e from 5.1 to 5.9GHz.
In order to c ove r this wide freq uenc y rang e w ith a ga in of at least 15dB, a t wo stage
topolog y wa s c hosen fo r this amp lifier design. The first sta ge w as designed for a g a inof ~11dB while sec ond ha s ~7dB with a feed back resistor to flatt en out the g a in. The
tw o c ascaded FET transisto rs a re b iased for c lass A o perat ion a nd both FETs are the
same size for design simp lic ity.
The two t ransisto rs a re c onfigured as self biased to ea se p ow er supp ly req uirem ents.
Both stage s d raw a bo ut 30mA ea c h from the supp ly which ove rall makes a fairly low
pow er design c onsidering a SSA g a in of 17.5dB.
Input and output matching networks are used to maximize the gain but also to get
the be st input and output ma tch.
~VCO
Tune
5150 - 5350 MHz
10 dBm
or 5725 -5875 MHz
Chip Set for the 5150 - 5350 MHz WLAN and
5725 - 5875 MHz ISM Bands
LNA SS Amp
5150 - 5350
5725 - 5875
MHz RF
15 dB 15 dB
PA-6 dBm
20 dBmSS Amp
13 dB 15 dB
I/Q
Mod0, 2, 4, 6 dB
Transmit Single Element
-2 dB
90, 180
-3 dB
5150 - 5350
5725 - 5875
MHz RF
LNA SS Amp
15 dB 15 dB 90, 180
-3 dB
Receive Array
1 of 4 Elements
4WAYCOMBINER
~
VCO
Tune
5150 - 5350 MHz
10 dBm
or 5725 - 5875 MHz
X
IQMIXX
Vector Mod
~
~
I/Q
DeMod
~VCO
Tune
5150 - 5350 MHz
10 dBm
or 5725 -5875 MHz
~VCO
Tune
5150 - 5350 MHz
10 dBm
or 5725 -5875 MHz
Chip Set for the 5150 - 5350 MHz WLAN and
5725 - 5875 MHz ISM Bands
LNA SS Amp
5150 - 5350
5725 - 5875
MHz RF
15 dB 15 dB
PA-6 dBm
20 dBmSS Amp
13 dB 15 dB
I/Q
Mod0, 2, 4, 6 dB
Transmit Single Element
-2 dB
90, 180
-3 dB
5150 - 5350
5725 - 5875
MHz RF
LNA SS Amp
15 dB 15 dB 90, 180
-3 dB
Receive Array
1 of 4 Elements
4WAYCOMBINER
~
VCO
Tune
5150 - 5350 MHz
10 dBm
or 5725 - 5875 MHz
~
VCO
Tune
5150 - 5350 MHz
10 dBm
or 5725 - 5875 MHz
X
IQMIXX
XX
IQMIXXX
Vector Mod
~~
~~
I/Q
DeMod
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1. Design Approach
1.1 Transistor selection:
The sma ll signa l am p lifier c onsists of tw o c ascaded transistor sta ges and both sta ge s
use a 300um DFET transistor. Initia lly only one sta ge w as conside red , how ever the ga inwas fairly narrow band. A feedback resistor flattens and widens the RF gain but also
a ttenua tes it signific antly.
Therefore a two stag e a pp roa c h was c hosen w here the first stage provides mo st o f
the gain while the second stage with feedback resistor turns the circuit into a wide
ba nd am plifier.
1.2 Biasing:
First the Idss (saturated drain source current) was determined at Vgs=0V using the FET
tracer tool and it ca me out to ab out 68mA a s show n in figure 4. For best linea r output
pow er, Ids should b e a bout 55-60% of Idss, so roug hly 36mA.Both t ransisto rs a re config ured as self bia sed transisto rs (resisto r a t FET sourc e c ontrols
d ra in current ) and for Ids of ~35mA, Vg s should b e ~ -0.35V as show n in the simulation
below . Bypa ss c apac itors a t the source resistors he lp c ont rolling t he g a in a little more.
1.3 Ma tching Networks:
For op timum g ain a nd VSWR, the input a nd outp ut of the SSA a re typ ica lly ma tc hedwith a c onjuga te c omp lex matc h to a 50 Ohm imp ed anc e. In this de sign, the input
was tuned with a shunt and series inductor while the output was matched with a
shunt c ap ac itor and a series induc tor.
Another critical element in this design is the connection between first and second
stage . A la rge c ap ac itor is used as a DC bloc k to sep arate the DC b ias of 1st and 2nd
stage and a series induc tor matc hes the output o f stage one to the input of stage 2.
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1.4 Design Tradeoffs - Optimizations:
Orig inally the SSA ga in (S21) showed a lot of ripp le (+/ - 1dB) in the band wid th o f
interest when using Ids= 36mA. Therefo re the ga in wa s lowered by increa sing the
source resisto rs as well as tun ing the fee dbac k resisto r va lue. As a result, S21 drop ped
abo ut 2dB but no w show s ab out +/ - 0.1dB ripple. Furthermore the drain c urrent wa s
reduced due to the higher source resistance to roughly 30mA which lowered theove ra ll po we r consump tion b y ~20%.
The two sc hem a tic snapshot s below show Ids of the first sta ge a round 29mA (Vgs~
-0.355V) and Ids= 30.4mA (Vg s~ -0.33V) for the sec ond sta ge. Also in the 2nd stage the
c urrent through the feed back resistor ra ises ga te vo ltag e to 1.19V.
Sec ond ly, afte r ad ding a ll the transmission line eleme nts, all the m at c hing eleme nts
(input, output a nd be twe en stage s) where tuned for minimum VSWR and ma ximum
gain fla tness (minimum ripp le).
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2. Simula tions:
The SSA performanc e w as simulate d and tuned using ADS from Ag ilent as we ll as
TriQuint transisto r and lumped elem ent mo dels.
An ove rview of the simulation results of t he final c ircuit is show n in figure 1.
S11 as well as S22 show a very broa d ma tc h w ith a VSWR bet ter tha n 1.375 from 5 to6GHz. The amp lifier ga in (S21) is ~17.7dB with a ripp le o f ~0.1dB ac ross a BW of 1GHz
and a maximum ripple of 0.5dB from ~3.7 to 6.8GHz (also shown in figure 2).
Furthe rmo re t he simulation p red icts uncond itiona l sta b ility from 3 to 8 G Hz.
Figure 1: Simulation o verview of S11, Mu1 & MuPrime , S22, S21, VSWR1&2 and S21.
Figure 2: Simula tion of S21 showing +/ -0.5dB ripp le
from 3.7 to 6.8GHz.
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Figure 3 illustrate s tha t the input a nd outp ut show a very good ma tc h (VSWR
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At 5.5GHz input , the 1dB co mp ression p oint is a round -2dBm input pow er, at 5.0GHz it
is a round -2.5dBm input pow er as show n be low.
The output IP3, me asured a t the 1dB co mp ression p oint, is about 29.7dB at 5.0GHz
and about 33.6dB a t 5.5GHz as show n in the simulation p lots below .
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3. Schematic
At first the schematic was created only with the lumped elements. After adding all
the connecting transmission line elements, the circuit had to be retuned to
c om pe nsa te for all the interc onnec ts.
Figure 5 shows the final schematic of the entire amplifier while figure 6 shows the
simplified sc hem at ic without the c onnec ting element s.
Figure 6: Simp lified sc hem a tic w ithout the interconnec ts.
tqped_res
R9
w=50 um
R=12.2 Ohm
tqped_phss
Q3
Ng=6
W=50 um
tqped_cap
C18
c=1.28 pF
tqped_res
R8
w=11 um
R=140 Ohm
tqped_mrind
L16
LVS_Ind="LVS_Value"
n=3
s=3 um
w=3 um
tqped_svia
V4
tqped_mrind
L17
LVS_Ind="LVS_Value"
n=9
s=15 um
w=15 um
tqped_svia
V9
tqped_cap
C14
c=20 pFTerm
Term1
Z=50 Ohm
Num=1
tqped_pad
P3
tqped_res
R10
w=12 um
R=434 Ohm
tqped_svia
V7
tqped_svia
V8
tqped_pad
P6
Term
Term2
Z=50 Ohm
Num=2tqped_capC15
c=20 pF
tqped_mrind
L18
LVS_Ind="LVS_Value"n=10
s=10 umw=10 um
tqped_cap
C13
c=10 pFL
L12
R=
L=1000000 nH
V_DC
SRC4
Vdc=5 V
tqped_pad
P5
tqped_mrind
L15
LVS_Ind="LVS_Value"n=13
s=6 um
w=5 um
tqped_cap
C12
c=0.26 pF
tqped_res
R11
w=50 um
R=50 Ohm
tqped_cap
C17
c=1.02 pF
tqped_res
R7
w=15 um
R=139 Ohm
tqped_mrind
L13
LVS_Ind="LVS_Value"
n=4
s=3 um
w=3 um
tqped_cap
C10
c=10 pF
tqped_mrind
L14
LVS_Ind="LVS_Value"
n=13
s=7 um
w=7 um
tqped_svia
V6
tqped_pad
P4LL3
R=L=1000000 nH
V_DC
SRC2
Vdc=5 V
tqped_cap
C11
c=10 pF
tqped_sviaV10
tqped_phss
Q2
Ng=6
W=50 um
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4. Layout
A p lot of t he layou t is shown below . The connec ting transmission lines on t he t hree
me ta l laye rs are show in red (Meta l0), green (Meta l1) and blue (Meta l2).
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5. Test Plan
Design verifica tion of the SSA req uires measuring s-param ete rs (S11, S21, S22) as well
as outp ut IP3 and DC pa ram ete rs (pow er consump tion).
5.1 Test Equipment:
The follow ing test equipm ent will be neede d to charac terize the SSA:
- Ag ilent 8510 network ana lyzer
- Ca sc ad e Mo d el 43 wa fer prob e sta tion with 2 RF prob es and 4 DC need le probe s
- Synthesized signa l genera to r up t o 10GHz
- Spec trum ana lyzer up to 10GHz
- Simp le DC po wer supp ly
5.2 Turn-On Procedure:
The SSA req uires two 5V sup p lies one fo r eac h transisto r but the SSA c an b epow ered by just one DC po we r supp ly. In orde r to p rotec t the MMIC SSA, the c urrent
limit on the pow er supp ly should be set to 1.5 time s the nom inal DC current w hich is
about 90mA ((30mA+29mA)x 1.5).
5.3 S-Parameter Mea surements:
After calibrating the network analyzer, connect the DC and RF probes to the MMIC
SSA a s shown with the lab els on layout. Afte r set ting the c urrent limits on the DC
pow er supp ly, S11, S21 and S22 ca n b e m ea sured w ith the VNA. The d ra in current s
c an b e me asured with a simple multimet er.
5.4 1dB Compression Point:
Since the freq uenc y spec trum of inte rest is so w ide (1GHz), the 1d B c om pression p oint
me asurement should be p erformed a t three freq uenc ies (5.0, 5.5 & 6.0GHz).
The signa l generator provides the input signa l at the d esired freq uenc y to the SSA
and the outp ut po we r level c an b e reco rde d w ith the spec trum analyzer. The initial
input p ow er level should b e relatively low , around -15dBm. The measured outp ut
pow er minus the p rovided input p ow er leve l should eq ua l the sma ll signa l ga in (S21).
By raising the input p ow er leve l and subt rac ting the g a in from the output po we r, the
1dB compression point can be determined. According to simulation the 1dB
c om pression should ~ +2dBm input pow er.
5.5 Output IP3 Measurements:
For the IP3 mea surem ent , two signa l generat ors a re the nec essary. The input tones
should be spac ed ~10MHz (e.g. f1= 5.50GHz and f2= 5.51GHz). This should ensure tha t
the amplitudes at the transistor input are identical since the attenuation should be
the same for suc h c lose freq uenc ies. The p ow er leve ls for bo th input tones should be
set to the same level as we ll.
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The first me asurem ent should be a t a very low input p ow er leve l, e.g . -15dBm. Using
the spectrum analyzer, the output tone level as well as third order output (2*f2-f1)
level need to b e reco rde d. The d elta b etwe en the third order prod ucts and the
fundame nta l tones is the third o rder inte rc ep t (TOI) value.
This measurement c an be repe ated two o r three more times (e.g. -15dBm, -10dBm, -
5dBm a nd 0dBm) a nd t he TOI values rec orde d . The TOI values c an plot ted aga inst
input p ow er and the intersec tion of TOI and Pout is the outp ut IP3 po int.
6 Summary and Conclusion
The sma ll signa l am plifier was designed and simulate d using ADS from Ag ilent w ith
TriQuint sem iconduc to r DFET transisto r and lump ed eleme nt m od els. The simula tion o f
the final schematic shows a gain of ~17.5dB with exceptionally good gain ripple (~
+/ - 0.1dB) and very good input a nd outp ut ma tc h (VSWR < 1.4).
The amp lifier itself p rom ises fairly low pow er consump tion w ith roug hly only 60mA from
a single +5V supp ly.