MIT6_012S09_lec06
Transcript of MIT6_012S09_lec06
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Lecture 6PN Junction and MOS Electrostatics(III)
Metal Oxide Semiconductor Structure
Outline1. Introduction to MOS structure 2. Electrostatics of MOS in thermalequilibrium3. Electrostatics of MOS with applied bias
Reading Assignment: Howe and Sodini, Chapter 3, Sections 3.7 3.8
6.012 Spring 2009 Lecture 6 1
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1. Introduction Metal Oxide Semiconductor structure
MOS at the heart of the electronics revolution: • Digital and analog functions – Metal Oxide Semiconductor Field Effect Transistor
(MOSFET) is key element of Complementary Metal Oxide Semiconductor (CMOS) circuit family
• Memory function – Dynamic Random Access Memory (DRAM) – Static Random Access Memory (SRAM) – Non Volatile Random Access Memory (NVRAM)
• Imaging – Charge Coupled Device (CCD) and CMOS cameras
• Displays – Active Matrix Liquid Crystal Displays (AMLCD)
6.012 Spring 2009 Lecture 6 2
Metal interconnect
to gate
Metal interconnect to bulk
0
x
Gate oxide
εox
= 3.9 εo
p-type
ε s = 11.7 ε
o
n+ polysilicon gate
Figure by MIT OpenCourseWare.
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2. MOS Electrostatics in equilibriumIdealized 1D structure:
• Metal: does not tolerate volume charge – ⇒ charge can only exist at its surface
• Oxide: insulator and does not have volume charge – ⇒ no free carriers, no dopants
• Semiconductor: can have volume charge –
⇒ Space
charge
region
(SCR)
In thermal equilibrium we assume Gate contact is shorted to Bulk contact. (i. e, VGB = 0V)
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For most metals on p Si, equilibrium achieved by electrons flowing from metal to semiconductor and holes from semiconductor to metal:
Remember: n o po=ni2
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Fewer holes near Si / SiO2 interface
⇒ ionized acceptors exposed (volume charge)
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Space Charge Density
• In semiconductor: space charge region close Si /SiO2 interface – can use depletion approximation
• In metal: sheet of charge at metal /SiO2 interface • Overall charge neutrality
x = −t ox ; σ σσ σ = QG − t ox < x < 0; ρ ρρ ρ o( x ) = 0 0 < x < x do ; ρ ρρ ρ o ( x ) = −qN a x > x do; ρ ρρ ρ o ( x ) = 0
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Electric Field Integrate Poisson’s equation
1 x 2 E o( x 2 ) − E o( x 1) = ∫ ρ ρρ ρ ( x ′) dx ′
ε εε ε x 1
At interface between oxide and semiconductor, there is a change in permittivity ⇒ change in electric field ε εε ε ox E ox = ε εε ε s E s
E ox = ε εε ε s ≈ 3 E ε εε ε s ox
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Start integrating from deep inside semiconductor:
x > x do; E o ( x ) = 0 0 < x < x do; E o( x ) − E o ( x do) = 1
ε εε ε s −qN a d ′ x x do
x ∫ = −
qN a
ε εε ε s x − x do( )
−t ox < x < 0; E o ( x ) = ε εε ε s ε εε ε ox E o( x = 0
+) = qN a x do
ε εε ε ox x < −t ox ; E ( x ) = 0
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Electrostatic Potential (with φφφφ = 0 @ no = po = ni)
φ φφ φ =kT q • ln no
ni φ φφ φ = −kT q • ln po
ni In QNRs, no and po are known ⇒ can determine φ
in p QNR: po = N a ⇒
in n+gate: no = Nd + ⇒
φ φφ φ p = − kT
q • ln N a ni
φ φφ φ g = φ φφ φ n +
Built in potential: φ φφ φ B = φ φφ φ g − φ φφ φ p = φ φφ φ
n + +kT q • ln N a
ni 6.012 Spring 2009 Lecture 6 8
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To obtain φφφφo(x), integrate Eo(x); start from deep inside semiconductor bulk:
φ φφ φ o ( x 2 ) − φ φφ φ o ( x 1) = − E o ( ′ x ) d ′ x
x 1
x 2 ∫
x > xdo; φ o ( x) = φ p
0 < x < xdo; φ o ( x) −φ o ( xdo ) = − −qN a ε s
′ x − xdo( )d ′ x xdo
x ∫
φ o ( x) = φ p +qN a 2ε s
x − xdo( )2
AT x = 0 φ o (0) = φ p +qN a 2ε s
xdo( )2
−t ox < x < 0; φ o ( x) = φ p +qN a xdo 2
2ε s +qN a xdo ε ox
− x( )
x < −t ox ; φ o ( x) = φ n +
Almost done ….
φ B = φ n + −φ p
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Still do not know xdo ⇒⇒⇒⇒ need one more equation Potential difference across structure has to add up to φB:
Solve quadratic
equation:
where C ox is the capacitance per unit area of oxide
φ φφ φ B =V B,o + V ox ,o = qN a x do 2 2ε εε ε s +
qN a x dot ox ε εε ε ox
x do = ε εε ε s ε εε ε ox t ox 1 + 2ε εε ε
ox 2 φ φφ φ B
qε εε ε s N at ox 2 − 1
=ε εε ε s C ox 1+
2C ox 2 φ φφ φ B
qε εε ε s N a −1
Now problem is completely solved!
C ox =ε εε ε ox t ox
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There are also contact potentials ⇒⇒⇒⇒ total potential difference from contact to contact is zero!
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3. MOS with applied bias VGB Apply voltage to gate with respect to semiconductor:
Electrostatics of MOS structure affected ⇒ potential difference across entire structure now ≠ 0
How is potential difference accommodated?
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Potential difference shows up across oxide and SCR in semiconductor
Oxide is an insulator ⇒ no current anywhere in structureIn SCR, quasi equilibrium situation prevails ⇒ New balance between drift and diffusion
• Electrostatics qualitatively identical to thermal equilibrium (but amount of charge redistribution is different )
2• np = ni
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Apply VGB>0: potential difference across structure increases ⇒ need larger charge dipole ⇒ SCR expands into semiconductor substrate:
Simple way to remember:with VGB>0, gate attracts electrons and repels holes.
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Qualitatively, physics unaffected by application of VGB >0.
Use
mathematical
formulation
in
thermal
equilibrium, but:
φ φφ φ → φ φφ φ + V GBFor
example,
to
determine
xd(VBG):
φ φφ φ B +V GB = V B (V GB ) +V ox (V GB)
2qN a x d (V GB ) qN a x d (V GB)t ox = +2ε εε ε
s ε εε ε
ox
2C ox 2 (φ φφ φ B + V GB) ε εε ε s
x d (V GB ) = 1+ε εε ε sqN a − 1
C ox
2 φ φφ φ (0 ) = φ φφ φ s = φ φφ φ p + qN a x d (V GB)
2ε εε ε s
6.012 Spring 2009 Lecture 6 15
φs gives n & p concentration at the surface
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What did
we
learn
today?
Summary of Key Concepts
• Charge redistribution in MOS structure in thermal equilibrium – SCR in semiconductor – ⇒⇒⇒⇒ built in potential across MOS structure.
• In most cases, we can use depletion approximation in semiconductor SCR
• Application of voltage modulates depletion region width in semiconductor – No current flows
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6.012 Microelectronic Devices and Circuits
Spring 2009
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