Minimization of Delay InLogic Circuits

7/31/2019 Minimization of Delay InLogic Circuits

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E C E N 6 2 6 3 D i g i t a l V L S I D e s i g n

Minimizing Delay in Complex Logic Circuits September 21, 2010 page 1 of 14

Minimizing Delay in Complex Logic

Circuits

Minimizing Path Delay. We would like to choose transistor widths to minimize delay,but what delay should be minimized? In our examples, there are 2 delays for the inverter,

4 for the NAND and 10 for the OR-NAND. The delay specifications for most logic

designs are that a certain block of logic should have a worst case delay less than some

maximum allowed delay. This is NOT the same as specifying a worst case delay for each

logic gate. Recall that minimizing the inverter pair delay gave different optimum widths

than minimizing the worst case single inverter delay.

Instead we should minimize the worst case delay on all paths through the entire logic

block. Finding the worst case delay paths is a very difficult problem for large circuits.

Consider a combinational logic circuit withNinputs. We will restrict ourselves to chang-

ing one of the inputs at a time while leaving the otherN- 1 inputs unchanged. There canbe a rising or falling edge on each input. If there is at least one path from each input to at

least one output, then the number of delays,Ndelays, must be greater than 2N. However,

there can be different paths depending on the values of the otherN- 1 inputs. This

increases the number of possible paths by a factor of 2N-1.

2N Ndelays 2N2N 1< < N2N=

Recall our 3-input OAI gate. There were 3x23 = 24 possible paths which we considered

previously. Many of these potential paths were uninteresting in that no change in the out-put occurred, but we had to consider all possible paths to be sure that we had not missed

one that could turn out to be the worst case delay path.

In general, it is an NP-complete problem to find the worst case delay paths. It is practi-

cally impossible to consider all the paths whenNis large. Instead, the designer uses his

intuition to pick the most likely candidates for the worst case delay paths. A possible

design procedure is as follows.

1. Choose initial transistor widths near the minimum allowed.

2. Simulate (up toN2Ntimes) to find the worst case delay. If the worst case delay meets

the design spec, stop.

3. Choose new transistor widths (usually wider) to reduce the delay along the worst case

delay path(s). Go back to step 2.

A typical delay path looks similar to fig. 4.29, p. 163.

If there are several logic gates along the path, it may take a large number of iterations of

the design loop to meet the specs. We need some way to speed up the design process. We


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can use our approximate delay equations to estimate the worst case delays which should

be much faster than using a simulation like SPICE in step 2. Furthermore, instead of just

guessing new transistor widths in step 3, we can use our delay formulas to pick new

widths in a manner which should converge to the optimal minimum delay solution.

There are two delays associated with each path through the circuit. Just as for the single

logic gates, we can start with a rising edge or a falling edge. At the next logic gate output,

the rising input produces a falling output and a falling input produces a rising output. To

be consistent with the single gate delay definitions, let as define a falling path delay to

mean the edge that produces a falling output, and the rising path delay produces a rising

output. For a path withNlogic gates in it,

tdfPATH tdr N 1( ) tdf N( )+ +=

tdrPATH tdf N 1( ) tdr N( )+ +=

For example, the path in fig. 4.29 with 4 logic gates in it,

tdfPATH tdr1 tdf2 tdr3 tdf4+ + +=

tdrPATH tdf1 tdr2 tdf3 tdr4+ + +=

Both of these path delays must meet the delay specification for the logic block. This is

different than requiring the rise/fall delays to be the same for each logic gate. Further-

more, delays on other paths must also meet the delay spec. This usually results in all the

longest path delays being the same as the specified maximum delay.

Since the path delays are nonlinear functions of the transistor widths, there is usually no

closed form solution for the optimum transistor widths. However, this problem can be

solved numerically with nonlinear optimization techniques. We will study a few simple

cases where additional simplifying assumptions yield a closed form solution. This will

allow us to gain insight into choosing near optimal transistor widths.

Multi-Stage Buffer Example. Suppose we want to design a multi-stage buffer out of a

chain of inverters.

inv 1 inv 2 ... invN

Cload(out)

...

Cload(in)

The input inverter has an input capacitance ofCload(in) and the output inverter must drive

the load capacitance, Cload(out). An inverter chain is often used to buffer a large capaci-

tance, Cload(out), while making it look like a much smaller capacitance, Cload(in).


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With only a single input and single output, there is only one path with two delays corre-

sponding to a rising or falling output. The contributions to the path delays from each logic

gate i aretdf i( ) tdPf i( ) Routf i( )Cload i( )+=

tdr i( ) tdPr i( ) Routr i( )Cload i( )+=

From our previous work, we know the parasitic rise-fall delay and output resistance for

the i-th inverter.

tdf i( )1

2--- 1 K+( )

Wn i( ) Wp i( )+

Wn i( )-------------------------------

2K

Wmin

Wn i( )------------+ t

Wmin

Wn i( )------------RCload i( )+=

tdr i( ) 1 K+( )Wn i( ) Wp i( )+

Wp i( )-------------------------------

2K

Wmin

Wp i( )------------+ t 2

Wmin

Wp i( )------------RCload i( )+=

Let us assume that the wires connecting the logic gates are short enough that the wire

resistance can be neglected, but long enough that the wire capacitance cannot be

neglected. Then each inverter except for the last inverter is loaded by the wire capacitanceand the input capacitance of the next inverter.

Cload i( ) Cwire i( ) Cin i 1+( )+=

From our previous work, we know input capacitance for the (i+1)-th inverter.

Cin i 1+( )Wn i 1+( ) Wp i 1+( )+

Wmin---------------------------------------------C=

so that

tdf i( )1

2--- 1 K+( )

Wn i( ) Wp i( )+

Wn i( )-------------------------------

2K

Wmin

Wn i( )------------+ t=

Wmin

Wn i( )------------R Cwire i( )

Wn i 1+( ) Wp i 1+( )+Wmin

---------------------------------------------C++

1

2--- 1 K+( )

Wn i( ) Wp i( )+

Wn i( )-------------------------------

t=

1

Wn i( )------------

Cwire i( )

C------------------ K+

Wmin Wn i 1+( ) Wp i 1+( )+ + t+

tdr i( ) 1 K+( )Wn i( ) Wp i( )+

Wp i( )-------------------------------

2K

Wmin

Wp i( )------------+ t=

2Wmin

Wp i( )------------R Cwire i( )

Cin

W--------

Wn i 1+( ) Wp i 1+( )+( )++

1 K+( )Wn i( ) Wp i( )+

Wp i( )-------------------------------

t=

2

Wp i( )------------

Cwire i( )

C------------------ K+

Wmin Wn i 1+( ) Wp i 1+( )+ + t+


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The last inverter is loaded by Cload(out) instead of an inverter input capacitance.

Cload N( ) Cwire N( ) Cload out( )+=

so that

tdf N( )1

2--- 1 K+( )

Wn N( ) Wp N( )+

Wn N( )

----------------------------------- t=

1

Wn N( )--------------

Cwire N( ) Cload out( )+

C------------------------------------------------- K+

Wmint+

tdr N( ) 1 K+( )Wn N( ) Wp N( )+

Wp N( )-----------------------------------

t=

2

Wp N( )--------------

Cwire N( ) Cload out( )+

C------------------------------------------------- K+

Wmint+

The path delays are

tdfPATH tdr i( )i odd{ } tdf i( )

i even{ }+=

tdrPATH tdf i( )i odd{ } tdr i( )

i even{ }+=

forNeven and the opposite forNodd.

The results are more clear if we transform variables to find the optimum Wi andZi where

Wi Wn i( ) Wp i( )+=

Zi Wp i( ) Wn i( )=

so that

Wn i( )Wi

Zi 1+--------------=

Wp i( )ZiWi

Zi 1+--------------=

tdf i( ) Zi 1+( )1

2--- 1 K+( ) 2

Cwire i( )

C------------------ K+

Wmin Wi 1++

Wi------------------------------------------------------------------+ t=

tdr i( )Zi 1+( )

Zi------------------- 1 K+( ) 2

Cwire i( )

C------------------ K+

Wmin Wi 1++

Wi------------------------------------------------------------------+ t=

2

Zi----tdf i( )=


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tdf N( ) ZN 1+( )1

2--- 1 K+( ) 2

Cwire i( ) Cload out( )+

C----------------------------------------------- K+

Wmin

Wi---------------------------------------------------------------------------+ t=



tdr N( )ZN 1+( )

ZN-------------------- 1 K+( ) 2

Cwire i( ) Cload out( )+C

----------------------------------------------- K+ Wmin

Wi---------------------------------------------------------------------------+ t=

2

ZN------ tdf N( )=

We want to minimize the path delays with the constraint that the rise/fall path delays are

the same. The method of Lagrange multipliers can be used for this constrained minimiza-

tion. The optimal transistor sizes can be found by differentiating the weighted path delays

with respect to the transistor sizes.

Wid

dm t dfPATH 1 m( ) t drPATH+[ ] 0=

Zid


md


The last equation insures that the rise/fall path delays are equal.

The weighted sum of the path delays is

m t dfPATH 1 m( ) t drPATH+ mtdf i( ) 1 m( )tdr i( )+( )i even{ }=

1 m( )tdf i( ) mtdr i( )+( )i odd{ }+

m 1 m( )2

Zi----+

tdf i( )i even{ }=

1 m( ) m 2Zi----+ tdf i( )

i odd{ }+


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The optimum Wi is found fromi even :

0Wid

dm t dfPATH 1 m( ) t drPATH+[ ]=

1 m( ) m2

Zi 1-----------+ Zi 1 1+( )

tWi 1-------------=

m 1 m( )2

Zi----+

Zi 1+( )

Cwire i( )

C------------------ K+

Wmin Wi 1++

Wi2

------------------------------------------------------------------t

Wi

Wi 1-------------

m 1 m( )2

Zi----+

Zi 1+( )

1 m( ) m2

Zi 1-----------+

Zi 1 1+( )------------------------------------------------------------------------

Cwire i( )

C------------------ K+

Wmin Wi 1++

Wi------------------------------------------------------------------=

0Zidd mtdfPATH 1 m( )tdrPATH+[ ]=

m [ ] t 1 m( )2

Zi2

----- [ ] t=

Zi 21 m

m------------- Zeven=

i odd : just interchange m and 1-m.

Wi

Wi 1-------------

1 m( ) m2

Zi----+

Zi 1+( )

m 1 m( )2

Zi 1-----------+

Zi 1 1+( )------------------------------------------------------------------------

Cwire i( )

C------------------ K+

Wmin Wi 1++

Wi------------------------------------------------------------------=

Zi 2m

1 m------------- Zodd 2 Zeven= =

The results look less complicated if we write

Wi

Wi 1-------------

r

Cwire i( )

C------------------ K+

Wmin Wi 1++

Wi------------------------------------------------------------------ i even,

1

r---

Cwire i( )

C------------------ K+

Wmin Wi 1++

Wi------------------------------------------------------------------ i odd,

=


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where

r

m 1 m( )2

Zeven------------+

Zeven 1+( )

1 m( ) m2

Zodd----------+

Zodd 1+( )-------------------------------------------------------------------------

Recall that the output inverter must drive a load capacitance, Cload(out).

WN

WN 1-------------- r

Cwire i( ) Cload out( )+

C----------------------------------------------- K+

WminW1

------------=

Also recall that the input inverter input capacitance must be Cload(in).

W1

Wmin------------C Cload in( )=

W1

Wmin

------------Cload in( )

C

--------------------=

Although there is no simple general solution, a closed form solution for the transistor

widths in the multi-stage buffer is possible if the following assumption is made.Cwire i( )

C------------------ K+

Wmin Wi 1+

This is a good assumptions for large load transistors and short wires, but may not be very

accurate for transistors near minimum size. Now the size ratios are all the same except for

the factorr.

Wi

Wi 1-------------

r

Wi 1+

Wi------------- i even,

1

r---

Wi 1+

Wi------------- i odd,

=


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WN

WN 1-------------- r

Cload out( )

C----------------------

Wmin

WN------------=

WN 1

WN 2--------------

1

r---

WN

WN 1--------------

Cload out( )

C----------------------

Wmin

WN------------= =

WN 2

WN 3-------------- r

WN 1

WN 2-------------- r

Cload out( )

C----------------------

Wmin

WN------------= =

W2

W1-------

rCload out( )

C----------------------

Wmin

WN------------ Neven,

Cload out( )

C----------------------

Wmin

WN------------ Nodd,

=



Let us define the size ratio as S.

SCload out( )

C----------------------

Wmin

WN------------

Then,

WN1

S---

Cload out( )

C---------------------- Wmin=

WN 11

rS-----WN

1

rS2

--------Cload out( )

C---------------------- Wmin= =

WN 21

S---WN 1

1

rS2

--------WN1

rS3

--------Cload out( )

C----------------------Wmin= = =

WN 31

rS-----WN 2

1

r2S

3----------WN

1

r2S

4----------

Cload out( )

C---------------------- Wmin= = =

W1

1

rS-----W2

1

rN 2

SN 1

------------------------WN1

rN 2

SN

-----------------Cload out( )

C---------------------- Wmin= = Neven,

1S---W2

1

rN 1( ) 2

SN 1

----------------------------------WN1

rN 1( ) 2

SN

---------------------------Cload out( )C

----------------------Wmin= = Nodd,

=

W1 is the size of the input transistor which must have the desired input capacitance,

Cload(in).


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W1Cload in( )

C-------------------- Wmin

1

rN 2

SN

-----------------Cload out( )

C---------------------- Wmin Neven,

1

rN 1( ) 2

SN

---------------------------Cload out( )

C---------------------- Wmin Nodd,

= =



SN

1

rN 2----------

Cload out( )

Cload in( )---------------------- Neven,

1

rN 1( ) 2

---------------------Cload out( )

Cload in( )---------------------- Nodd,

=

S

1

r1 2

----------Cload out( )

Cload in( )----------------------

1 NNeven,

1

r1 1 N( ) 2--------------------------

Cload out( )

Cload in( )----------------------

1 N

Nodd,

=

A value forrcan be found by requiring the two path delays to be equal.

tdfPATH tdrPATH=

tdr i( )i odd{ } tdf i( )

i even{ }+ tdf i( )

i odd{ } tdr i( )

i even{ }+=

tdf i( ) tdr i( )( )i odd{ }

tdf i( ) tdr i( )( )i even{ }

=

12

Zi----

tdf i( )i odd{ } 1

2

Zi----

tdf i( )i even{ }=

2 Zi

Zi-------------

Zi 1+( )

1

2--- 1 K+( )

Wi 1+

Wi-------------+ t

i odd{ }

2 Zi

Zi-------------

Zi 1+( )

1

2--- 1 K+( )

Wi 1+

Wi-------------+ t

i even{ }=

Neven:2 Zodd

Zodd-------------------

Zodd 1+( )

1

2--- 1 K+( ) rS+ t

i odd{ }

2 Zeven

Zeven---------------------

Zeven 1+( )

1

2--- 1 K+( ) S+ t

i even{ }=


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N

2----

2 Zodd

Zodd-------------------

Zodd 1+( )

1

2--- 1 K+( ) r1 2

Cload out( )

Cload in( )----------------------

1 N+ t

N

2----

2 Zeven

Zeven---------------------

Zeven 1+( )

1

2--- 1 K+( )

1

r1 2

----------Cload out( )

Cload in( )----------------------

1 N+ t=



2 Zodd

Zodd-------------------

Zodd 1+( )

1

2--- 1 K+( ) r1 2

Cload out( )

Cload in( )----------------------

1 N+

2 Zeven

Zeven---------------------

Zeven 1+( )

1

2--- 1 K+( )

1

r1 2

----------Cload out( )

Cload in( )----------------------

1 N+=

This is worse than it looks becauseZeven andZodd also depend on r. There is a simple

solution whenNis even because theN/2 terms cancel.

m1

2---=

Zodd Zeven 2= =

r 1=

SCload out( )

Cload in( )----------------------

1 N=

Nodd:2 Zodd

Zodd-------------------

Zodd 1+( )

1

2--- 1 K+( ) S+ t

i odd{ }

2 Zeven

Zeven---------------------

Zeven 1+( )

1

2--- 1 K+( ) rS+ t

i even{ }=

N 1+

2-------------

2 Zodd

Zodd-------------------

Zodd 1+( )

1

2--- 1 K+( )

1

r1 1 N( ) 2

--------------------------Cload out( )

Cload in( )----------------------

1 N+ t

N 1

2-------------

2 Zeven

Zeven---------------------

Zeven 1+( )

1

2--- 1 K+( ) r

1 1 N+( ) 2 Cload out( )

Cload in( )----------------------

1 N+ t=

N 1+2-------------2 Z

odd

Zodd------------------- Zodd 1+( ) 12--- 1 K+( ) 1r1 1 N( ) 2

--------------------------C

load out( )Cload in( )----------------------

1 N

+

N 1

2-------------

2 Zeven

Zeven---------------------

Zeven 1+( )

1

2--- 1 K+( ) r

1 1 N+( ) 2 Cload out( )

Cload in( )----------------------

1 N+=


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There is no simple solution whenNis odd except whenN= 1.

12 Zodd

Zodd-------------------

Zodd 1+( ) [ ] 0

2 Zeven

Zeven---------------------

Zeven 1+( ) [ ]=

Z Zodd 2= =

Other odd values ofNcan be solved using numerical techniques.

Optimum Sand N. Instead of a fixed number of inverters in the buffer, it is interesting to

consider varying the number of inverters,N, to find the number of inverters that gives the

minimum delay for fixed loads, Cload(in) and Cload(out). For evenN,

SN Cload out( )

Cload in( )----------------------=

Nln S( )Cload out( )

Cload in( )----------------------ln=

N

lnC

load out( )Cload in( )----------------------

ln S( )---------------------------------=

and the minimum delay is

tdfPATH tdrPATHN

2----

2 2

2----------------

2 1+( )

1

2--- 1 K+( ) S+ t= =

lnCload out( )

Cload in( )----------------------

ln S( )---------------------------------

2 2

2 2----------------

2 1+( )

1

2--- 1 K+( ) S+ t=

Note that the delay is proportional to the log of the load capacitance ratio if we chooseN

correctly. We can now find the optimum size ratio, S, from

S

tdPATH0=

lnCload out( )

Cload in( )----------------------

ln2

S( )---------------------------------

1

S---

2 2

2 2----------------

2 1+( )

1

2--- 1 K+( ) S+ t

ln

Cload out( )

Cload in( )----------------------

ln S( )---------------------------------

2 2

2 2----------------

2 1+( ) t+ 0=

1

ln S( )-----------

1

S---

1

2--- 1 K+( ) S+ 1+ 0=

ln S( )1 K+

2S------------- 1+=

This last transcendental equation can be solved numerically to find the optimum S= 3.18


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forK= 0 and S = 3.59 forK= 1. Any size ratio in the range 3 < S< 4 should give near

optimal (minimum) delay.

Output Pad Driver Example. Suppose we want to design an output pad driver for the

TSMC 0.18m process. Bonding pads typically have a capacitance of a few pF. Let usdesign for 2 pF. A multistage buffer is needed where the first inverter should be near min-

imum size. Let us assume that our minimum size inverter has Wn = 4 and Wp = 5. The

optimumZ Wp Wn 2= = would require Wp to be between 5 and 6. So, we choose

5 to save area and power.

Cload in( )4 5+

Wmin------------------- C=

In this process, C= 0.9fF, and Wmin = 4 so that Cload in( ) 2.25C 2.03fF= = . Recall

that

N

lnCload out( )

Cload in( )

----------------------

ln S( )---------------------------------=

and the optimum stage ratio, S, should be 3.59 sinceK= 1 for this process. The number of

stages should be

N

ln2pf

2.03fF----------------

ln 3.59( )-------------------------- 5.40= =

and we chooseN= 5 to again save area and power. This slightly smallerNrequires a

slightly largerS.

SN Cload out( )

Cload in( )----------------------=

SCload out( )

Cload in( )----------------------

1 N=

2pf

2.03fF----------------

1 5=

3.97=

Even though the number of stages is odd, we will stick with Z 2= which should give

near optimal delay.


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Our design is

inv 1 inv 2 inv 3 inv 4 inv 5

2.03fF 2000fF

where the first inverter size was already chosen to beWn1 4= Wp1 5=

and the rest can be found by scaling each stage by 3.97.

W2 S W1 3.97 9 35.7= = =

Wn2W2

Z 1+------------

35.72.41

-------------- 15= = =

Wp2 Z W n2 1.41 15 21= = =

W3 S W2 3.97 35.7 141.7= = =

Wn3W3

Z 1+------------

141.72.41

----------------- 59= = =

Wp3 Z W n3 1.41 59 83= = =

W4 S W3 3.97 141.7 562.5= = =

Wn4

W4

Z 1+------------

562.52.41----------------- 233= = =

Wp4 Z W n4 1.41 233 329= = =

W5 S W4 3.97 562.5 2233= = =

Wn5W5

Z 1+------------

22332.41

--------------- 925= = =

Wp5 Z W n5 1.41 925 1308= = =

As a check, the output capacitance should be

Cload out( )SW5

Wmin------------C

3.97 22334

------------------------------ 0.9fF 1994.6fF= = =

which is close enough to the desired 2 pF.


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The estimated delay istdfPATH tdr i( )

i even{ } tdf i( )

i odd{ }+ 2tdr 3tdf+= =

tdrPATH tdf i( ) tdr i( )+ 3tdr 2tdf+= =

wheretdf Z 1+( )

1

2--- 1 K+( ) 2S+[ ] t=

tdr2

Z---tdf=

using t 9.5psec= for the TSMC 0.18m process gives

tdf 2.411

2--- 2 2 3.97+[ ] t 12t 114psec= = =

tdr2

1.41----------tdf 17t 161psec= = =

tdfPATH 2 161psec 3 114psec+ 664psec= =

tdrPATH 3 161psec 2 114psec+ 711psec= =

This design has several very large transistors. Remember that transitors with widths larger

than about 30 must be folded and surounded with guard rings. The bonding pads areabout 100m on a side which correponds to 1111. Thus, the largest transistors withguard rings will take up about as much area as the bonding pad. Real pad drivers are usu-

ally designed with largerSand smallerNto save area and power. Note that the biggest

savings in area and power are achieved by making the biggest transistors smaller. Thus, a

largerS, perhaps as big as 10, might be used in the last stage only, with smallerSfor the

other stages. We will discuss trading off delay to save area and power in more detail later

on in the course.

Minimization of Delay InLogic Circuits

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