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MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar

memory arrays

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2014 Semicond. Sci. Technol. 29 104005

(http://iopscience.iop.org/0268-1242/29/10/104005)

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Invited Review

MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatilecrossbar memory arrays

Rohit S Shenoy1, Geoffrey W Burr1, Kumar Virwani1, Bryan Jackson1,Alvaro Padilla1, Pritish Narayanan1, Charles T Rettner1, Robert M Shelby1,Donald S Bethune1, Karthik V Raman2, Matthew BrightSky3, Eric Joseph3,Philip M Rice1, Teya Topuria1, Andrew J Kellock1, Bülent Kurdi1 andKailash Gopalakrishnan3

1 IBM Research—Almaden, 650 Harry Road, San Jose, CA 95120, USA2 IBM India Research Labs, Bangalore 560045, KA, India3 IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, USA

E-mail: gwburr@us.ibm.com

Received 27 February 2014, revised 11 April 2014Accepted for publication 27 May 2014Published 18 September 2014

AbstractSeveral attractive applications call for the organization of memristive devices (or other resistivenon-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVMdevices frequently possess some degree of inherent nonlinearity (typically 3–30× contrast), theoperation of large (> 1000×1000 device) arrays at low power tends to require quite large (> 1e7)ON-to-OFF ratios (between the currents passed at high and at low voltages). One path to suchlarge nonlinearities is the inclusion of a distinct access device (AD) together with each of thestate-bearing resistive-NVM elements. While such an AD need not store data, its list ofrequirements is almost as challenging as the specifications demanded of the memory device.Several candidate ADs have been proposed, but obtaining high performance without requiringsingle-crystal silicon and/or the high processing temperatures of the front-end-of-the-line—which would eliminate any opportunity for 3D stacking—has been difficult.We review our work at IBM Research—Almaden on high-performance ADs based on Cu-containing mixed-ionic-electronic conduction (MIEC) materials [1–7]. These devices requireonly the low processing temperatures of the back-end-of-the-line, making them highly suitablefor implementing multi-layer cross-bar arrays. MIEC-based ADs offer large ON/OFF ratios(>1e7), a significant voltage margin Vm (over which current <10 nA), and ultra-low leakage(< 10 pA), while also offering the high current densities needed for phase-change memory andthe fully bipolar operation needed for high-performance RRAM. Scalability to critical lateraldimensions < 30 nm and thicknesses < 15 nm, tight distributions and 100% yield in large (512kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50 ns turn-ON timeshave all been demonstrated. Numerical modeling of these MIEC-based ADs shows that theiroperation depends on +Cu mediated hole conduction. Circuit simulations reveal that while scaledMIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low (< 1.2 V)switching voltages, stacking two MIEC devices can support large crossbar arrays for switchingvoltages up to 2.5 V.

Keywords: MIEC, access devices, nonvolatile memory, memristive devices

Semiconductor Science and Technology

Semicond. Sci. Technol. 29 (2014) 104005 (11pp) doi:10.1088/0268-1242/29/10/104005

0268-1242/14/104005+11$33.00 © 2014 IOP Publishing Ltd Printed in the UK1

(Some figures may appear in colour only in the online journal)

1. Introduction

A crossbar array consists of a dense, cartesian array of inter-connections at the crossover points between two planes of clo-sely-spaced wires running at right angles to each other. If boththe wires and the spaces between them have width F, then thearea per connection is 4F2. A crossbar memory device must be atwo-terminal device that can be reliably, repeatedly, and readilyswitched between at least two resistance states, preferably with alarge resistance contrast. This switching operation must notrequire excessive power, yet the device should be capable ofsurviving through many millions, if not billions or more, ofswitching cycles. Each read operation, at lower voltages andcurrents than the switching operation, needs to supply currentsufficient for distinguishing the various states. Yet even a verylarge number of successive read operations must not induce aswitching event.

Research over the past 10–15 years, originally motivatedby the desire to have a ‘backup device’ in case either NANDor NOR Flash had trouble scaling to smaller dimensions, hasproduced a number of viable two-terminal non-volatilememory (NVM) devices [8–10], including memristive devi-ces [11]. There has been a general realization that many ofthese two-terminal NVM devices might offer better perfor-mance than NAND Flash through much lower latencies andmuch higher program-erase endurance. This opportunity isreferred to collectively as Storage Class Memory [8, 12].

Here we focus on the leap from a single, ‘state-holding’memory device to a large array of memory devices. Ideally,within a vast matrix of densely packed devices, we would beable to write and read any small subset of the memory devicesat will, yet all other devices would remain completely

unperturbed, dissipating zero additional power beyond thatrequired for writing or reading. We can come close to thisideal by introducing a strongly nonlinear −I V characteristic—an access device (AD)—together with the state-bearingmemory element at every crossbar node.

One way to introduce this nonlinearity is to integrate asecond two-terminal device—such as a diode, switch, or othersimilar element—in series with each state-holding (NVM)element. These devices can each be optimized separately, andthen integrated together in the final semiconductor processingscheme, though this may increase the number of processingsteps. An alternative approach is to simply add the need formassive nonlinearity to the already long list of criteria that theprospective state-holding element must deliver. If successful,this approach leaves only one device to integrate; unfortu-nately, the criteria for state-holding devices is quite dauntingalready, without adding a strong nonlinearity of many ordersof magnitude—at exactly the ‘right’ voltage —to the list.

In this review article, we briefly overview crossbarbiasing schemes, and discuss the need to minimize leakagethrough various non-selected cells while delivering the rightvoltages and currents to the selected cell. After summarizingthe list of criteria for an AD, we briefly review currentresearch on various discrete AD options [13]. These includeconventional silicon-based semiconductor devices, oxidesemiconductors, threshold switch devices, oxide tunnel bar-riers, and various approaches for self-selected RRAM [13].We then review our research on ADs based on mixed-ionic-electronic-conduction (MIEC) [1–7], and show that thesedevices are highly suitable for multi-layer crossbar memoryfor resistive-NVM devices with modest switching voltages.

Figure 1. (a) In a crossbar array of resistive-NVM devices, voltage applied at the edge of the array, to select one or more memristor/select-device pairs, also affects three other sets of memristor+ADs: those in the same row, in the same column (both half-selected), and all others(un-selected). These effects can be minimized by appropriate choice of the intermediate voltagesVc and Vr applied to unselected columns androws. (b) The total voltage drop across any selected resistive-NVM device must be sure to switch the device, despite the additional voltagedrop in its own AD and in the wiring. However, that same applied voltage must not lead to excessive leakage in either the half-selected or un-selected devices. In a 1000 × 1000 array, for example, there will be ∼2000 half-selected devices and nearly one million un-selected devices.(Copyright © IEEE. All rights reserved. Reprinted, with permission, from [5]. Personal use of this material is permitted. However, permissionto reuse this material for any other purpose must be obtained from the IEEE.)

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2. Crossbar arrays

In a crossbar array, a set of voltages is applied at the edge of agiven sub-array within the chip, such that the desired opera-tions (reads and writes) take place at the desired selected cells,yet all un-selected cells remain unperturbed and overall powerdissipation remains manageable. It can be readily shown [14]that it is nearly impossible to implement a crossbar array ofany practical size without a strong nonlinearity at each node—we will not repeat such analyses here. Each sub-arrayshould be as large as possible, to amortize the peripheralcircuitry placed at the edge for rapidly driving the largewriting currents and for accurately sensing the small readcurrents. The larger these sub-arrays, the larger the areaefficiency: the fraction of silicon used for memory bits, andsuch higher area efficiency typically leads to a lower cost-per-bit.

While there is a strong incentive to make sub-arrays aslarge as possible, this must be traded off against the problemsassociated with large sub-arrays, including significant linecapacitance, large worst-case resistance drop, and difficultiesin enforcing compliance currents within the array [13]. Amajor issue is the aggregate leakage through all the devicesother than those selected for write. Such leakage can beconstrained by careful choice of the biasing scheme: theintermediate voltages that are applied to all the other wireswithin the array, so as to minimize the overall leakage andprevent any undesired disturbance to previously stored data.

As shown in figure 1, these other devices in the array fallinto three classes: the half-selected devices along the samerow as a selected device, the half-selected devices along thesame column as a selected device, and the un-selected devicesthat share neither a row nor a column with any selecteddevice. The ‘V/3’ scheme [14–17]—in which applied voltageis split into three parts, one for each of the three classes ofnon-selected devices—is highly useful when supplying largewriting voltages to one or more selected devices. As shown infigure 1, the sum of these three voltage drops is roughly equalto the effective voltage drop across the selected device. Whilethe name ‘V/3’ would suggest division into three equal vol-tages, it often makes sense to reduce the voltage across themany un-selected devices until total aggregate leakage isminimized (figure 1) [13].

During write operations, it is critical to deliver thenecessary voltage and current to the selected cell whileavoiding two undesirable outcomes: dissipating too muchaggregate power, and risking even the remote possibility thatany of the non-selected cells might accidentally switch. Forlarge arrays, excess power dissipated during write may reducethe achievable write parallelism (and thus write bandwidth),and large sub-arrays lead to more aggregate leakage andlarger CV1

22 energy for driving wires to the desired voltage

levels.During read operations, since both the currents and the

associated device voltages are typically significantly smaller,a ‘V/2’ scheme can be used, where the voltage applied to thewires leading to un-selected devices is either brought to zeroor alternatively, these lines are allowed to float [15, 18, 19].

During read, the strong nonlinearity at each node suppressesthe many potential ‘sneak paths’ that could lead to inaccuratesensing of the state of selected devices.

A final consideration is the (hopefully) small fraction ofADs that fail in a low resistance, or ‘shorted,’ state. Suchdevices act just like strong ‘sneak paths,’ masking read cur-rents from all devices that share the same sense-amplifier anddissipate significant power during write. One approach forcombatting this problem, demonstrated for two-terminalMIEC-based ADs in series with phase-change memory(PCM) [3], is to place the state-bearing device (associatedwith the shorted AD) into an extremely high resistance state.This is possible for PCM because negative polarity pulses thatare ramped down slowly are known to lead to phase-separa-tion of the phase-change material [20, 21], producing a veryhigh resistance state. Although this requires a voltage similarto very large writing voltages, this corrective action can betaken without damaging neighboring devices because thefailed AD is not consuming any of the voltage drop. TheNVM device, once in this ultra-high resistance state, thenprotects the array from the leakage that would otherwise beinduced by the shorted AD. Unfortunately, it is not yet clear ifother resistive-NVM devices besides PCM can be placed insuch a high-resistance state with voltage sequences that canbe applied within the array without damaging neighboringhealthy device pairs.

3. AD requirements

An AD should be capable of a high ON-state current density,so it can supply high currents through its small cross-sectionalarea, as needed to program and erase memory elements. Sinceun-selected cells vastly outnumber the selected cells, theADʼs OFF-state leakage current needs to be as low as pos-sible, so as to prevent the aggregate leakage through all theun-selected cells from dominating the overall system powerbudget. Satisfying both of these first two points (high ON-state current and low OFF-state leakage) simultaneouslyimplies that the AD must have a highly nonlinear I–V curve.

Many resistive-NVM devices candidates either showbetter reliability, or only operate correctly, when program anderase pulses use opposite voltage polarities, requiring that theAD support bidirectional operation. Process compatibilitywith 3D multilayer stacking allows the AD, like most emer-ging resistive-NVM elements, to be located above the wafersurface without consuming active Si wafer area. This frees upSi area for placement of some peripheral circuits underneaththe crossbar memory array, and enables multi-layer stackingof arrays if the AD (and NVM) can be fabricated in a back-end-of-the-line (BEOL)-compatible process. Such a processcan involve prolonged and repeated exposures to tempera-tures of ∼ °400 C, yet forbids processing at any temperaturessignificantly higher than this value.

The AD must achieve voltage compatibility with thememory element with which it is paired. If the ADʼs turn-onvoltage is much lower than that needed across the selectedmemory element, array biasing voltages will lead to large

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currents through the half-selected cells, degrading the effec-tive selectivity and ON/OFF ratio of the ADs [7]. All otherproperties of the AD should be better than or equal to that ofthe memory element, so that its switching speed, cyclingendurance, array yield, and variability do not limit the per-formance of the resulting memory chip.

4. Other proposed ADs

The set of requirements listed above have made it verychallenging to find ADs that are fully suitable for high-den-sity, 3D multilayer resistive crossbar memory [13].

After decades of research and development, Si-basedADs are very well understood. However, three-terminaldevices are non-trivial to implement in a 4F2 footprint, anddevices that require single-crystal silicon preclude 3D multi-layer stacking. Polysilicon devices can be stacked, but typi-cally require high (> °400 C) fabrication temperatures [13].

The main advantage of oxide PN junction ADs is theirlow fabrication temperature, providing compatibility with 3Dmultilayer stacking approaches. ADs based on metal-oxideSchottky barriers offer both relative ease of integration andlow (< °400 C) processing temperatures. However, the ON-state current density of both oxide PN junctions and metal-oxide Schottky barriers needs improvement by several ordersof magnitude for operation with most resistive memory ele-ments [13]. Both Si rectifiers and oxide PN junction diodessupport only unipolar operation, and will not work withbipolar memory elements. However, it is possible to getbidirectional operation using Si NPN punchthrough diodes[22] or metal-oxide-metal Schottky barrier devices withappropriately chosen metal electrodes [23, 24].

Three types of threshold switches have been proposed aspotential ADs for resistive-NVM devices [13]: ovonicthreshold switching (OTS) devices [25], Metal-insulatortransition (MIT)-based devices [26, 27], and the thresholdvacuum switch (TVS) [28]. OTS devices have been shownwith good switching performance and in large arrays [25], butrequire complex materials and improvements in switchingendurance and leakage current will be needed. It is also notyet clear what sort of RRAM switching voltages and stateresistances which OTS or other threshold ADs might be ableto accommodate.

In contrast, MIT and TVS switches have been demon-strated only at the few-device level, both individually and inseries with RRAM devices. While MIT devices using mate-rials such as NbO2 with acceptably high threshold tempera-tures have been demonstrated [27], it will be important tofurther reduce the half-select and un-select leakage currents.Also, higher threshold temperature implies that added elec-trothermal power is being used to trigger the MIT behavior,which could potentially increase the overall power requiredfor NVM switching. The TVS device [28] is interesting, but itwill be critical to demonstrate that sufficiently identicalvacuum gaps, leading to tightly distributed electrical switch-ing characteristics, can be demonstrated at high yield overlarge arrays of TVS ADs.

Oxide tunnel barriers offer steeply nonlinear curves, andhave attained success in combination with various memoriesincluding conductive-bridging RAM (CB-RAM) and non-filamentary conductive metal oxides [29, 30]. However, it isextremely important that the switching voltages of the RRAMremain low so that the half-select leakage—as evaluated at ahalf (or in the ‘V/3’ scheme, at roughly a third) of the appliedvoltage across both memory and AD, as well as across anyextra bias dissipated in the wiring—can still be low.

Methods for adding AD functionality to resistive-NVMdevices [13] include the complementary resistive switch(CRS) [31], hybrid devices in which AD functionality isincorporated together with the memory functionality [32, 33],and nonlinear RRAM, in which barrier layers introducenonlinearity to help reduce leakage current [34–37]. Althougha CRS device can significantly reduce sneak-path currents,destructive readout with subsequent write-back is required. Inaddition, each CRS device must either be fabricated from astack of two well-behaved and symmetric memory elements[31], or a single RRAM layer with very precise control overoperating voltages [38, 39]. A particularly important step willbe the demonstration of reliable CRS operation at the lowswitching currents (20– μ50 A) required for implementation inthe narrow-pitch wiring of advanced technology nodes [19].

Another aspect of self-selected memories is the difficultyin independently tuning select-device and memory function-ality. This is more of an issue in hybrid devices using MIT ortunnel barriers which participate in the motion of oxygenions, since the select function is nearly inseparable from thememory function. While nonlinearity can be tuned byincreasing the thickness of an added tunnel barrier, themaximum nonlinearities achieved so far fall well short of thelarge (106

–107) values needed for large (1000 × 1000) sub-arrays [35, 37].

5. MIEC

BEOL-friendly AD based on Cu-containing MIEC materials[1–5] have become an intriguing choice as 3D-ready ADs forNVM. MIEC-based ADs offer large ON/OFF ratios (>107),high voltage margin Vm (over which current <10 nA), andultra-low leakage (< pA10 ), while also offering the highcurrent densities needed for PCM and the fully bipolaroperation needed for high-performance RRAM [1, 2].

These devices contain a large amount of mobile copperions, which can move readily within the MIEC material. Ourprimary, ‘Process-Of-Record’ (POR) MIEC material is in factmore than 50% copper by weight. No silver (Ag)-basedMIEC material has yet delivered similar IV characteristicswhen fabricated in a confined via. The discussion belowconsiders a confined device fabricated from the Cu-containingPOR material.

At low bias, Schottky barriers at the MIEC-electrodeinterfaces are believed to help suppress current flow, leadingto the ultra-low leakage. As bias increases in either direction,copper ions and vacancies shift accordingly within the device,modulating the interfaces and leading to an exponential

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increase in electronic current [6]. Although the currenteventually saturates, extremely high current densities havebeen observed (up to −50 MA cm 2 (figure 3) [1]).

The large amounts of copper present might suggest afilamentary role in the operation of these MIEC-based ADs,similar to the way CB-RAM [40] and even some memristive[41] NVM devices are known to operate. However, ourextensive experimental evidence does not support thishypothesis at all. The turn-ON of symmetric MIEC-basedADs (figure 2(a)) does not exhibit filamentary behavior [2],and devices clearly show area-scaling of current over a widerange of electrode sizes (figure 3) [1]. The long-term repeat-ability and stability of MIEC-based ADs over a wide range ofcurrents (figure 4) is also highly inconsistent with a fila-mentary role [5].

However, the I–V characteristics of highly asymmetricdevices—such as the devices shown in (figure 2(b)) whichhave a top electrode contact (TEC) that is much larger( μ>80 m diameter) than its bottom electrode contact (BEC∼ 80 nm)—do illustrate that filament formation can occur inthis material. In such a configuration, positive voltage on thelarge-area contact drives a very large concentration of copperions to the small-area contact, allowing filament formation tooccur before the normal exponential-like turn-ON of a healthyMIEC-based AD can be observed. This is true even whenboth electrodes are inert (non-ionizable), such as the deviceshown in dark-field TEM in the inset of figure 2(b). In thissense, a symmetric MIEC-based AD is effectively a frustratedCB-RAM device—one that might want to form a filament butlacks sufficient copper ion density to do so.

Note that a highly-asymmetric MIEC-based AD can berepeatedly and continuously exercised under the ‘good’ vol-tage polarity, where positive voltage on the smaller electrodedrives copper ions towards the larger electrode (left side offigure 2(b)). Only upon application of voltage under the ‘bad’

polarity, with positive voltage on the larger electrode drivingcopper ions into the confined reservoir at the smaller electrode(right side of figure 2(b)), will a copper filament form. Such afilament has extremely low resistance, and thus completelydominates electronic conduction unless and until it is fullyremoved by large voltages or thermal treatment [2].

Failure of MIEC-based ADs has been extensively stu-died, and is generally attributed to agglomeration of Cu-richregions within the device, and the eventual formation of afilament that bridges the device and shorts out the device [2].Although higher drive currents have been observed to sharply

Figure 2. (a) Measured I–V characteristics for symmetric devices (here a 5 × 10 array of diode-in-via MIEC-based ADs, tested with integratedFETs) show an exponential increase of current for both polarities. The voltage margin, defined as the span over which median leakageremains below 10 nA, is tightly distributed (here ∼Vm 1.1 V). (b) In contrast, superimposed I-V characteristics of sixty asymmetric devices,where the bottom electrode contact (BEC) is much smaller (∼80 nm) than the top electrode contact ( μ>3 m, ionizable TEC), are markedlydifferent. Negative bias on the TEC produces very tight, exponential diode-like I-V characteristics. At moderate positive bias, Cu+ ions sweptfrom the large TEC into the tiny via form a metallic filament, masking the diode-like action that would have been present in a symmetricdevice. Inset shows a dark-field TEM image of a device with the same nominal electrode dimensions, except that it used a non-ionizable(Tungsten) TEC—such devices exhibited similar I-V characteristics. (Copyright c IEEE. All rights reserved. Reprinted, with permission, from[1, 2]. Personal use of this material is permitted. However, permission to reuse this material for any other purpose must be obtained fromthe IEEE.)

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reduce cycling endurance, ∼108 cycles has been demonstratedat μ∼150 A [2]. Endurance at lower currents is so high as tobe difficult to measure, and is known to be >1e10 cycles at

μ∼5 A [1] and >12 h of continuous dc exposure at ∼30 pA(figure 4(a)) [5].

While copper ions in a healthy symmetric MIEC-basedAD are not able to form a filament, these ions do play acritical role in its electrical characteristics. Numerical simu-lations including both positively-charged copper ions as wellas negatively-charged vacancy sites have been able to quan-titatively match the electrical characteristics of MIEC-basedADs (figure 5) [6]. These simulations suggest that at low bias,mobile ions settle into a U-shaped distribution with largeelectric fields at each interface, maintaining a dynamic equi-librium between electrostatic ion drift towards, and ion dif-fusion away from, each interface. The strong ionaccumulation at each interface results in residual electrontunneling at each interface, but strong suppression of holesand hole current. Device turn-ON occurs as hole injectionfrom the positively-biased electrode increases sharply, drivenby motion of large populations of copper ions and vacancies[6]. Asymmetry between top and bottom electrodes leads toasymmetric I–V characteristics, since both ion densities andthe mapping from current density to current are affected bythe geometry of the device with respect to the polarity ofoperation.

Integration of MIEC-based ADs has been demonstratedon ″8 wafers, with Cu-containing MIEC material sputteredinto vias followed by an optimized CMP process [2] and aconfined, non-ionizable TEC. Conductive-AFM testing ofshort-loop devices with minimal wiring has validated single-target deposition and revealed a wide processing temperaturewindow (up to °500 C) for these MIEC-based ADs [3].Although these ADs do not need high processing tempera-tures, MIEC-based ADs would not be adversely affected if aco-integrated RRAM or other NVM did require such pro-cessing conditions.

Bi-directional array diagnostic monitor (ADM) arrays ofup to 512 × 1024 integrated MIEC-based ADs have beentested using integrated 1-bit sense-amplifiers and a fast elec-trical tester (Magnum 2 EV) [3]. Cumulative distributionfunctions (CDFs) of the bitline voltage VBL needed to producevarious device currents Id show tightly distributed array I–Vcharacteristics (figure 6(a)). All 524 288 MIEC-based ADs—100% yield—hadVm >1.1 V, and 99.955% of ADs fell within±150 mV of the median voltage margin =V 1.36 Vm at10 nA (figure 6(b)) [3]. Multiple such ADMs across twowafers showed very similar yield values.

Thickness scaling experiments showed that as MIEC-based ADs become thinner, voltage margin remains mostly

Figure 4. MIEC-based ADs maintain (a) ultralow-leakage over hours of exposure, whether in a deep (±230 mV) or shallow un-select(±350 mV) condition, and even (b) repeated 2sec exposures to half-select (±530 mV) and even higher bias conditions has minimal impact onsubsequent leakage, all highly inconsistent with filamentary operation. (Copyright c IEEE. All rights reserved. Reprinted, with permission,from [5]. Personal use of this material is permitted. However, permission to reuse this material for any other purpose must be obtained fromthe IEEE.)

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Figure 5. A commercial device simulator was adapted to modelaccess devices (AD) based on cu-containing mixed-ionic-electronic-Conduction (MIEC) materials. Ultralow leakage at low bias due toresidual electron tunneling, with hole current suppressed by a central‘quasineutral’ region, gives way to device turn-ON as hole injectionfrom the positively-biased electrode increases sharply, driven bymotion of large populations of copper ions and vacancies. MeasuredI-V characteristics can be matched in simulation, including ultralowleakage currents, voltage turn-ON values, and the > 7 orders ofmagnitude current increase. Insets show bright-field TEM images ofthe tested device. [6].

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Semicond. Sci. Technol. 29 (2014) 104005 R S Shenoy et al

unchanged until the minimum gap between electrodes, dmin,reaches ∼ −11 12 nm [4]. Short-loop MIEC-based ADs fab-ricated with ultra-scaled vias show both high yield and highvoltage margin [4]. Despite their small size, these MIEC-based ADs can still rapidly drive the large currents needed forNVM switching (figure 7(a)). Voltage margin Vm (at 10 nA)improves markedly as devices are scaled in lateral size.Aggressively-scaled MIEC-based ADs retain all requisitecharacteristics, including ultra-low leakage (<10 pA) and thelarge voltage margins ( >V 1.50 Vm ) needed for large arrays,even with both top and bottom critical dimensions (CDs)< 30 nm (figure 7(b), (c)). Unlike thickness scaling, whereleakage increases sharply below ∼dmin 11 nm, no lower limitto CD scaling has yet been identified [4].

Integration of MIEC-based ADs immediately abovesmall (CD ∼35 nm) PCM devices allowed testing ofintegrated PCM+MIEC device pairs. Figure 8 demonstratesendurance in excess of 100 000 cycles, despite the repeatedapplication of RESET pulses μ>200 A and 5 μs long SETpulses at μ∼90 A [3]. To demonstrate NVM write speedcapabilities, an MIEC-based AD was used to rapidlyRESET a co-integrated PCM device. After each 15 nsRESET pulse at varying amplitude (figure 9(a)), a longSET pulse recrystallized the doped-Ge2Sb2Te5 PCMmaterial. After each pulse, bipolar dc I–V curves(figure 9(b), (c)) showed the expected change in the PCMresistance above the same low-leakage characteristics ofthe MIEC-based AD [4].

Figure 6.Cumulative distribution functions (CDFs) across bitline voltageVBL at various device currents Id (a) show array level I-V results withtight distributions across a 512 × 1024 array of integrated MIEC-based ADs [3]. These devices were nominally the same lateral size as thedevice shown in the inset of figure 2(a), but were about 30% thinner. (b) Within this same 512 × 1024 array, there were no leaky devices;100% of the array showed Vm > 1.1 V, while 99.955% of MIEC-based ADs had voltage margins Vm at 10 nA within ±150 mV of the medianof 1.36 V. (Copyright c IEEE. All rights reserved. Reprinted, with permission, from [3]. Personal use of this material is permitted. However,permission to reuse this material for any other purpose must be obtained from the IEEE.)

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Figure 7. (a) In addition to high yield, scaled short-loop MIEC-based ADs [4] exhibit the same > 1e7 ON-OFF contrast, < 50 ns turn-ONtimes (test-setup-limited), and ultra-low leakage shown in larger devices [2, 3]. Aggressively-scaled short-loop MIEC-based ADs, with (b)both TEC and BEC < 30 nm, also show (c) large voltage margins and ultra-low leakage. (Copyright c IEEE. All rights reserved. Reprinted,with permission, from [4]. Personal use of this material is permitted. However, permission to reuse this material for any other purpose mustbe obtained from the IEEE.)

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Semicond. Sci. Technol. 29 (2014) 104005 R S Shenoy et al

1uA

100nA

10nA

1nA

100pA

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

Cur

rent

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rent

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rent

DC reads SET

RESET

Voltage [V]

1mA

100uA

10uA

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10pA10 100 1k 10k 100k

[uA

] 250200

150

100

50

00 2 4 6

Time [us]

RESETPulses

Pulses

SET

RESET SET

DC leakage (+100mV)DC reads (660mV)

CycleFigure 8. Endurance of an integrated PCM+MIEC device-pair to > 100 k cycles, with RESET currents μ>200 A and 5 μs-long SET pulses(∼90 μA). No AD degradation or PCM failure had occurred at the time testing was terminated. (Copyright c IEEE. All rights reserved.Reprinted, with permission, from [3]. Personal use of this material is permitted. However, permission to reuse this material for any otherpurpose must be obtained from the IEEE.)

500uA

400uA

300uA

200uA

100uA

0

1uA

100nA

10nA

1nA

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-1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5

Current15ns

5 ns/division

Increasing

Increasing

pulse

pulse

amplitude

amplitude

Time

Cur

rent

Cur

rent

Voltage Voltage

a)

b) c)

Figure 9. After each (a) single 15 ns RESET pulse, bipolar dc I-V curves show the large resistance contrast (∼1 M Ω) of PCM RESETdevices, yet the low-leakage characteristics of the MIEC-based AD remain unaffected, in both the (b) RESET and (c) SET states (Copyright cIEEE. All rights reserved. Reprinted, with permission, from [4]. Personal use of this material is permitted. However, permission to reuse thismaterial for any other purpose must be obtained from the IEEE.).

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Semicond. Sci. Technol. 29 (2014) 104005 R S Shenoy et al

We expect that MIEC-based ADs should prove equallycompatible with integration of RRAM and STT-MRAMdevices. For RRAM, the 180 nm test vehicle (ADM) used forfigure 6 proved unsuitable, because it could not providesufficient control over current compliance, either at the edgeof the array or even at each device. Work is ongoing tointegrate STT-MRAM devices together with MIEC ADs, butno test results are yet available. Challenges for STT-MRAMinclude rapid read and write speeds [5], as well as the need todistinguish between two very similar resistance states.

These considerations—enforcing compliance and imple-menting low-contrast sensing—will be issues for any two-terminal AD, and not just for MIEC-based ADs. ADs thatexhibit extremely low variability should provide a highdegree of control over RRAM programming currents. How-ever, initial research explorations will likely require reliableand independent control over compliance at each cell in orderto unambiguously assess the performance of an RRAM

integrated together with any two-terminal AD. Similarly,while low variability is essential for distinguishing low-con-trast STT-MRAM read currents across a large array, the firststep is to show that co-integration is viable and that singledevice-pairs can be switched and read reliably.

As mentioned previously, it has been shown that theultra-low leakage offered by MIEC-based ADs representingthe un-selected state can be held for hours (figure 4(a)), whilehigher half-selected leakage can be sustained for at least a fewseconds (figure 4(b)), more than long enough for millions ofsuccessive μ1 s reads to the same bitline [5]. In addition,MIEC-based ADs can return rapidly from either the selected-for-read or selected-for-write states [5]. The leakage recoveryafter write μ−(30 50 A) operations requires μ∼1 s, with post-read μ−(3 6 A) recovery being even faster. The application ofshaped pulses or a transient ‘overvoltage’ read readily allowsMIEC-based ADs to support ∼5– μ10 A NVM reads in<50 ns, fast enough for use with MRAM (figure 10) [5].

Figure 10. (a) While thick MIEC-based ADs can transition from half-select to 10 μA read currents in ∼50 ns with significant over-voltage, (b)even the un-accelerated native turn-ON in thinner MIEC-based ADs is measurably fast. (Copyright c IEEE. All rights reserved. Reprinted,with permission, from [5]. Personal use of this material is permitted. However, permission to reuse this material for any other purpose mustbe obtained from the IEEE.)

Figure 11. Circuit-level SPICE simulations of large 1AD+1R (MIEC-based ADs + a generic NVM) cross-bar arrays reveal that (a) NVMswitching voltages (VHRS, VLRS) are much more critical for low power operation than switching currents (IHRS, ILRS). Even small increases inVHRS beyond the maximum value (that a given AD can support) greatly inflates the voltages that must be applied at the edge of the array,leading to enormous excess power dissipation. (b) Despite these constraints, arrays of up to 1 Mb in size up can be supported by scaledMIEC-based ADs ( ∼Vm 1.54 V) for NVM devices with switching voltages up to ∼VNVM 1.2 V, and a simple stack of two MIEC-based ADsenables large arrays for VNVM up to ∼2.4 V. [7]

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Semicond. Sci. Technol. 29 (2014) 104005 R S Shenoy et al

Inherently-fast thin MIEC-based ADs offer similar speeds atmodest overvoltages, which is important for minimizing thepossibility of read disturb [5].

The design space for crossbar arrays composed of ADsbased on MIEC has been explored using circuit-level SPICEsimulations. This modeling shows that achievable array sizeand the excess required power during write depends stronglyon careful matching between the turn-ON voltage Vm of theAD and the switching voltage VNVM of the memory device(figure 11(a)) [7]. In contrast, the dependence of excess writepower on NVM switching currents INVM is much less critical.Scaled MIEC-based devices ( ∼Vm 1.54 V) have been shownto support arrays of 1 Mb in size up to NVM switchingvoltages of ∼VNVM 1.2 V (figure 11(a)), and a simple stack oftwo MIEC-based devices enables ∼VNVM 2.4 V(figure 11(b)) [7].

6. Conclusion

Access devices (ADs) based on copper-containing MIECmaterials [1–7] make for an ideal companion to resistive-NVM devices for implementing large, densely-packed, multi-layer crossbar arrays. These MIEC-based ADs are well-suitedfor both the scaled CDs and thicknesses of advanced tech-nology nodes, and for the fast read and write speeds ofemerging NVM devices, and require only the low processingtemperatures of the BEOL. They offer large currents (

μ>100 A), bipolar operation, large ON/OFF ratios (> 107 ), asignificant voltage margin Vm (over which current < 10 nA),and ultra-low leakage (< 10 pA). Co-integration with PCM,integration in large (512 kBit) arrays with 100% yield andtight distributions, fast transient operation, long-term persis-tence of the required ultra-low-leakage, and scalability toaggressive technology nodes have all been demonstrated. Theoperation of these MIEC-based ADs is believed to depend on

+Cu -mediated hole conduction, and SPICE analysis hasshown them to be highly suitable for any crossbar array builtwith resistive-NVM devices with modest (<2.5 V) switchingvoltages.

Future desired improvements in MIEC-based ADs wouldinclude better endurance at high current (currently ∼10 8

cycles at μ150 A [2]), study of the temperature dependence ofvoltage margin, verification of high endurance and lowvariability in ultra-scaled devices at both high and lowoperating temperatures, and increases in the voltage margin soas to enable large arrays for NVM devices requiring largerswitching voltages.

References

[1] Gopalakrishnan K et al 2010 Highly-scalable novel AD basedon Mixed Ionic Electronic Conduction (MIEC) materials forhigh density phase change memory (PCM) arrays Symp.VLSI Tech. p 19.4

[2] Shenoy R S et al 2011 Endurance and scaling trends of novelADs for multi-layer crosspoint-memory based on Mixed

Ionic Electronic Conduction (MIEC) materials Symp. onVLSI Technology pp T5B–1

[3] Burr G W et al 2012 Large-scale (512kbit) integration ofmultilayer-ready ADs based on Mixed-Ionic-Electronic-Conduction (MIEC) at 100% yield Symp. on VLSITechnology p T5.4

[4] Virwani K et al 2012 Sub-30nm scaling and high-speedoperation of fully-confined ADs for 3-D crosspoint memorybased on Mixed-Ionic-Electronic-Conduction (MIEC)materials IEDM Technical Digest 2.7

[5] Burr G W et al 2013 Recovery dynamics and fast (sub-50ns)read operation with ADs for 3D crosspoint memory basedon Mixed-Ionic-Electronic-Conduction (MIEC) Symp. onVLSI Technology T6.4

[6] Padilla A et al 2014 The origin of massive nonlinearity inMixed-Ionic-Electronic-Conduction (MIEC)-based ADs, asrevealed by numerical device simulation 72nd DeviceResearch Conf. 22–25 June 2014 Poster III-53

[7] Narayanan P, Burr G W, Shenoy R S, Stephens S, Virwani K,Padilla A, Kurdi B and Gopalakrishnan K 2014 Exploringthe design space for resistive nonvolatile memory crossbararrays with Mixed-Ionic-Electronic-Conduction (MIEC)-based ADs 72nd Device Research Conf. 22–25 June 2014session V-A

[8] Burr G W, Kurdi B N, Scott J C, Lam C H,Gopalakrishnan K and Shenoy R S 2008 Overview ofcandidate device technologies for storage-class memory IBMJ. Res. Dev. 52 449–64

[9] Raoux S et al 2008 Phase-change random access memory: ascalable technology IBM J. Res. Dev. 52 465–80

[10] Burr G W et al 2010 Phase change memory technology J. Vac.Sci. Technol. B 28 223–62

[11] Strukov D B, Snider G S, Stewart D R and Williams R S 2008The missing memristor found Nature 453 80–83

[12] Freitas R and Wilcke W 2008 Storage-class memory: the nextstorage system technology IBM J. Res. Dev. 52 439–48

[13] Burr G W, Shenoy R S and Hwang H 2015 Chapter 23: Selectdevice concepts for cross-bar arrays Resistive Switching-From Fundamentals of Nanoionic Redox Processes toMemristive Device Applications (New York: Wiley)

[14] Chen A 2013 A comprehensive crossbar array model withsolutions for line resistance and nonlinear devicecharacteristics IEEE Trans. Electron Devices 60 1318–26

[15] Chen A 2011 Accessibility of nano-cross-bar arrays of resistiveswitching devices Nanotechnology (IEEE-NANO) 2011 11thIEEE Conf. pp 1767–71

[16] Zhang L, Cosemans S, Wouters D J, Groeseneken G andJurczak M 2012 Analysis of the effect of cell parameters onthe maximum RRAM array size considering both read andwrite ESSDERC p 282–5

[17] Deng Y X, Huang P, Chen B, Yang X L, Gao B, Wang J C,Zeng L, Du G, Kang J F and Liu X Y 2013 RRAM crossbararray with cell selection device: a device and circuitinteraction study IEEE Trans. Electron Devices 60 719–26

[18] Liang J and Wong H-S P 2010 Cross-point memory arraywithout cell selectors-device characteristics and data storagepattern dependencies IEEE Trans. Electron Devices 572531–8

[19] Liang J L, Yeh S, Wong S S and Wong H S P 2013 Effect ofwordline/bitline scaling on the performance, energyconsumption, and reliability of cross-point memory ACM J.Emerging Technol. Comput. Syst. 9 9

[20] Padilla A et al 2010 Voltage polarity effects in GST-basedphase change memory: physical origins and implicationsIEDM Technical Digest p 29.4

[21] Padilla A et al 2011 Voltage polarity effects in Ge Sb Te2 2 5

-based phase change memory devices J. Appl. Phys. 110054501

10

Semicond. Sci. Technol. 29 (2014) 104005 R S Shenoy et al

[22] Srinivasan V S S et al 2012 Punchthrough-diode-based bipolarRRAM selector by Si epitaxy IEEE Electron Device Lett. 331396–8

[23] Huang J-J, Tseng Y-M, Luo W-C, Hsu C-W and Hou T-H 2011One selector-one resistor (1S1R) crossbar array for high-densityflexible memory applications IEDM Technical Digest p 31.7

[24] Huang J J, Tseng Y M, Hsu C W and Hou T H 2011 Bipolarnonlinear Ni/TiO2/Ni selector for 1S1R crossbar arrayapplications IEEE Electron Device Lett. 32 1427–9

[25] Kau D C et al 2009 A stackable cross point phase changememory IEDM Technical Digest p 27.1

[26] Son M, Lee J, Park J, Shin J, Choi G, Jung S, Lee W, Kim S,Park S and Hwang H 2011 Excellent selector characteristicsof nanoscale VO2 for high-density bipolar ReRAMapplications IEEE Electron Device Lett. 32 1579–81

[27] Kim S el al 2012 Ultrathin (<10nm) Nb2O5/NbO2 hybridmemory with both memory and selector characteristics forhigh density 3D vertically stackable RRAM applicationsSymp. on VLSI Technology T18.3

[28] Ho C H et al 2012 Threshold vacuum switch (TVS) on 3D-stackable and 4F2 cross-point bipolar and unipolar resistiverandom access memory IEDM Technical Digest p 2.8

[29] Woo J et al 2013 Multi-layer tunnel barrier (Ta2O5/TaOx/TiO2)engineering for bipolar RRAM selector applications Symp.on VLSI Technology p T12.4

[30] Woo J, Lee D, Cha E, Lee S, Park S and Hwang H 2013Multilayer-oxide-based bidirectional cell selector device forcross-point resistive memory applications Appl. Phys. Lett.103 202113

[31] Linn E, Rosezin R, Kuegeler C and Waser R 2010Complementary resistive switches for passive nanocrossbarmemories Nat. Mater. 9 403–6

[32] Meyer R, Schloss L, Brewer J, Lambertson R, Kinney W,Sanchez J and Rinerson D 2008 Oxide dual-layer memoryelement for scalable non-volatile cross-point memorytechnology NVMTS 2008

[33] Chevallier C J, Siau C H, Lim S F, Namala S R, Matsuoka M,Bateman B L and Rinerson D 2010 A μ0.13 m 64 Mbmulti-layered conductive metal-oxide memory ISSCC 2010p 14.3

[34] Lee H D et al 2012 Integration of 4F2 selector-less crossbararray 2Mb ReRAM based on transition metal oxides for highdensity memory applications Symp. on VLSI Technologyp T18.1

[35] Park S-G et al 2012 A non-linear ReRAM cell with sub-1 μAultralow operating current for high density vertical resistivememory (VRRAM) IEDM Technical Digest p 20.8

[36] Yang J J et al 2012 Engineering nonlinearity into memristorsfor passive crossbar applications Appl. Phys. Lett. 100113501

[37] Lentz F, Roesgen B, Rana V, Wouters D J and Waser R 2013Current compliance-dependent nonlinearity in TiO2 ReRAMIEEE Electron Device Lett. 34 996–8

[38] Nardi F, Balatti S, Larentis S and Ielmini D 2011Complementary switching in metal oxides: toward diode-less crossbar RRAMs IEDM Technical Digest p 31.1

[39] Yang Y, Choi S H and Lu W 2013 Oxide heterostructureresistive memory Nano Lett. 13 2908–15

[40] Kozicki M N, Park M and Mitkova M 2005 Nanoscalememory elements based on solid-state electrolytes IEEETrans. Nanotechnol. 4 331–8

[41] Kwon D-H et al 2010 Atomic structure of conductingnanofilaments in TiO2 resistive switching memory Nat.Nanotechnol. 5 148–53

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