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Faculty of Engineering

Mid Exam

Fall 2015

Faculty Engineering

Department Electrical Communication & Electronic Systems

Module Code ECE 511,445

Module Title VLSI Design

Semester 58 - Fall 2015

Time Allowed 90 minutes

Total Mark 20

No. of Pages 3 including cover page

Material provided None

Equipment permitted Calculators

Additional Instructions None

No books, paper or electronic devices are permitted to be brought into the examination

room other than those specified above. Answers in Arabic will be disregarded and will

not be graded.

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Faculty of Engineering

Mid Exam

Fall 2015

Module Title : Very Large Scale Integrated Systems

Module Code : ECE 511,445

Semester : 58

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Question 1 (7 marks)

Design a behavioral abstract of the Baud Rate Generator (BRG), shown in Figure 1, of

the USART of the AVR Microcontroller, where T is sequentially executed, and

represents a generated frequency that value is equal to CLK / 2A. The BGR output

(CLKO) is concurrently executed and its value is determined based on the input S, as

described in Table 1. The reset input (RST) is asynchronous active low.

Question 2 (7 marks)

Design a synchronous active high positive edge triggered Transmit/Receive Register

(TX_RX), depicted in Figure 2, of the USART of the AVR Microcontroller. The

INOUT Ports ( D, TXF, RXF) are initially cleared, and they are also cleared under the

reset condition. Then they are determined based on the truth table shown in Table 2,

where:

i. For Case TX, the 12-bit TR inout port is sent serially, every +VE edge trigger of

the clock, via the inout Port D, starting with sending the Least Significant Bit

(LSB). After sending the 12 bits of the TR, the TXF flag should get high for one

clock cycle then it gets low again.

ii. For Case RX, the bit received at the inout Port D should be stored in a location

of the 12-bit TR inout, every +VE edge trigger of the clock, starting with storing

in its LSB. After filling the TR port, the RXF flag should get high for one clock

cycle then it gets low again.

S CLKO

0 T

1 CLK

OTHERS OPEN

Circuit

Fig. 1

1

Table 1

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Module Title : Very Large Scale Integrated Systems

Module Code : ECE 511,445

Semester : 58

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Hint: Checking TX and RX is done before checking TXF or RXF

Question 3 (6 marks)

Design the hierarchical block diagram (TOP), shown in Figure 3, that represents a

part of the AVR USART, implemented on an FPGA. The input GRS supports all reset

signals in the system.

TX RX TXF RXF D

1 0 0 DC Case TX

0 1 DC 0 Case RX

Table 2

Fig. 3

Fig. 2