Mid Frequency Decoupling Using Embedded Decoupling CapacitorsPrathap Muthana, Madhavan Swaminathan, Ege Engin, P. Markondeya Raj*, Rao Tummala

School of Electrical and Computer Engineering, 777, Atlantic Drive*School of Material Science and Engineering

Georgia Institute of TechnologyAtlanta

prathap@ece.gatech.edu,madhavan.swaminathan@ece.gatech.edu,engin@ece.gatech.edu,raj@ece.gatech.edu,rtummala@ece.gatech.edu

Abstract Surface Mount Technology (SMT) decoupling capacitors fail to provide decoupling above 100MHz. Thispaper presents the use of embedded thin film capacitors to provide decoupling in the mid frequency range from100MHz to 2GHz. On-chip capacitance provides decoupling above 2GHz. The effect of chip, package and boardcapacitors on the performance of digital systems is analyzed taking into account the parasitic effects of power/groundplanes, vias and solder balls. A synthesis and selection methodology for embedded package capacitors is also presented.Introduction The Intemational Roadmap for Semiconductors (ITRS) has projected an increase in the powerconsumption of microprocessors for future technology nodes [1]. For chips with a feature size of 90nm, supply voltageof 1.2V and chip size of 140mm2, the power dissipation is expected to be 84W. Table I shows a variation of differentmicroprocessor parameters for cost performance applications for the 90, 65 and 45nm nodes. The power deliverynetwork (PDN) provides the power supply to the processor. If improperly designed this network could be a majorsource of noise, such as ground bounce and electromagnetic interference (EMI) [2]. A methodology for designing agood PDN is to define a target impedance for the network that should be met over a broad frequency band [3]. Thisparameter can be computed by assuming a 5% allowable ripple in the voltage supply and a 50% switching current inthe rise and fall time of the processor clock [2]. Target impedance can be calculated as

z Vddx0.05, 1g Ix50%

where Vdd is the core voltage of the processor and I is the current drawn by the microprocessor from the PDN. Thetarget impedance listing for the 90, 65 and 45nm technology nodes is listed in Table 1. The current can be calculatedfrom the power and voltage as

P=VddI. (2)

Table 1: Target impedance through technology nodesYear Feature size (nm) Power (W) Vdd (V) Current (A) Target Impedance (mQ)2004 90 84 1.2 70 1.72007 65 103.6 0.9 115.11 0.7812010 45 119 0.6 198.33 0.302

As the processor is powered through the board and the package, the design of the PDN in both these levels is extremelyimportant. Decoupling capacitors play a very important role in the PDN as they act as charge providers for theswitching circuits. The target impedance has to be met over a broad frequency band; the low frequency, mid frequencyand high frequency capacitors need to be appropriately placed to meet this requirement. This paper will analyze theperformance ofmid frequency band decoupling capacitors in the PDN.SMT capacitors provide good decoupling up to around 100MHz. Figure 1 shows the response of 3 SMT capacitorsplaced at a port of reference (solid line) in a 10cm by 10cm plane. The response of the same capacitors placed 10mmaway from the port is also shown as dashed lines in Figure 1. It can be clearly seen that the performance of capacitorsis dependent on its placement on the plane. The sensitivity of capacitors performance to its placement is alsohighlighted in [4]. This trend is further magnified in a decoupling capacitor network. To highlight the limitations ofSMTs, a decoupling network was designed to meet the target impedance for the 65nm node. The response of thenetwork is shown in Figure 2. It can be seen that the inductance of the SMT capacitor network dominates the responseclose to 100 MHz. This problem cannot be addressed by using on-chip capacitors, since the amount of on-chipcapacitance that can be added is limited to the real estate on-chip. This is a limitation for on chip capacitors at lowfrequencies. An increase in the amount of decoupling capacitance will increase the cost and the size of the chip [5].Therefore, the low inductance combined with the low capacitance make on-chip capacitors viable only for highfrequency decoupling.For decoupling above 100MHz embedded capacitors in the package have shown good performance. Embeddingcapacitors in the package, positions them closer to the chip reducing the inductance associated with the capacitors.Reduced inductance coupled with high capacitance improves the decoupling performance. The design of an embeddedcapacitor network using the Packaging Research Center (PRC) technology will be highlighted in this paper. As shownin this paper, the embedded capacitor array shows decoupling performance degradation at around 2GHz due to itsinductive nature. For decoupling frequencies higher than 2GHz, on-chip capacitors would be required. For frequencieshigher than 2GHz, on-chip capacitors would be required. The amount of on-chip capacitance required that would

0-7803-9220-5/05/$20.002005 IEEE. 271

maintain the required target impedance is decided by the frequency response of the decoupling networks on thepackage and the board at 2GHz. The value of on-chip capacitance required to meet the target impedance after 2GHz forthe 65nm node was 50nF. The architecture of a possible capacitor array in the package is also described in this paper.The PDN is designed to meet the target impedance of 0.78m.Q for the 65nm technology node as listed in Table 1.

103 10.,Solid- Capacior at PortDashed- Capacitor 10mm from

12

101 10

P P

Fu10 - 10 Taret Impedance

10Capacitorl1 ,- Capacitor3

3 ~~~~~~~Capacitor 2

10' 10' 10O 109 102 10' 104 105 10a 107 10FrequencyN-z) Frequency(Hz)

Figure 1. SMT capacitor response Figure 2. Frequency response ofSMT network

Embedded Capacitors The details of the different capacitors that were used in the design of the capacitor decouplingnetworks are described in this section. The characterized capacitors were thin-film Barium Titanate (BaTiO3)capacitors (Figure 3), fabricated using a hydrothermal process. These capacitors were fabricated at PRC.

Nanograined ultra thin crystalline Barium Titanate thin filmswere synthesized on laminated copper foils using the lowcost low temnerature (<1iO°C) hvdrothermal Drocess.

klie T' ---- --- -- r " Hydrothermal synthesis of BaTiO3 involves treating Ti-iIunrnm coated copper clad laminates with Ba2+ ions in highlyXC1 2 alkaline solution at 95 C. With this method high K thin films

,qpr It IN can be integrated into organic packages using standardprinted wiring board processes such as lamination and

Figure3. Cross section ofBaTiO3 capacitor lithography.

The resultant 300nm thick films exhibited a dielectric constant close to 300, loss tangent less than 0.06 and acapacitance density greater than lpF/cm2 [6]. The size of the grains of the Barium Titanate varies from 60nm to 80nm.The top electrode is 2um thick copper and the bottom electrode is 12um copper with 500nm of Titanium. Thecharacterization of the capacitors was done by using the methodology described in [7]. The equations used forextracting the real and imaginary part of the capacitive structure is given by

Re(dut) - 25x (Re(S2 1)x (I - R(S2 1))- Im(S2 1)2)((i -Re(S2 1))2 + Im(S2 1)2

Im(dut) = 25x Imn(S21) (4)(l,-Re(S21))2 ±Im(S21)')

where Re(dut) and Im(dut) are the real and imaginary parts of the capacitive structure respectively. Re(S21) andIm(S21) are the real and imaginary parts of the measured S parameters between port 1 and port 2 of the device undertest (dut). The above mentioned measurement procedure requires a 2 port VNA station. Figure 4 shows the model tomeasurement correlation between two different sized capacitors. Capacitor 1 is a 2.1mm diameter circle and capacitor 2is a 1mm by 1mm square structure. Table 2 lists their properties.

Table 2. Parameters of capacitors in Figure 4Capacitance Inductance Resistance Resonant Frequency

Capacitor I 27.9nF 35pH 20imQ 161.05MHzCapacitor 2 9nF 38pH 16.9m.Q 272.14MHz

Capacitor Arrav The methodology used to design the capacitive network in the package is described in this section.Figure 5 shows the proposed package cross section with embedded capacitors layers. Figure 6 shows the embeddedcapacitor array layout in the package. The purpose of the network is to provide decoupling from 100MHz to 2GHz.Therefore, different sized capacitors constitute this array. The rationale for various sized capacitors is that thecapacitance associated with each of them is different, which translates into a different resonant frequency. The via pairsthat connect the capacitors to the power ground solder balls of the chip also influence the performance of the array. Byproper co-design of the vias and capacitors, the frequency band under consideration can be targeted. The capacitors areconnected in parallel with each other to meet the target impedance. The number of capacitors required of a particulartype is

Ztarget , (5)

ESRcap

272

where ESRCap is the series resistance ofan individual capacitor. The capacitor frequency response is very sensitive to itsposition in the package. It is important to be able to place these low ESL capacitors in the die shadow of the processor.Placement of these capacitors outside the die shadow will cause routing problems and change the predictedperformance ofa capacitor because of the increased spreading inductance.

10' .. I 21wDaslhed -- Mes..n. ot--MSolid-- Model

10' - I- M2

-o' EM-,D$<e9 B 2 GROUND

embedded Copshor2 "A100.

Simulation Models of System with Embedded Capacitors Fors ~ the frequency domain simulations in this paper, the board and

the package structures were modeled using the TransmissionMatrix Method [8]. The results in this paper have been presentedfor a single reference port in the structure. The port of reference(Port 1) is the chip looking into the package and the board. The

DISCRETE board is assumed to have a single plane layer. A 0.8mm thick,LAYERS 10cm by 10cm FR4 board of copper thickness 30um is assumed

for the board. The board is assumed to have a single plane layer.The package is assumed to be of size 4cm by 4cm as shown inFigure 5. The dielectric thickness and copper thickness of 9umeach is assumed as per PRC ground rules. The flip-chip bumpinductance and ball grid array (BGA) solder ball inductance

Figure 6. Package embedded capacitor array have been included in the model. The flip-chip bumps andsolder balls were modeled in FastHenry. For the chip to the

package interface, the flip-chip bump diameter of 50um was assumed and a pitch of213um was calculated based on [1].The inductance of a single bump pair was calculated to be 16.45pH. In the 65nm node, for 1024 bump pairs [1], thetotal effective inductance of the bumps is 1.6e-14H. Carrying out a similar analysis for the PWB technology, theinductance of a single supply BGA ball pair was calculated as 90.13pH. The diameter of the BGA ball and the pitchwas assumed as 500um. For 500 such pairs [1], the effective inductance is 1.80e-13H. Different SMT capacitors wereplaced on the board in the form of capacitor rings to meet the PDN target impedance for low frequency band tilllOOMfz. To reduce the effect of the plane spreading inductance, the lower ESL capacitors were placed closer to theBGA balls. Embedded capacitors within the package were used to target the frequency band from IOOMHz to 2GHz asdiscussed above and in [9]. For frequencies above 2GHz, on-chip capacitance has been used to meet the targetimpedance. Figure 7 shows the complete frequency response of the system by incorporating board, package and chipcapacitors. The improvement in the frequency response can be clearly seen by the use ofpackage embedded capacitors.To capture the simultaneous switching noise (SSN), a transient simulation of the system was carried out. A 115Acurrent excitation pulse train of rise and fall time of 25psec and period of 0.25nsec was injected to the system at Port Ito mimic a transient current by switching a 4GHz clock. The FFT of the pulse was multiplied by the frequency domainZ parameters of the system. The IFFT was taken of the resultant product to get the transient response and is shown inFigures 9 and 10 for two cases. Case 1 is the response of the system with board and on-chip decoupling capacitors andcase 2 is the response with the board, package and chip capacitors. The effect of the decoupling capacitors can beclearly seen from the system response in each case. There is a 3 fold improvement in the SSN, when embeddedcapacitors are used in the system with on-chip and SMTs. The time domain simulations clearly show the benefit ofembedded capacitors in the system. The total capacitance of the package capacitors is 2.163uF. The area occupied bythe embedded capacitors in the package is approximately the area of the processor die shadow (i.e., 140mm2). Incomparison, the real estate occupied by the SMTs on the board is approximately 452mm2.Conclusion Frequency and time domain simulations of a digital system have been performed to show the effect of thedecoupling capacitors on the board, package and the chip. A 3 fold improvement in performance of the system PDN byusing embedded capacitors over SMTs is highlighted in the time domain. A capacitor synthesis methodology has alsobeen presented for the design of decoupling networks in the package.References[1] 2003 International Roadmap for Semiconductors (ITRS). http://public.itrs.net.[2] Sungiun Chun, "Methodologies for Modeling Simultaneous Switching Noise in Multi-Layered Packages andBoards", PhD Dissertation, Georgia Institute ofTechnology, April 2002.

273

[3] Larry Smith et al, "Power Distribution System Design Methodology and Capacitor Selection for Modem CMOSTechnology", IEEE Transactions on Advanced Packaging, Vol. 22, No. 3, August 1999[4] Steve Weir, "Does Position Matter? Locating Bypass Capacitors for Effective Power Distribution" TeraSpeedConsulting Group.[5] JongHoon Kim et al, "Separated Role of On-chip and On-PCB Decoupling Capacitors for Reduction of RadiatedEmission on Printed Circuit Boards", EMC, 2001[6] Devarajan Balaraman et al, "BatiO3 films by low-temperature hydrothermal techniques for next generationpackaging applications", Journal of Electroceramics, 13, 95-100, 2004[7] Istvan Novak, Jason R.Miller, "Frequency Dependent characterization of Bulk and Ceramic Bypass Capacitors",Poster material for the 12'h Topical Meeting on Electrical Performance of Electronic Packaging, October 2003[8] Joong Ho Kim et al, "Modeling of Irregular Shaped Power Distribution Planes Using Transmission Matrix Method",IEEE Transactions on Advanced Packaging, Vol. 24, No. 3, August 2001[9] Prathap Muthana et al,"Design, Modeling and Characterization of Embedded Capacitor Networks for Mid-frequency Decoupling in Semiconductor Systems", EMC, August 2005

120 j ---v

110

90 1

80

70-

60-

50

20

10

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5Time(sec) x 10-9

Figure 7. Complete system frequency response with chip,package and board capacitors seen at Port 1.

Figure 9. Transient response ofthe structure at Port 1

with board and on-chip decoupling capacitors

Figure 8. Excitation current pulse train applied at Port 1.

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5Time(sec) 10°'

Figure 10. Transient response of the structure at Port 1

with board, package and chip decoupling capacitors.

274

S£

aa

£4

K2!C)