Microwind Tutorial
87
LAYOUT AND MICROWIND TUTORIAL DIGITAL ELECTRONICS II COURSE Eng. Waleed El - Halwagy Misr International University Faculty of Engineering Electronics and Communications Department Prepared By
Transcript of Microwind Tutorial
LAYOUT AND MICROWIND TUTORIALDIGITAL ELECTRONICS II COURSE
Eng. Waleed El - Halwagy
Misr International University
Faculty of Engineering
Electronics and Communications Department
Prepared By
As the CMOS is composed of NMOS and PMOS
we should at first present their properties and
construction.
NMOS, PMOS and CMOS
Construction
NMOS Properties
1. The Substrate : P – Type.
2. The Drain and Source : n+ diffusion.
3. The Select Area : p+ select.
4. The p + select is connected to ground.
5. The current flows from D to S.
6. The Drain voltage > The Source voltage
NMOS Construction
PMOS Properties
1. The Substrate : n – Type.
2. The Drain and Source : p+ diffusion.
3. The Select Area : n+ select.
4. The n + select is connected to VDD.
5. The current flows from S to D.
6. The Source voltage > The Drain voltage
PMOS Properties
CMOS Inverter ConstructionElevation View
CMOS Inverter ConstructionTop View
CMOS Inverter Construction3D View
Mask 1: N – well mask in the P – substrate
Fabrication Process of the CMOS
Inverter
Mask 1: N-well mask in the P-substrate
Mask 1: N-well mask in the P-substrate
Mask 1: N-well mask in the P-substrate
Mask 1: N-well mask in the P-substrate
Mask 2: Active Mask Creation ( n+ and p+ )
Fabrication Process of the CMOS
Inverter
Mask 2 : Active Mask Creation (n+ and p+)
Mask 2 : Active Mask Creation (n+ and p+)
Mask 2 : Active Mask Creation (n+ and p+)
Mask 2 : Active Mask Creation (n+ and p+)
Mask 3: Poly Silicon Mask Creation
Fabrication Process of the CMOS
Inverter
Mask 3 : Poly silicon Mask Creation
Mask 3 : Poly silicon Mask Creation
Mask 3 : Poly silicon Mask Creation
Mask 3 : Poly silicon Mask Creation
Mask 4: P+ region Mask Creation
Fabrication Process of the CMOS
Inverter
Mask 4 : P+ region mask creation
Mask 4 : P+ region mask creation
Mask 4 : P+ region mask creation
Mask 4 : P+ region mask creation
Mask 5: n+ region Mask Creation
Fabrication Process of the CMOS
Inverter
Mask 5 : n+ region mask creation
Mask 5 : n+ region mask creation
Mask 5 : n+ region mask creation
Mask 5 : n+ region mask creation
Mask 5 : n+ region mask creation
Mask 6: Contacts Mask Creation
Fabrication Process of the CMOS
Inverter
Mask 6 : Contact mask creation
Mask 6 : Contact mask creation
Mask 6 : Contact mask creation
Mask 6 : Contact mask creation
Mask 7: Metal Mask Creation
Fabrication Process of the CMOS
Inverter
Mask 7 : Metal mask creation
Mask 7 : Metal mask creation
Mask 7 : Metal mask creation
Mask 7 : Metal mask creation
It provides a set of guidelines for constructing the variousmasks needed in the patterning process.
Scalable Design Rules : all dimensions are given as afunction of λ
Micron Rules : all design rules are expressed in absolutedimensions
The Design Rules and Layout
The Design RulesIt provides a set of guidelines for constructing the various masks
needed in the patterning process
The Design Rules acts as the interface or even the contractbetween the circuit designer and the process engineer.
Circuit designers generally want tighter, smaller designs,which lead to higher performance and higher circuitdensity.
The process engineer on the other hand, wants areproducible and high – yield process.
Consequently, design rules are a compromise that attemptsto satisfy both sides.
Design rules consists of: Minimum width requirements.
Minimum spacing requirements.
Minimum Surface requirements.
Requirements between objects on the same or different layers.
The Design RulesScalable Design Rules : all dimensions are given as a function of λ
Even for the same minimum dimension, design rules tendto differ from company to company, and from processto process. This makes porting an existing designbetween different processes a time consuming task.
To address this issue we can use the scalable designrules, which defines all the design rules as a function ofa single parameter “λ”.
Scaling of the minimum dimension is accomplished bysimply changing the value of “λ”. This results in a linearscaling of all dimensions.
For a given process, λ is set to a specific value and alldesign dimensions are consequently translated intoabsolute numbers.
Minimum Feature size = 2 λ
The Design Rules Disadvantages of the Scalable design rules approach
Linear scaling is only possible over a limited range ofdimensions (for example between 0.25 μm and 0.18 μm).When scaling over large ranges, the relations betweendifferent layers tend to vary in a non-linear way that cannot be converted by the linear scaling rules.
Scalable design rules are conservative, they represent across section over different technologies, and they mustrepresent the worst case rules for the whole set. This resultsin over dimensioned and less dense designs.
For these and other reasons, scalable design rulesnormally are avoided by industry. (while not entirelyaccurate, the lambda rules are still useful to estimate theimpact of a technology scale on the design area).
The Design Rules Micron Rules: all design rules are expressed in absolute dimensions
As circuit density is a prime goal in industrial
designs, most semiconductor companies tend to use
the micron rules, which express all design rules in
absolute dimensions and thus can exploit the
features of a given process to a maximum degree.
Scaling and porting designs between technologies
under these rules is more demanding and has to be
performed either manually or by using advanced
CAD tools.
What is a Layout ?
A layout consists of a combination of
polygons, each of which is attached
to a certain layer. The functionality
of the circuit is determined by the
choice of the layers, as well as the
interplay between objects on
different layers.
A transistor
A MOS transistor is formed by the
cross section of the diffusion layer
and the poly silicon layer.
L
W
The Objective
Is to design the minimum size inverter in the 0.18 μm
technology and develop its seven masks.
The technology is specified by its minimum line
width (minimum feature size) which is usually
taken as the channel length of the transistor and
it is denoted by 2λ
Design using minimum sized NMOS and take the
W PMOS = 3 WNMOS and take the channel length
of both transistors as 2λ
DESIGN AN 0.18 μm technology
CMOS INVERTER ( 2 λ = 0.18 μm )
First : Select the Design Technology
from the Microwind
To get the Design Rules of the chosen
technology
First : The minimum sized NMOS Transistor
Design
First: Design the minimum sized NMOS
transistor.
What do we need to construct an NMOS transistor ?
P – substrate
Poly silicon for the gate.
n+ diffusion regions for the drain and source.
P+ select region that is connected to ground.
Contacts to connect the active area with the metallayer.
Remark:
The Microwind assumes the Silicon ignot used infabrication is doped with Boron, that is its a P-typesilicon ignot .
What are the design rules we need to
know to be able to construct the NMOS ?
The Minimum Poly Width = 2λ The Minimum Poly Area = 16 λ2
The Minimum extra Poly
surrounding the n diffusion = 3λ
The Minimum
n diffusion
Width = 4λ
The Minimum
n diffusion
Area = 16 λ2
The Minimum Contact
Width = 2λ
The Minimum spacing
between the contact
and the Poly = 3λ
The Minimum
extra n
diffusion
surrounding the
contact = 2λ
The Minimum extra n diffusion surrounding
the poly = 4λ
What are the design rules we need to
know to be able to construct the NMOS ?
The Minimum
p diffusion
Width = 4λ
The Minimum
p diffusion
Area = 16 λ2
The Minimum spacing
between contacts = 4λ
How to Check that the design Rules of
the layout are satisfied ?
Design Rule
Check ( DRC )
If any of these design rules are not
satisfied, the Microwind will signify it.
If any of these design rules are not
satisfied, the Microwind will signify it.
Now what is the minimum size and area of the
NMOS Transistor in the 0.18 μm technology ?
L : is the length of the poly silicon.
W : is the width of the n+ diffusion region.
From the design rules:
Minimum poly silicon length = 2 λ.
Minimum n+ diffusion width = 4 λ.
Taking into consideration that the minimum extra poly
surrounding the n+ diffusion is 3 λ.
Taking into consideration that the minimum extra n+
diffusion surrounding the poly is 4 λ.
Now what is the minimum size of the NMOS
Transistor in the 0.18 μm technology ?
The Minimum
extra Poly
surrounding the n
diffusion = 3λ
The Minimum
n diffusion
Width
W= 4λ
The Minimum
extra Poly
surrounding the
n diffusion = 3λ
The Minimum extra
n diffusion
surrounding the
poly = 4λ
The Minimum extra
n diffusion
surrounding the
poly = 4λ
The
Minimum
Poly Width
L = 2λ
L = 2 λ
W = 4 λ
Area = 10 λ x 10 λ
Now lets add the contacts.
The contacts – Design Rules:
Minimum contact width = 2λ
Minimum extra diffusion surrounding the contact = 2λ.
Minimum spacing between the poly and contact = 3λ.
As we can see that the last two design rules are not satisfied when LD = 4λand W = 4λ , so we have to expand them as follows :
L D = 4λ
L D = 3λ (poly – contact) + 2 λ (contact width)+ 2λ (contact – diff.) = 7 λ
L D = 4λ
2λ λλλ
2λ
λ
W = 4λ
W = 2λ (contact – diff) + 2 λ (contact width)+ 2λ (contact – diff.) = 6 λ
Now lets add the contacts.
Extra Poly
3λ
Poly
Width
L =2λ
Contact –
diff= 2λ
Contact –
diff= 2λ
Contact
width= 2λ
Poly –
contact
3λ
Contact
width
2λ
Contact
– diff
2λ
Extra Poly
3λPoly –
contact
3λ
Contact
width
2λ
Contact
– diff
2λ
L = 2λW = 6 λArea = 16 λ x 12 λ
W = 6λ
Optimizing the Aspect ratio and area
of the NMOS Transistor
From the above discussion we conclude that:
Minimum L = minimum poly width = 2λ.
Minimum W = 2 ( minimum contact - diff) + minimum contact width = 6 λ.
The Question now is can not we optimize this aspect ratio.
We can not decrease L because we can not implement a dimension that isless than 2λ.
But from the design rules, the minimum diffusion width is 4λ. We wereforced to implement it as 6λ due to the contact design rules constraints.
By a small trick we could let W = 4λ without altering the contactdesign rules constraints.
This can be accomplished by reducing the diffusion width to 4λ atthe poly silicon surface and widening it in the region surroundingthe contact.
Optimizing the Aspect ratio and area
of the NMOS Transistor
Extra Poly
3λ
Extra Poly
3λ
diffusion
width at
the poly
W = 4λ
Diffusion
width at
the
contact
6λ
L = 2λW = 4 λArea = 16 λ x 10 λ
L =2λ7λ 7λ
Adding the P-select region Taking into consideration the contact design rules restrictions
Area of p – select = 6λ x 6λ
Extra Poly
3λ
Contact
– diff
Contact
width
Extra Poly
3λ
Diffusion
width at
the poly
W = 4λ
Poly
Width
L =2λ
Poly –
contact
3λ
Contact
width
2λ
Contact
– diff
2λ
2λ
2λ
Contact
– diff
2λ
Contact
width
2λ
Poly –
contact
3λ
Contact
– diff
2λ
Contact
– diff
2λ
Contact
width
2λ
Contact –
Contact
4λ
L = 2λW = 4 λArea = 22 λ x 10 λ
2λ
2λ
2λ
Contact
– diff
Second : The PMOS Transistor Design
LPMOS = 2λ and W PMOS = 3 WNMOS
Now Design The PMOS with LPMOS = 2λand W PMOS = 3 WNMOS
What do we need to construct a PMOS transistor ?
N – well
Poly silicon for the gate.
p+ diffusion regions for the drain and source.
n+ select region that is connected to ground.
Contacts to connect the active area with the metal layer.
There are some additional design rules that we will need to know concerning the N-well before we proceed in our design of the PMOS.
The design rules concerning with the minimum width and area of the diffusion as well as the relation between the poly and the contacts with the diffusion are the same for both n-type and p-type.
Design Rules Concerning the N-well
The minimum extra
n-well surrounding
the p diffusion = 6 λ
The minimum extra
n-well surrounding
the p diffusion = 2 λ
The Minimum
n-well Width
= 10 λ
The Minimum
n-well Area
= 144 λ2
The Number of Contacts in the PMOS
As a rule: the more the number of contacts, the better the performance. This is because the resistance through which the current flows will decrease.
The following equation gives a relation between the diffusion width and the number of contacts.
W = 2 ( contact – diff.) + N ( contact width )
+ ( N – 1 ) ( contact – contact )
W
18 λ
Example : W = 18 λ
18 λ = 2 ( 2 λ )+ N ( 2 λ ) + ( N – 1 ) ( 4 λ ) ------- N = 3 contacts
Example : W = 17 λ
17 λ = 2 ( 2 λ )+ N ( 2 λ ) + ( N – 1 ) ( 4 λ ) -------- N = 2.83, that is N = 2 contacts
2 λ 2 λ 2 λ 2 λ 2 λ 2 λ 3 λ 3 λ
L
2 λ 2 λ 2 λ 6 λ
W
12 λ
2 λ
2 λ
2 λ
2 λ
2 λ4 λ
6 λ3 λ
3 λ
24 λ
30 λ
L = 2λW = 12 λArea = 30 λ x 24 λ
The CMOS is Constructed by connecting the NMOS
and PMOS transistors together
The CMOS is constructed by interconnecting both
the NMOS and PMOS
There are some additional design rule that must be taken inconsideration when interconnecting the NMOS and PMOS toconstruct the CMOS Inverter.
The minimum spacing between the n-well of the PMOS and the n+diffusion (drain) of the NMOS = 6 λ.
The metal used in the connections Minimum metal width = 6 λ
Minimum metal surface = 16 λ Minimum Spacing between metal layers = 4 λ
Minimum extra metal surrounding the contact = 2 λ
We need metal to
NMOS: Connect the p+ select with the source to ground
PMOS: Connect the n+ select with the source to V
Connect the NMOS and PMOS drains to the output.
Connect the poly to the input.
The minimum metal
spacing = 4 λ
The minimum extra
metal surrounding
the contact = 2 λ
The minimum spacing
between the n-well and
n-diffusion = 6 λ
NMOS : L = 2λ W = 4 λPMOS : L = 2λ W = 12 λCMOS Area = 58 λ x 24 λ
After we have finished the CMOS layout designand computed its dimensions, we are ready toextract the seven inverter masks to send them tothe Fab to be manufactured.
The Seven Masks Extraction
CMOS Inverter Layout
Mask 1 : N – well Mask
Mask 2 : Active Area Mask
Mask 3 : Poly Silicon Mask
Mask 4 : p + Region Mask
Mask 5 : n + Region Mask
Mask 6 : Contacts Mask
Mask 7 : Metal Mask
