Microtronix Firefly IV Module · PDF file 2018-11-28 · Firefly IV Datasheet Page 8...
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Microtronix
Firefly IV Module
USER MANUAL
Revision 1.02
4056 Meadowbrook Dr.
Unit 126 London, ON Canada N6L 1E3 www.microtronix.com
http://www.microtronix.com/
Page 2 of 19
This datasheet provides information regarding the Firefly IV
Configurable Processor Module. The following table shows the
document revision history.
Document Revision History
Date Description
July 2012 Initial Release – Version 1.0
August 2013 Updated mechanical drawing – Version 1.01
May 2014 Correct RS-232 - FPGA pin assignments
E-mail
Sales Information: [email protected]
Support Information: [email protected]
Website
General Website: http://www.microtronix.com
Nios Forum Website: http://www.niosforum.com
Phone Numbers
General: 519-690-0091
Fax: 519-690-0092
Path/Filename A path/filename
[SOPC Builder]$ A command that should be run from within the Cygwin Environment.
…sdk/ A file that is relative to the sdk directory.
Code Sample code.
Indicates that there is no break between the current line and the next line.
How to Contact Microtronix
Typographic Conventions
mailto:[email protected] mailto:[email protected] http://www.microtronix.com/ http://www.niosforum.com/
Firefly IV Datasheet
Page 3 of 19
Table of Contents
How to Contact Microtronix ............................................................................................................. 2
E-mail ........................................................................................................................................... 2
Website ........................................................................................................................................ 2
Phone Numbers ........................................................................................................................... 2
Typographic Conventions ................................................................................................................ 2
Features ........................................................................................................................................... 4
General Description ......................................................................................................................... 4
Reference Design ........................................................................................................................ 4
Board Components .......................................................................................................................... 5
Cyclone IV FPGA ......................................................................................................................... 5
Serial Configuration Device ......................................................................................................... 6
Flash ............................................................................................................................................ 7
SDRAM ........................................................................................................................................ 7
RS-232 ......................................................................................................................................... 7
Clock ............................................................................................................................................ 7
Module Connector ........................................................................................................................ 8
Module I/O Connector Pinnings ................................................................................................... 8
Module Board Mechanical Diagram ............................................................................................. 9
SOPC Builder Components ........................................................................................................... 10
Serial Configuration Device ....................................................................................................... 10
Flash .......................................................................................................................................... 10
SDRAM ...................................................................................................................................... 10
RS-232 ....................................................................................................................................... 11
External Support Circuitry .............................................................................................................. 12
Power Supply ............................................................................................................................. 12
JTAG .......................................................................................................................................... 13
Appendix A: Firefly IV Module Pins ............................................................................................... 14
Appendix B: Cyclone IV FPGA Pins .............................................................................................. 16
Firefly IV Datasheet
Page 4 of 19
Altera EP4CE30, EP4CE40, EP4CE55 or EP4CE75 484-pin Cyclone IV FPGA
Numonyx M25P64 Serial Configuration Device
64MB PC133 SDRAM
32MB Flash
4-wire RS-232 Transceiver
24 MHz oscillator
95 User I/O pins
User accessible PLL (2 input pins, 2 output pins)
JTAG port
Supports Nios II soft core processor and uClinux operating system
Supports self-reconfiguration of FPGA from logic in FPGA
Figure 1: Firefly IV EP4CE30 Module
The Firefly IV Configurable Processor Module is intended to provide a
drop-in processor system for embedded systems. It provides a
Cyclone IV FPGA for a Nios II soft-core processor as well as enough
SDRAM and Flash to run uClinux or other embedded operating system.
A large I/O count allows the module to be used in many diverse
applications. Communication and programming is provided through
Altera’s standard utilities.
Reference Design
The Microtronix Firefly IV Module ships with a reference design that
connects all of the devices on the module. It is a Nios II based system
that boots uClinux from the flash. Communication is provided through
the JTAG port and can be initiated using Altera’s nios2-terminal utility.
Features
General Description
Firefly IV Datasheet
Page 5 of 19
This section describes the various components and sub-circuits of the
Microtronix Firefly IV Configurable Processor Module. For each
component or circuit, this section explains: basic function, performance
limits and I/O requirements. Figure 2 shows the location of all the
Firefly IV components mentioned in this section.
Figure 2: Firefly IV Components
Cyclone IV FPGA
U2 is an Altera Cyclone IV FPGA: EP4CE30F484, EP4CE40F484,
EP4CE55F484 or EP4CE75F484 FPGA device in a 484 pin FineLine
BGA® package. Table 1 lists the Cyclone IV device features.
Table 1: Cyclone IV Device Features
EP4CE30 EP4CE40 EP4CE55 EP4CE75
LEs 28,848 39,600 55,856 75,408
M9K RAM Blocks 66 126 260 305
Total RAM Bits 608,256 1,161,216 2,396,160 2,810,880
Embedded multipliers 66 116 154 200
Board Components
Firefly IV Datasheet
Page 6 of 19
The Cyclone IV is configured on power-up by the M25P64 serial
configuration device (U4). It can also be configured through the JTAG
port using Altera’s FPGA programming tool.
See the Altera Cyclone IV literature page for Cyclone IV related
documentation at http://www.altera.com/literature/hb/cyclone-
iv/cyclone4-handbook.pdf.
Serial Configuration Device
U4 is a Numonyx M25P64 Serial Configuration Device which is
equivalent to the Altera EPCS64. This device is a serial flash device
with additional state machine logic for handshaking with the Active
Serial Programming feature of the Cyclone FPGA. After a Power-On or
Board Reset event, the Cyclone IV FPGA and Serial Configuration
Device work together to load a design from the flash memory of the
configuration device into Cyclone IV FPGA SRAM cells. Once
configuration is complete, the new core starts running.
Detailed information about the configuration device, as well as design
file sizes, can be found in Table 2 below.
Table 2: Serial Configuration Device
Max Serial Clock Frequency 75MHz
Power On Reset Time 10ms
Compression Performance 35-60%
Flash Memory Size (bits) 67,108,864
Max Uncompressed Design Size (4CE30) (bits) 9,534,304
Min area left for general use (4CE30) (bits) 57,574,560
Max Uncompressed Design
