Microstrip Patch Array Design - CST - Computer · PDF fileCST – COMPUTER SIMULATION...

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Microstrip Patch Array Design

Workflow Using CST MICROWAVE STUDIO®

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Introduction

Single element Array factor

design

optimization full model

feeding network

Antenna array

TBP optimization


1. Design a single patch element

Resonant frequency, (gain)

2. Postprocessing optimization of feeding

coefficients and spacing (Array Factor)

Gain, sidelobe level

3. Design and optimize a feeding network

S11, bandwidth, gain, sidelobe level

Design Procedure


1. Design a Single Patch Element

ABS Cover

RO4350

Aluminium

Stackup

Reference

plane

pW

pW

msW


Microstrip Width

msW


Create the Waveguide Port

Macros -> Solver -> Port ->

Calculate port extension coefficient


Symmetry Settings

Magnetic symmetry

in YZ plane

Open (add space)

boundaries are used

to estimate backlobes


Mesh Settings (1/2)

At least 2 - 4 cells per strip width


Mesh Settings (2/2)

2 cells per substrate height

At least 2 cells per air gap

ABS Cover

RO4350

Aluminium


Patch Width for Resonance at 5.5GHz

pW=19.5mm


Electric Field at 5.5GHz

Radiation

Travelling wave

Standing wave

ABS Radome

(not shown)


Single Patch Farfield Pattern

Discrete face port






• Gain, sidelobe level



Design Procedure


Array Factor

),(),(),( AFFF elementarray Array Pattern Multiplication

(for 5 patch antennas)

Assumptions: identical elements with no coupling.

= x


Farfield Pattern for Uniform Array

phi=90

phi=0

phi=45


Magnitudes for Optimal Array

mag1 mag2

mag1

mag2

mag2

mag2

mag3

mag3

Magnitudes will be optimized in order to minimize sidelobe level

Online demonstration


Optimize Feeding Coefficients (Optimal Array)

phi=90

phi=0

phi=45


Optimizer Settings (Optimal Array)

Not necessary to optimize mag3 (mag1, mag2 are relative)

The spacing parameter

was optimized for uniform array

Only TBP results

are evaluated


Template Based Postproc. Settings


Arbitrary Array Distribution

No ENTER there

File could contain variables

from CST MWS Parameter List

One TAB there


Array Factor Approach Validation (Optimal Array)


Array Wizard Macro

Construct finite array

Update Simultaneous

Excitation

Setup array factor

Combine results

(no Sim.Ex.)

Online demonstration


Array Construction with Array Wizard






Gain, sidelobe level



Design Procedure


Farfield – Effects of Housing


Include ABS Cover


Effect of Housing on Farfield Pattern


Effect of Housing on Farfield Pattern

The actual housing effects

mainly the back radiation


Feeding Network Design


Compute 16-port S-parameters

Discrete Face port


S-Parameter Symmetry Settings

16-port excitation reduced to 4-port


Design the Feeding Network Using Ideal

Transmission Lines


Optimize the Feeding Network in DS (Optimal Array)

16 parameters

to be optimized


Farfield + Feeding Network


Feeding Network (3D Model)

Curves Trace from Curve… This half is

mirrored


Symmetry Settings (1/2)

Magnetic

symmetry (YZ plane)

Open (add Space)


Symmetry Settings (2/2)

Is it possible to use

a symmetry in ZX plane ?

No symmetry in ZX plane:

The microstrip requires magnetic symmetry

however the patches require electric symmetry.


Mesh Settings (1/2) 2 cells per strip width


Mesh Settings (2/2)

Influences simulation speed

2 cells per substrate height


Initial Feeding Network Results

3D optimization is necessary to include couplings

between the feed network and radiating elements.


Electric Field

Coupling between the line and the patch

Phase delay due

to couplings.

Full wave

3D optimization


Optimizer Settings (Uniform Array)

13 parameters

to be optimized

Very

effective

for 3D

optimization


Optimized S-Parameters (Uniform array)


Optimized Farfield Pattern (Uniform array)


Start with simple models and add complexity

Post processing optimization of farfield pattern

Array wizard macro for array construction or array

factor settings

3D EM/ Circuit co-simulation (feeding network)

Trust Region Framework optimizer for 3D optimization

GPU acceleration

Key Features for Antenna Array Design


Divide complex task into smaller ones.

Use best approach at each stage.

Optimize your device.

Shorten your development cycle.

Conclusion

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Thank you!

Any questions?

Microstrip Patch Array Design - CST - Computer · PDF fileCST – COMPUTER SIMULATION...

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