Microscale Thermal Engineering of Electronic Systemsweb.mit.edu/hmtl/www/papers/GOODSONpres.pdf ·...
Transcript of Microscale Thermal Engineering of Electronic Systemsweb.mit.edu/hmtl/www/papers/GOODSONpres.pdf ·...
Thermosciences DivisionMechanical Engineering Department
Stanford University
Ken Goodson
Microscale Thermal Engineering of Electronic Systems
Key Points
3. Microscale Technologies for Heat and Power Management
2. Nanothermal Devices for Information Technology
IBM
1. Self Heating of Transistors and Interconnects
15 µm
silicon
Solid-state EO
pump
IBM Zurich / Stanford
Microprocessor Thermal Challenges
Siemens
1 µm
ESDMetal 1 (AlCu)
W-plug
TiNThermaldamage
n+ Silicon Diffusion Region0.2 µm
Silicon Dioxide
Metal HeatingTexas Instruments
IBM
Novel Materials
Strained Silicon / Si Ge
Novel Geometries
UC Berkeley/AMD
NanotransistorsGate
Source Drain
Tbody
Thin Body SOI
Source Drain
Gate
SiO2
Si substrate
Classic Bulk FET
Lch
Gate
Strained-Si FET
DrainSource
Si substrate
Graded SiGe
Relaxed SiGe
Strained-Sichannel
GateSource Drain
Gate
Gate
Double-Gate SOI(Purdue, IBM)
FinFET(UC Berkeley, AMD, IBM)
Source
DrainTbody
Transistor Electrothermal Physics
IBM
225 nm
Material boundary with roughness η
electron
d
lattice wave
phononωh=E
λ
Λ
dopantatom phonon
intense electron-phonon
scattering
High ElectricField
Hot Electrons(Energy E)
Acoustic PhononsAcoustic Phonons
τ ~ 0.5psE < 50 meV
Optical PhononsOptical Phonons
τ ~ 10 ps
τ ~ 0.1psE > 50 meV
High ElectricField
Hot Electrons(Energy E)
Hot Electrons(Energy E)
Heat Transferto Package
Heat Transferto Package
Heat to Package
Acoustic PhononsAcoustic Phonons
τmeV
Optical PhononsOptical Phonons
τ ~
τ ~ 0.1psmeV
∆T In
crea
se (K
)
Power Q
’ (µW/µm
)
Channel Length L (nm)
Approximate Impact of DeviceScaling on Peak Phonon
Temperatures
Pop, Banerjee, Dutton, Goodson,Proc. IEDM 2001
field
Transistor Simulation Regime Map
Drif
t Diff
usio
n
BTE
Mom
ents
Mon
te C
arlo
& B
TE
Mon
te C
arlo
with
Qua
ntum
Mod
els
Stratto
n (1962)
Bloetekjaer (1970)
Baccarani (1985)
Rudan (1986)Jacoboni (1983)
Fischetti (1988)
Electrons Full
Qua
ntum
Nanotransistor Regime
~1 nm~5 nmλ
~100 nm~5 nmMFP
phononselectrons
Datta,
Lundstrom (1995)In progress
Latti
ce
Isothermal
Atomistic
Diffusion
BTE or Monte Carlo
BTE withWave models
much work
Wachutka
(1994) Shur (1990)
Apanovich (1995)
Sverdrup, Ju,
Goodson (2000)
Lai, Majumdar
(1995) Research needs for the future
Electron Drift& PhononGenerationat 40kV/cm
• Monte Carlo, 300 electrons at 300 K• Electric Field starts at 0.5 ps• Eavg jumps from 39 meV to 290 meV
Thesis work ofEric Pop, 2003
Phonon Emission
Interconnect Thermal Management
Temperature Contour Plot (50 nm technology node)
209 °C209 °CGlobal WiresGlobal Wires
The temperature rise in interconnects is small now, but compounding trends in the ITRS roadmap lead to a tremendous increase at the 70 nm node beyond
low-k dielectric materialsincreasing current densities and aspect ratiosincreasing number of interconnect layers
0 2 4 6 8 10
120
140
160
180
200
220
Tem
pera
ture
[o C]
Distance from Substrate [µm]
35 nm
50 nm
70 nm
100 nm
130 nm
180 nm
Student: Sungjun Im. Sponsor – MARCO 7.1
ILD
ILDMETMET
2 Nkdd j~ ηρPeak ∆T
Tem
pera
ture
Ris
e (o C
)
0
100
50
IBM Zurich: Vettiger, Binnig Stanford: King, Kenny, Goodson.See King et al., Applied Physics Letters 78, 1300 (2001)
Stanford University Micro- and NanoMechanicsZurich Research Laboratory
Nanoscale Thermal Data Storage
Ibias
Data Reading
“0”∆T ~ 5 K
Ibias
“1”∆T reduced
Ibias
Data Writing
∆T ~ 300 K
Cantilever Array100 nm
Microrocessor Thermal Management
Microprocessor heat sinks are 3000 times larger and heavier than the chip
Power Delivery~1 cm3
ASICs~1 cm3
Heat Sinks,Heat Pipes,Vapor Chambers
~ 102 cm3
~10-1 cm3
RAM~10-1 cm3
Video~10-1 cm3
They crowd away power delivery components, ASICs, RAM, and Video
HOTSPOTS
Interdisciplinary Grand Challenge:Integrated Power Delivery & Heat RemovalGroups of Goodson, Kenny, Santiago, Saraswat, Stanford Mechanical Engineering
Groups of Thompson & Troxel, MIT Materials and Electrical Engineering
Thermofluidic Module with Solid-State Pump (Sponsors: Intel & DARPA)
Thermofluidic Mixed-Signal Power Module (Sponsors: SRC/MARCO & DARPA)
Mixed Signal Chip
Fluidic I/OPhotonic I/O RF
Integrated MEMSSensing
ElectricalConnections
Fluidic Cooling
Mixed Signal Chip
Fluidic I/OPhotonic I/O RF
Integrated MEMSSensing
ElectricalConnections
Fluidic Cooling
Fluid
Mixed Signal Chip
ElectricalConnections
Integrated EOPump/controller
targeted, on-demandmicrochannel cooling
Free I/OSurface
ElectroOsmotic Microchannel Cooler Sponsors: DARPA, Intel, AMD, Apple. Trans CPMT (2002). Best Paper SemiTherm 2001
Heat Rejector
Micro Heat Sink
2002: Apple Dual Processor Demo2001: 30 W Demo, 1 cm2 (Intel)2002: 100 W Demo, 1 cm2 (Intel)
2003: AMD Demo2002: 150 W Demo, 4 cm2 (Intel)
2002: Laptop Demo
EO Pump
ElectroOsmotic Pump
Microchannel Heat Sink
Stanford/Intel 100 W DemoEO Pump Flowrate ~ 20 ml/min
PIs: Goodson, Santiago, Kenny, Stanford ME
+ +++++
Silicondioxide
wall
Chargedouble-layer Charge Double
Layer
+ -High-PressureLiquid Pumping
~ 50 nm
Pyrex seal
ChannelsIn silicon
Si chip
Thermalattach
ElectroOsmotic Pumps With groups of Santiago and Kenny, Stanford Mechanical EngineeringSponsor: SRC/MARCO, DARPA
1 cm1 cm
Vd
p 2max32εζ
=∆
µ−
−µεζ
=)ra(
dxdpE)r(u
22
lVAQ
µεζ
=max•Very high volume to flowrate ratio
•Stanford pump performance (Feb 2002)
Pmax ~ 2 atm, Qmax ~ 40 ml/min, Vol. ~ 2 cm3
EOF
+ + + +++ ++ ++ + +++ ++
Glass or fused-silica capillary wall
Charge double-layer
Deprotonated silanolgroups
+ -
Idealized pore channel:
Free-standing pump
• Founded in 2001 by Stanford Profs. Ken Goodson, Tom Kenny, Juan Santiago, Mechanical Engineering
• 24 employees (Feb 2003) with engineering expertise including chemical, mechanical, packaging, thermal, & fluidic specialties
• Experienced management and directors drawn from Intel, Dell, Corning, Silicon Light Machines.
• Focussing on reliability demonstration, product implementation, collaboration with computer manufacturers
2370 CharlestonMountain View, CA 94043
www.cooligy.com
Cooligy develops thermal management components based on electro-osmotic pumps and novel microscale heat exchangers
Heat Rejector
Micro Heat Sink EO Pump
Concluding Remarks• The next decade of IC research & development will bring
solutions to “secondary” challenges associated with Moore’s Law, such as power delivery, heat removal, and package integration.
• IC thermal management problems will have lengthscalesspanning six orders of magnitude, from 10 nm in nanotransistors to more than 10 cm at the package level.
• Novel materials and geometries are increasing micro/nanoscale on-chip thermal resistances, leading to hotspots in metallization and interconnects.
• Circuit design focuses computation on the chip, yielding mm-scale hotspots that dramatically increase the thermal resistance from the chip to the package.
Alumni (1999-2002)Prof. Mehdi Asheghi Carnegie Mellon University (ME)Prof. Dan Fletcher UC Berkeley (Bioengineering)Prof. Bill King Georgia Tech (ME)Prof. Katsuo Kurabayashi University of Michigan (ME)Prof. Sungtaek Ju UCLA (ME) – with IBM until Fall 2003Prof. Kaustav Banerjee UC Santa Barbara (EE)Dr. Uma Srinivasan XeroxDr. Per Sverdrup Intel Dr. Peng Zhou CooligyDr. Maxat Touzelbaev AMD
Goodson Microscale Heat Transfer GroupThermosciences Division, Mechanical Engineering Department, Stanford
Current Students and Post-Docs (AY 2002/2003)Dachen Chu (Physics) Monikka Mann (ME) Xuejiao Hu (ME) Sanjiv Sinha (ME)Sungjun Im (Materials Science) Evelyn Wang (ME)Kevin Ness (ME) Ankur Jain (ME)Jae-Mo Koo (ME)Yue Liang (ME) Dr. Linan JiangAngie McConnell (ME) Dr. Abdullahel BariEric Pop (Electrical Engineering) Dr. Samuel Graham (Visitor from SNL)