Microprocessor & interfacing

Lecture 5

OUTLINE

• Instruction Cycle

• Instruction Format

• Instruction Set – Data Transfer

– Aritmatic and Logic

– Branch

Instruction Cycle

– Fetch take the instructions from memory to processor

– Decode to understand the meaning of binary code into micro-instructions

– Execute run the micro-instructions

Fetch Decode Execute

• The most difficult process is decode!!

• Some Definitions: – Program susunan instruksi (user)

– Instruksi bagian terkecil dari program (user)

– Mikroprogram susunan pekerjaan yang diperintahkan Control System

– Mikroinstruksi pekerjaan yang diperintahkan Control System

Instruction Format

– Op-code 8 bit

+

– Operand (data,register,dll)

– MOV AX,BX 89 (opcode) D8 (operand)

Opcode

• Selects the operation (addition, subtraction, etc.,) performed by the microprocessor. – either 1 or 2 bytes long for most instructions

• the general form of the first opcode byte of many instructions. – first 6 bits of the first byte are the binary opcode

– remaining 2 bits indicate the direction (D) of the data flow, and indicate whether the data are a byte or a word (W)

Data Transfer

MOV Clock

Acc mem 10

Mem acc 10

R R 2

Mem R 8 + EA

R mem 9 + EA

Immed R 4

Immed mem 10 + EA

R seg R 2

Mem seg R 8 + EA

Seg R R 2

Seg R mem 9 + EA

MOV

1 0 0 0 1 0

D W

(5 bit) mode pengalamatan

Pemilihan register

Data byte/word ; 0=byte, 1=word

Arah transfer data, dari/ke register ; 0=dari, 1=ke

kode operasi (operation code)

op code mod reg R/Mlow displacement high displacement

or

direct address

low byte

direct address

high byte

byte 1 byte 2 byte 3 byte 4

1. Reg/Mem to/from Reg 1000 10dw modregr/m disp (if

exist)

2. Immediate to

Register

1011 wreg Data data (w=1)

3. Memory to

Accumulator

1010 000w addr-low addr-high

4. Accumulator to

Memory

1010 001w addr-low addr-high

Register Code

code

10

code

01

11

00

SS

Seg. Reg.

CS

DS

ES

101

110

W=0 W=1

001

010

100

111

BP

SI

Register

000

011

SP

DI

AX

BX

CX

DX

AH

BH

CH

DH

AL

BL

CL

DL

MOD and R/M

d8 : 8 - bit displacement, d16 : 16 - bit displacement

[BX] + [DI] [BX] + [DI] + d8 [BX] + [DI] + d16

00 01 MOD

R/M

[BX] + [SI] [BX] + [SI] + d8 [BX] + [SI] + d16000

10

[BP] + [SI] [BP] + [SI] + d8 [BP] + [SI] + d16

[BP] + [DI] [BP] + [DI] + d8 [BP] + [DI] + d16

[BP] + d16

[BX] [BX] + d8 [BX] + d16

[SI] [SI] + d8 [SI] + d16

[DI] [DI] + d8 [DI] + d16

DH

101

110

111

001

010

011

100

d16

direct address[BP] + d8 SI

DI

W=0 W=1

AL

CL

DL

BL

AH

CH

11

MEMORY MODE REGISTER MODE

BH

AX

CX

DX

BX

SP

BP

PUSH

– Asumption : SP=1236, AX=24B6, DI=85C2, DX=5F93 Look at the Stack Memory:

PUSH AX PUSH DI PUSH DX

PUSH DX PUSH DI PUSH AX start

SP:1236

24 24 24 SP:1235

B6 B6 B6 SP:1234

85 85 SP:1233

C2 C2 SP:1232

5F SP:1231

93 SP:1230

1. Register 0101 0reg

2. Segment Register 000reg110

POP

– Assume : SP=1230, Pay attention on Stack Memory:

POP AX POP DX POP BX

POP BX POP DX POP AX START

SP:1236

24 24 24 SP:1235

B6 B6 B6 SP:1234

85 85 SP:1233

C2 C2 SP:1232

5F SP:1231

93 SP:1230

1. Register 0101 1reg

2. Segment Register 000reg111

Aritmatic and Logic

ADD/SUB Clock DIV Clock

R R 3 8 bit reg 80 sd 90

Mem R 9 + EA 16 bit reg 144 sd 162

R mem 16 + EA 8 bit mem (86 sd 96)+EA

Immed R 4 16 bit mem (150 sd 168)+EA

Immed mem 17 + EA

MUL Clock Shift & Rotate Clock

8 bit reg 70 sd 77 Single bit reg 2

16 bit reg 118 sd 133 Var bit reg 8 + 4/bit

8 bit mem (76 sd 83)+EA Single bit mem 15 + EA

16 bit mem (124 sd 139)+EA Var bit mem 20+EA+4/bit

1. Reg/Mem with

Register

0000 00dw modregr/m

2. Immediate to

Reg/Mem

1000 00sw mod000r/m data data(sw=01)

3. Immediate to

AX/AL

0000 010w Data data (w=1)

ADD - Add

Program Control

JMP Clock Clock

short 15 JCXZ 6 (no branch)

18 (branch)

Intrasegment direct 15 J condition 4 (no branch)

16 (branch)

Intersegment direct 15

Intrasegment using reg mode

11

Intrasegment indirect 18 + EA

Intersegment indirect 24 + EA

JMP - Unconditional Jump

Direct w/in Segment

Short

1110 1011 Disp

JZ - Jump on Zero

JZ - Jump on Zero 0111 0100 Disp

Instruksi Clock Instruksi Clock

INC/DEC reg8 3 MOV reg,reg 2

INC/DEC data 23+EA MOV mem,reg 13+EA

INC/DEC reg16 3 MOV reg,mem 12+EA

LOGIC reg,reg 3 MOV mem,imm

14+EA

LOGIC mem,reg

24+EA MOV reg,imm 4

LOGIC reg,mem

13+EA MOV mem,acc 14

MOV seg,reg 2 MOV acc,mem 14

MOV reg,seg 2 MOV seg,mem 12+EA

MOV mme,seg 13+EA

Effective Address

Addressing Mode Clock

Direct 6

Register indirect 5

Register relative 9

Based indexed

(BP)+(DI) or (BX)+(SI) 7

(BP)+(SI) or (BX)+(DI) 8

Based indexed relative

(BP)+(DI)+disp or (BX)+(SI)+disp 11

(BP)+(SI)+disp or (BX)+(DI)+disp 12

Examples

Clock Calculation

Address Mnemonic Assembly Clock

CS:0100 B8 34 12 MOV AX,1234 4

CS:0103 35 34 12 XOR AX,1234 4

CS:0106 74 02 JZ 010A 16 (branch)

CS:0108 B3 12 MOV BL,12 - (skiped)

CS:010A 8A 0E 34 12 MOV CL,[1234] 8 + 6(EA)

CS:010E 88 16 34 12 MOV [1234],DL 9 + 6(EA)

Total 53

OPCODE

Try it!