1

MICROELETTRONICA

DC and transient responses

Lezione 3

2

OutlineOutline• DC Response• Logic Levels and Noise Margins• Transient Response• Delay Estimation

3

DC Response• DC Response: Vout vs. Vin for a gate• Ex: Inverter

– When Vin = 0 -> Vout = VDD

– When Vin = VDD -> Vout = 0– In between, Vout depends on

transistor size and current– It’ clear that we must settle

Idsn = |Idsp|– We could solve equations– But graphical solution gives more insight

4

Beta RatioIf βp / βn 1, switching point will move from VDD/2Called skewed gateOther gates: collapse into equivalent inverter

Vout

0

Vin

VDD

VDD

0.51

2

10p

n

0.1p

n

5

Noise MarginsHow much noise can a gate input see before it doesnot recognize the input?

IndeterminateRegion

NML

NMH

Input CharacteristicsOutput Characteristics

VOH

VDD

VOL

GND

VIH

VIL

Logical HighInput Range

Logical LowInput Range

Logical HighOutput Range

Logical LowOutput Range

6

Logic Levels

VDD

Vin

Vout

VOH

VDD

VOL

VIL VIHVtn

Unity Gain PointsSlope = -1

VDD-|Vtp|

p/n > 1

Vin Vout

0

To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic

7

Capacitance• Any two conductors separated by an

insulator have capacitance• Gate to channel capacitor is very important

– Creates channel charge necessary for operation• Source and drain have capacitance to body

– Across reverse-biased diodes– Called diffusion capacitance because it is

associated with source/drain diffusion

8

Gate Capacitance• Approximate channel as connected to

source• Cgs = oxWL/tox = CoxWL = CpermicronW• Cpermicron is typically about 2 fF/m

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.90)

polysilicongate

9

Diffusion Capacitance• Csb, Cdb

• Undesirable, called parasitic capacitance• Capacitance depends on area and perimeter

– Use small diffusion nodes– Comparable to Cg

for contacted diff– ½ Cg for uncontacted– Varies with process

10

Transient Response• DC analysis tells us Vout if Vin is constant• Transient analysis tells us Vout(t) if Vin(t)

changes– Requires solving differential equations

• Input is usually considered to be a step or ramp– From 0 to VDD or vice versa

11

Inverter Step ResponseEx: find step response of inverter driving load cap

0

0

( )( )

( )

(

(

)

)

DD

DD

loa

d

ou

i

d

t

o

n

ut sn

VV

u t t Vt t

V tV

ddt C

t

I t

0

22

0

2)

)( ( )

( DD DD t

DD

out

outout out D t

n

t

ds

D

I V

t t

V V V V

V V V VV

tV t V t

Vin(t) Vout(t)Cload

Idsn(t)

Vout(t)

Vin(t)

t0t

12

Operating Regions

Region nMOS pMOSA Cutoff LinearB Saturation LinearC Saturation SaturationD Linear SaturationE Linear Cutoff

CVout

0

Vin

VDD

VDD

A B

DE

Vtn VDD/2 VDD+Vtp

13

Delay Definitions• tpdr: rising propagation delay (maximum time)

– From input to rising output crossing VDD/2• tpdf: falling propagation delay (maximum time)

– From input to falling output crossing VDD/2• tpd: average propagation delay

– tpd = (tpdr + tpdf)/2• tr: rise time

– From output crossing 0.2 VDD to 0.8 VDD

• tf: fall time– From output crossing 0.8 VDD to 0.2 VDD

14

Delay Definitions• tcdr: rising contamination delay (minimum

time)– From input to rising output crossing VDD/2

• tcdf: falling contamination delay (minimum time)– From input to falling output crossing VDD/2

• tcd: average contamination delay– tpd = (tcdr + tcdf)/2

15

Simulated Inverter Delay• Solving differential equations by hand is too hard• SPICE simulator solves the equations numerically

– Uses more accurate I-V models too!• But simulations take time to write

(V)

0.0

0.5

1.0

1.5

2.0

t(s)0.0 200p 400p 600p 800p 1n

tpdf = 66ps tpdr = 83psVin Vout

16

Delay Estimation• We would like to be able to easily estimate delay

– Not as accurate as simulation– But easier to ask “What if?”

• The step response usually looks like a 1st order RC response with a decaying exponential.

• Use RC delay models to estimate delay– C = total capacitance on output node– Use effective resistance R– So that tpd = RC

• Characterize transistors by finding their effective R– Depends on average current as gate switches

17

RC Delay Models• Capacitance proportional to width• Use equivalent circuits for MOS transistors

– Ideal switch + capacitance and ON resistance– Unit nMOS has resistance R, capacitance C– Unit pMOS has resistance 2R, capacitance C

• Resistance inversely proportional to width

kgs

dg

s

d

kCkC

kCR/k

kgs

dg

s

d

kC

kC

kC

2R/k

18

Example: 3-input NAND• Sketch a 3-input NAND with transistor widths chosen to

achieve effective rise and fall resistances equal to a unit inverter (R).

19

Elmore Delay• ON transistors look like resistors• Pullup or pulldown network modeled as RC ladder• Elmore delay of RC ladder

nodes

1 1 1 2 2 1 2... ...

pd i to source ii

N N

t R C

RC R R C R R R C

R1 R2 R3 RN

C1 C2 C3 CN

20

Delay Components• Delay has two parts

– Parasitic delay• 6 or 7 RC• Independent of load

– Effort delay• 4h RC• Proportional to load capacitance

21

Contamination Delay• Best-case (contamination) delay can be substantially less

than propagation delay.• Ex: If both inputs fall simultaneously

6C

2C2

2

22

4hC

B

Ax

Y

22

Diffusion Capacitance• We assumed contacted diffusion on every s / d.• Good layout minimizes diffusion area• Ex: NAND3 layout shares one diffusion contact

– Reduces output capacitance by 2C– Merged uncontacted diffusion might help too

7C

3C

3C3

3

3

222

3C

2C2C

3C3C

IsolatedContactedDiffusionMerged

UncontactedDiffusion

SharedContactedDiffusion