Microcontrollers ElectroMagnetic Interferences (EMI) modeling and reduction

MOIGN Mélanie, LECA Jean-Pierre, FROIDEVAUX Nicolas

JACQUEMOD Gilles, BRAQUET Henri, LEDUC Yves

20/03/19

Summary

1 •  Introduction and motivations

2 •  EMI measurements and analysis

3 •  Building an EMI model

4 •  Results and guidelines to reduce EMI

•  Conclusion

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1. Introduction and motivations

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The ElectroMagnetic Compatibility

•  EMC: ability of an equipment to function satisfactorily in its EM environment without introducing intolerable EM disturbances to another environing equipment's.

•  EMS (EM Susceptibility) aspect: increase the immunity of the victim. •  EMI (EM Interferences) aspect: reduce the emissions of the source. •  Coupling aspect: improve coupling path.

SOURCE VICTIM Coupling path

  Lightning   Electrostatic Discharges (ESD)   Fast Transient Bursts (FTB)   Hertzians emitters   Motors   …

  Human   Radio/TV receptors   Computers   Analogic sensors   …

  Conductive coupling   Radiative coupling

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Conducted and radiated EMC issues 5

Motivations •  EMI: Disturbances that affect an electrical circuit due to either EM

conduction or EM radiation emitted from an external source.

• Why EMI of ICs are problematic? •  ICs are the source of EMI in applications •  ICs are embedded in almost all electronic devices •  EMI are generally increasing with the increase of ICs performances •  Devices have to pass international EMI standards to be commercialized and

ensure a maximum safety

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Minor (Annoyance, delays)

Medium (Revenue, Data loss)

Major (Injuries, death)

AM/FM/TV interferences

Aircraft navigation tool interferences

Cell Phones interferences

Bluetooth/Wi-Fi interferences Automated monetary transactions

Critical communications interferences Aircraft landing system interruption

Pacemakers

Improper deployment of airbags

Basic EMI mechanisms •  Noise generation due to switching currents by:

• Memories access • Clock-driven block • IO switching activity • …

•  Current peaks converted into Power & Ground voltage drops (“Simultaneous Switching Noise” or “SSN”) due to the wire parasitic.

•  Common mode radiation

•  Power & Ground current loops •  Differential mode radiation

•  Unintentional radiation by antennas (package, interconnections…)

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DIE

Leadframe

Current loop

Voltage drop

Bonding wire

Voltage drop

STM32 microcontroller as case study •  A µC is a standalone electronic system which integrates on a single

integrated circuit: •  A processor core •  Memories (RAM, ROM, Flash) •  Analogue IPs •  IOs

•  Advantages: •  Low cost •  Low size

•  Drawbacks: •  CPU frequency slower than microprocessors

•  They are often the neuralgic center of embedded systems

importance of the EMC

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•  Define an EMI strategy during the design stages by: •  The use of predictive EMI models to show weaknesses. •  Layout/Design rules implementations to reduce the emission levels

EMI Philosophy 9

Back-end

Specifications

Design

Front-end Compliance

EMI simulations compliance

NO GO

GO

CAD Tools ols ls

Design rules

Back-end BackSpecifications

Design

Front-end Version n°

EMI measurements compliance

NO GO GO

Before : we were expected Now : we are planning

2. Microcontroller EMI Measurements & Analyzes

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IEC 61967-2 TEM-Cell measurements

•  Dedicated EMI Printed Circuit Board •  PCB IEC 61967-2 compliant

•  Help of a TEM-Cell as EMI receiver & Faraday cage •  Results visible on a spectrum analyzer

•  Comparison between different devices •  Knowing the emission levels

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TEM–Cell Measurements •  Comparison Flash/

RAM mode: •  CMOS 90 nm •  1MByte of Flash •  FCPU = 120MHz •  FSOFT_LOOP = 13.33MHz •  FSOFT_LOOP = 8.50MHz •  All peripherals ON •  No IO Switching

•  In this case, the Flash Memory is the main EMI contributor so no CPU modeling

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3. Building a microcontroller EMI model

ICEM model • Modeling methodology

•  Based on the ICEM model standard (IEC 62014-3), for “Integrated Circuits Emission Model”.

•  Goal: to predict EMI levels during the design stages & test different solutions

• Main blocks •  IA (Internal Activity) •  PDN (Power Distribution Network)

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PCB Model Package Model

PG Rails Model IA Model

Die Model

STM32 EMI model 15

•  PCB PDN and External Decoupling Capacitance model 1

•  Package PDN model •  Leadframe model •  Bonding model

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•  DIE PDN model •  Internal activity (Flash IP) model •  IO ring Power & Ground model

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•  TEM-Cell model 4

1. PCB PDN model •  PDN between the external supply and the µC external pins

• Obtained by computation

•  RLCK network •  Typical values @1GHz:

•  L=LTOP+LBOTTOM=18nH

•  R=RTOP+RBOTTOM=1Ω •  C=100nF (7 in //) •  K=0.5 •  LTRACK=ESL(DCAP)+LTRACE=5.5nH (7 in //)

•  RTRACK=ESR(DCAP)+RTRACE=100mΩ (7 in //)

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2. Package PDN model •  PDN between the external pins and the IO pads

•  Leadframes •  Bonding wire

• Obtained with Ansoft Q3D and HFSS or by computation •  RLCK network •  Typical values @1GHz:

•  L=LLEAD+LBOND=6nH •  R=RLEAD+RBOND=300mΩ •  C=100fF •  K=0.5

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3. Die PDN model •  PDN between the IO pads and the internal supplies • Wires inherent inductances and resistances

•  Supply rails tracking from the device gds2 •  Parasitics obtained by computation (no skin effect and mutual inductances) from

the rails geometry. •  RLC network •  Typical values @1GHz:

•  L=50pH (for 1IO) •  R=50mΩ (for 1IO) •  C=2.85pF (for IO) •  K=0.6

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3. Die PDN model •  IO PDN model between VDD and GND:

•  Equivalent to an RC filter •  Impedance formed by n IOs in parallel •  IOs not switching •  CIO=2.85pF •  CTOTAL=0.48nF (168 IOs in //)

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3. Die IA Flash memory & PDN model •  IA and PDN between VDD and GND

•  PDN extraction with Apache Totem •  IA extraction by Spice simulations •  Typical values:

•  IPEAK=330mA

•  TRISE=350ps => FEQU=1GHz

•  F=13.33MHz

•  C=0.15nF

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3. Die model •  VDD<1:7> and GND<1:3> are connected to the package model •  Pad ring representation

•  Flash memory Internal Activity •  Power & Ground rail model •  IO model

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4. TEM-Cell model •  EMI receiver • Obtained with an EM solver

•  Representation of the electric and magnetic coupling between IC and septum •  Valid up to 1GHz •  RLCK network

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EMI Modeling Flow

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4. Results and guidelines to reduce EMI

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Simulation results and correlation •  SPICE transient simulation: good correlation with measurements in

term of amplitude & frequency

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5. EMI reduction • With the help of the model, we can now test different solutions to

reduce the emissions •  Here, for example, with 1nF of internal capacitance added on the

Flash memory •  Simulation done before derivative product PG tape. •  Prediction: EMI reduction from 10dB to 20dB in simulation (pink curve versus blue

curve).

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5. EMI reduction •  Silicon result

•  EMI reduction from 10dB to 20dB well effective as predicted •  The model helped well to reduce the emissions •  So, such a predictive model will help to introduce more design/layout guidelines.

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EMI modeling conclusion

• Performances: • Good EMI prediction • Good EMI mechanisms representation • Comparison between devices possible • Possibility to see the parameters influence on EMI

• Limitation: • Number of software required • 1GHz limitation • Automatic flow to be implemented

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Thank you! Do you have some questions

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