Microcontroller Technologies for Smart...

Renesas Electronics America Inc.

© 2012 Renesas Electronics America Inc. All rights reserved.

Class ID: Class ID:

Microcontroller Technologies for Smart Society Ritesh Tyagi, Sr. Director MCU Marketing

1C02B

© 2012 Renesas Electronics America Inc. All rights reserved. 2

Sr. Director – Microcontroller Product Marketing

Product Marketing and Segment Marketing

Responsibilities for 8, 16 and 32-bit MCU families

MSEE and MBA from University of Allahabad, India

More than 15 years of experience in MCU/MPU products and applications

MCU product definition and marketing launch

Solution development for key segments like consumer, Medical industrial and communication

Design experience for consumer electronics

Mr. Ritesh Tyagi


Renesas Technology & Solution Portfolio


Smart Society Paradigm

“Soon the amount of data in the world will

QUADRUPLE every day” -IBM

Energy is limited

More THINGS connected to

the internet than PEOPLE

From sporadic to CONTINUOUS measurement

REALTIME is the new PRIME TIME

PRIVACY is the new

ATOMIC BOMB

INFORMATION OVERLOAD is an opportunity for

PATTERN RECOGNITION

Source: The conversation prism by Brian Solis

& LESS3


“Between now and 2020, the amount of digital information created and replicated in the world will grow to an almost inconceivable 35 trillion gigabytes, as all major forms of media -voice, TV, radio, print -complete the journey from analog to digital… This explosive growth means that by 2020, our Digital Universe will be 44 times as big as it was in 2009.” -IDC

Data is the Key

data is the NEW OIL


MIPS

0.01

0.1

1

10

100

1000

1980 1990 2000 2010 Year

2MHz

8-bit

16MHz

10MHz

16-bit

40MHz

80MHz

25MHz

16/32-bit

Dual-core

200MHz

32-bit

Trends of CPU Performance


0.01

0.1

1

10

1980 1990 2000 2010 Year

x8

x8

x8

MB

Trends of Embedded Memory Capacity


Renesas’ innovative Microcontroller Technologies

Process technology

Architecture (Performance and Power consumption)

Innovative integration

Summary & Q/A

By the end of this session you will be able to:

Understand the Renesas’ microcontroller technologies and

solutions driving the smart society concept

Agenda


Embedded Flash Technology Roadmap

Max. read

freq.

ES MP

2007 2008 2009 2010 2011 2012 2013 2014 2015 Memory

Structure

Te

ch.

Low power op.

Low voltage

NOR (Split-gate) 40MHz

130nm

NO

R

2016 2017

MONOS*

100MHz

90nm

MO

NO

S

120MHz

40nm

MO

NO

S

Large capacity

High speed

Unified flash

(RV40F) for RH850 &

RX600

100MHz

90nm

MO

NO

S

UX6LF (Former NECEL)

RC03F (Former Renesas Tech.)

Renesas MCUs are the first with 40 nm embedded flash!

* MONOS:

Metal Oxide

Nitride Oxide

Silicon

50MHz N

OR

130nm


World First 40nm Flash MCU

Leading Flash Process for Next Generation Automotive & Industrial

Transistor / mm2

Technology node 40 60 80 100

Previous generation 90nm

Other Option B 65nm

Other Option A 55nm

40nm

320MHz CPU

120MHz Flash

~ 8MByte

Lowest power

consumption


Firmly maintained the world’s No.1 MCU market share of 27% in CY2011

Dominant position in automotive MCU unchanged with the world’s No.1 share

No. 1 MCU Supplier in the World

2,150

2,147

1,055

454

574

740

61

1,052

233

764

150

783

369

512

16

782

274

431

6506

Renesas Infineon STMicro TI Fujitsu

M US$ CY2011

Auto- motive MCU

General- purpose

MCU *

Freescale Infineon Atmel STMicro Microchip TI Samsung Fujitsu NXP

WW MCU #1 27% share

WW Automotive MCU #1

42% share

8-bit MCU #1: 17% share 16-bit MCU #1: 27% share 32-bit MCU #1: 38% share

Deepened relationships with carmakers Collaborating in BCP

Source: IHS iSuppli, Annual 2011 Semiconductor Market Share *General-purpose MCU: MCUs for applications excluding automobiles


Microcontroller and Microprocessor Line-up

Wide Format LCDs Industrial & Automotive, 130nm

350µA/MHz, 1µA standby

44 DMIPS, True Low Power

165 DMIPS, FPU, DSC

1200 DMIPS, Performance

1200 DMIPS, Superscalar

500 DMIPS, Low Power

165 DMIPS, FPU, DSC

25 DMIPS, Low Power

10 DMIPS, Capacitive Touch

Industrial & Automotive, 150nm

190µA/MHz, 0.3µA standby

Industrial, 90nm

500µA/MHz, 1.6µA deep standby

Automotive & Industrial, 90nm



600µA/MHz, 1.5µA standby Automotive, 40nm

500µA/MHz, 35µA deep standby

Industrial, 40nm




2010 2012

32

-bit

8

/1

6-b

it






165 DMIPS, FPU, DSC




165 DMIPS, FPU, DSC

25 DMIPS, Low Power




Industrial, 90nm







Industrial, 40nm




2010 2012

32

-bit

8

/1

6-b

it

32-Bit High Performance, High Scalability & High Reliability


High-end, 32-bit CPU Roadmap

Succession of “V850 and SH” Architecture

V850E1 * 5-stage

V850E2 * 7-Stage * dual-issue

V850E2R +FPU

V850E2M +MPU

G3M +FPU(IEEE754-2008)

+Branch prediction, +SIMD, +Multi-Core

G3K * 5-stage

Good Performance and Low Power

E2S * 5-stage

High Performance and Low power

SH2A

SH2

SH1


RH850 Architecture (Example CPU Core and Pipeline)

Flash Memory

Capable

to Flash

120MHz

SRAM

Example RH850 CPU

5-STAGE PIPELINE

5 STAGES OF PIPELINE

F = FETCH INSTRUCTION

D = DECODE INSTRUCTION

E = EXECUTE INSTRUCTION

M = READ OR WRITE MEMORY

W = WRITE BACK TO REGISTER

Inst 128 bit path Instruction

Data 39 bit path

Operand

(Data)

HARVARD ARCHITECTURE

96 MHz CPU Core 2.x

DMIPS/MHz

32x 32bit

General

Purpose

Registers 32bit

Floating

Point Unit

(Optional)

32x32 +64 MAC,

64b Result

32 x 32 DIV or MULT, 32bit

or 64bit Result

Memory

Protect Unit

Interrupt

Control

On-Chip

Debug

HARVARD ARCHITECTURE

5-STAGE PIPELINE

F D E M W

TIC

K

F D

F

TIC

K

E

D

F

TIC

K

M

E

D

F

TIC

K

W

M

E

D

F

TIC

K

F

W

M

E

D

TIC

K

D

F

W

M

E

TIC

K

E

D

F

W

M

TIC

K

M

E

D

F

W

TIC

K

E

E

E

E

E

W

M

E

D

F

Achieves :

One Clock-Per-Instruction (CPI)

E

E Que 1

Que 2


RH850 Architecture… System Interface

Communication (CSI, CAN, SCI,LIN, I2C, Flex Ray)

Timers (TAUA, TAU J, OST, CMT)

Analog GPIO

System Control (DMA, E2P, ICU, LVD, RTC, WDG, CLKS)

Peripheral Busses to Spread Bandwidth Loading

Bus Bridge

DMAC (bus master)

RH850 BUFFER

128b INST

32b DATA

Bus Master

64 bits

Bus Bridge

32 bits

Internal Main Bus 1/ System interconnect

32 bits

RH850 MCU

SRAM,

120MHz Access

Flash Memory,

120MHz Access

Buffer PIPELINE 128b

instruction


Low Power

Platform

RH850: 40nm MCU Series for Vehicle Control

High Mid Low

240MHz Dual core w/ LS x2

240MHz Single core w/ LS

160MHz Single Core

320MHz Dual core w/ Lockstep I/O CPU

240MHz Dual core w/LS I/O processor

120MHz Multi Core Low Cyclic Power

120MHz Single Core Low Power


120/160MHz Single core Low Power



High

Reliability

Platform

Powertrain

Chassis & Safety

Air Bag

Body

EV/HEV 240MHz Dual core w/ LS


160MHz Single core w/LS


48

RH850/F1x Line-up

8MB

6MB

1.5MB

384KB

256KB

1MB

768KB

512KB

64 80 100 144 176 208 272 357

3MB

2MB

4MB

RH850/F1L

Single core 80MHz

RH850/F1H

Dual Core 120MHz

RH850/F1U

Triple-Core 160MHz

RH850/F1M

Single core 120MHz

QFP BGA






165 DMIPS, FPU, DSC




165 DMIPS, FPU, DSC

25 DMIPS, Low Power




Industrial, 90nm







Industrial, 40nm




2010 2012

32

-bit

8

/1

6-b

it

32-Bit High Performance DSP, FPU with High

Integration

32-Bit High Efficiency Ultra Low Power and Low

Voltage


Typically

SRAM

Typically

Flash Memory

RX Flash is

10 nsec, or

100 MHz

zero-wait

RX SRAM is

also 10 nsec

RX600 CISC CPU

5-STAGE PIPELINE

5 STAGES OF PIPELINE

F = FETCH INSTRUCTION

D = DECODE INSTRUCTION

E = EXECUTE INSTRUCTION

M = READ OR WRITE MEMORY

W = WRITE BACK TO REGISTER

Inst 64bit path Instruction

Data 32bit path

Operand

(Data)

ENHANCED HARVARD

ARCHITECTURE WRITE BUFFER

For Slow Memory

PRE-FETCH

QUEUE

(PFQ)

Holds 4 to 32

Instructions

for Slower

Memory Memory Interface

64

32

100MHz CPU Core

1.65 DMIPS/MHz

16 x 32bit

General

Purpose

Registers

9 x 32bit

Control

Registers

RX Architecture… CPU Core and Pipeline

32bit

Floating

Point

Unit

16x16 or 32x32 MAC,

48bit or 80bit Result

32 x 32 DIV or MULT,

32bit or 64bit Result

Memory

Protect

Unit

Interrupt

Control

On-Chip

Debug

ENHANCED HARVARD

ARCHITECTURE

5-STAGE PIPELINE

64

bit

s

64

bit

s

64

bit

s

64

bit

s

Buffer

Only for

Writes

F D E M W

TIC

K

F D

F

TIC

K

E

D

F

TIC

K

M

E

D

F

TIC

K

W

M

E

D

F

TIC

K

F

W

M

E

D

TIC

K

D

F

W

M

E

TIC

K

E

D

F

W

M

TIC

K

M

E

D

F

W

TIC

K

E E

E E

E

W

M

E

D

F

Achieves One

Clock-Per-Instruction (CPI)


Advanced Bus Architecture for High Data Throughput


RX vs. M4: Performance, Power & Peripherals


RX600 Series: High Performance Roadmap

Up to 120 MHz 40 nm Process

100 MHz, Single Cycle Flash 90 nm Process


RX200 Series: Low Power Roadmap

RX210

Comparator ＥＬＣ

50MHz

64KB- 256KB

RX210


50MHz

128BK-512KB

RX210


50MHz

1MB

RX220


32MHz

256KB

RX211


50MHz

USB

RX211

24 bit ADC AES

50MHz

512KB


RX: Scalable Lineup


Next Generation RX


4.0 Coremark/MHz 400MHz～

Next

RX CPU Architecture Roadmap

• High Performance • Low Power • Small Code Size

2012

RX-v2 (240MHz～)

3.30 Coremark/MHz

0.78 Automark/MHz

RX64x

2015

Smaller gate count

Smaller code size

Higher

Performance/MHz

RX-v1 (200MHz～)

RX600, RX200, RX100

2.76 Coremark/MHz

0.68 Automark/MHz

2009


RX Family Roadmap: Next Generation

RX100

RX200

RX600

Up to 4MB DSC, FPU,

Connectivity

Up to 8MB Dual

Ethernet, DSP, LCD

240MHz

RX700

Lowest Power 32-bit platform in

the Industry

32MHz

Low power, Up to 1MB Flash, 1.62 to 5.5v, 24-bit ADC, Security

100/120MHz

50MHz


32-bit Performance

Integration

Eco-System

Higher power consumption

Industry Leading Low Power 32-bit Platform

RX-L (32-bit)

32-bit 8/16-bit

<1$ price point

Lowest Power

Fast wake up

Analog integration

Scalability

1.56 DMIPS/MHz performance

155uA/DMIPS in active & 0.1uA in standby

<$1 price point

RX scalability

Similar eco-system


RX-L: Lowest Power 32-bit Family

1.56DMIPS/MHz

1.25DMIPS/MHz

0.9DMIPS/MHz

1.25DMIPS/MHz

155µA/DMIPS

200µA/DMIPS

300µA/DMIPS Company A

Cortex M3

Company B

Cortex M0

RX-L

Cortex

M4

RX-L

Cortex

M3

Cortex

M0

Best in class Performance Best in class Power efficiency


• Lowest DC off set, lowest power at 1 MHz, faster wake up (<5us), <155uA/DMIPS active, 0.1uA standby

Lowest Power 32-bit MCU

• 8KB to 2MB Flash memory, Smaller 3x3mm QFN/WPP package for space critical applications Memory & Package

• ELC, Asynchronous Timers to reduce power consumption Innovative integration

• IEC60730 are critical for medical and Industrial Safety features

• PMC to offer maximum number of I/O, Semi- programmability of I/Os and reduction of external noise circuitry Flexibility of layout

• 12-bit, 24-bit A/Ds, 10-bit D/As, Op-Amps, Comparators, Temp sense, Capacitive touch etc.

Bridge between Digital and Analog world

RX100: Unique Differentiators


•120MHz/240Mhz operation with 120MHz single cycle Flash High Performance

•4MB Flash, 512KB RAM, IEE1588 Dual Ethernet, Trusted ELC, 2MSPS ADC, Data Capture Unit, SDIO, MMC etc. Innovative Integration

• IEC60730, AES security, CRC, DOC , CSD etc. Safety Features

•PMC to offer maximum number of I/O, Semi-programmability of I/Os and reduction of external noise circuitry, Event Link Controller

Flexibility of layout

•64 pin to 256 pin package variants Flexible package size

•12-bit, 24-bit A/Ds, 10-bit D/As, Op-Amps, Comparators, Temp sense, etc.

Bridge between digital and Analog world

RX700: 40nm, 240MHz Industrial Applications






165 DMIPS, FPU, DSC




165 DMIPS, FPU, DSC

25 DMIPS, Low Power




Industrial, 90nm







Industrial, 40nm




2010 2012

32

-bit

8

/1

6-b

it

8/16-Bit True Low Power High Efficiency & Integration


RL78 Renesas New Low end core performs up to 40.6DMIPS

RL78/G14 core hits 44DMIPS with DSP instructions

Low-end CPU Core Roadmap

78K Architecture

R8C Architecture

78K0

8bit, 2.9DMIPS

78K0R

16bit, 31.2DMIPS

78K0S 8bit,1.1DMIPS

RL78 16bit, 40.6DMIPS

RL78/G14 core 16bit, 44DMIPS

Compact

MAC/MUL/DIV instructions R8C

10 DMIPS

RL78 Architecture

Renesas New Low end core


RL78/G14 only

PC SP

MUL/MAC /DIV.

Address Bus

Addr./

Data Bus

Control Signals

PSW

ALU

Bit Interrupt Controller

RL78 CPU Core

Register Banks 0-3: 16-bit (Register Pair)

Internal Buses Bank 3

Bank 2

Bank 1

Bank 0

System Bus Interface ES

CS

16-Bit Barrel Shifter


RL78 CPU Low Power Technique

2nd- Byte

1st- Byte

2nd-byte decoder turned on, only when the instruction is judged as 2 bytes instruction

Fetch ID MEM

Decode + Address operation MEM operation + Write

Judge 1 or 2 instruction bytes

Add

HL +Byte

Fetch

Write

Ex) ADD A, [HL] - Instruction : 1byte - Address Operation : HL - Data Operation : ADD

BR$

RAM

Bit

Mul

…

Instru

ctio

n

Decode

r

Addre

ss

Ope

rator

Data

Ope

rator

Only the operator which will be used in a instruction will be turned on.

Current reduction!

25% 50%

Decoder Operator

3-stage pipe line

66uA/MHz at basic operation (NOP)

Selected “Path”

Automatically Adjusted


Flash modes realize an optimal power consumption

Flash Operation Modes

VDD

VSS

CPU, Peripherals

I/O Etc.

Reg

RL78

Regulator System

HS (High-speed) mode:

32MHz (VDD = 2.7 to 5.5V)

16MHz (VDD = 2.4 to 5.5V)

2.1V (Active, Halt) & 1.8V(STOP) regulator

LS (Low-speed) mode:

8MHz (VDD = 1.8 to 5.5V)

1.8V regulator

LV (Low-voltage) mode:

4MHz (VDD = 1.6 to 5.5V)

1.8V regulator

LS 8MHz

MCU current

1.7mA

HS 8MHz

LV 4MHz

1.2mA

HS 4MHz

0.8mA

LS 4MHz

1.7mA

1.2mA 1.3mA

30% down 40% down


Active Current Advantage to Competition

0

2

4

6

8

10

12

0 10 20 30

Po

wer

Co

nsu

mp

tio

n [

mA

]

Operation Frequency [MHz]

RL78/G13(VDD=2.0V/3.0V/5.0V)RL78/G13 (BasicOperation)A MCU-1 (VDD=3.6V)

A MCU-1 (VDD=3V)

A MCU-1 (VDD=2.2V)

A MCU-2 (VDD=3.0V)

A MCU-3 (VDD=3.0V)

A MCU-3 (VDD=2.2V)

0

2

4

6

8

10

12

0 10 20 30

Po

we

r C

on

sum

pti

on

[m

A]

Operation Frequency [MHz]

RL78/G13(VDD=2.0V/3.0V/5.0V)A MCU-1 (VDD=3.6V)

A MCU-1 (VDD=3V)

A MCU-1 (VDD=2.2V)

A MCU-2 (VDD=3.0V)

A MCU-3 (VDD=3.0V)

A MCU-3 (VDD=2.2V)

Typ. Value Max. Value

Competition

RL78

Competition

RL78


Fast wake-up is critical when active time is <30uS

Fast Wake-up is Good, but doesn’t Always Have an Effect

30usec

- Assuming current consumption during wake up is the same as during the Active

- Active mode: 8MHz, 3V

100usec

RL78

A MCU-3

10usec

1.2mA

2.0mA

22 mAusec

42 mAusec

25usec

Wake up time

Active Time Condition

1usec

72 mAusec

72 mAusec

35usec

204

mAusec

150

mAusec

100usec

No good

Better

Real Application functions

- Glass Break detector :35usec - Smock detector : 400usec - Health care applications : msec to sec - Remote controller : 100msec - UART 1 byte @ 9600bps = 1.04 msec - EEPROM storage ; msec order

Simple Monitoring - Simple Status check (1 ADC, Port check etc.) - Increment Standard Timer for

Real Time


RL78: Roadmap

Schedule is preliminary and subject to change

SEG

LCD

ASSP

~ CY 2012

Pro

duct

Cate

gory

CY 2013~

GEN

ERAL

G1x (USB)

L12 (LCD Standard) 32-64 pin, 8-32 KB

L1x (USB, Enhanced Analog)

I1A (Lighting)

F12 (Auto Body)

D1x (Auto Dashboard)

Metering

RF4CE

G13 (Standard) 20-128 pin, 16-512 KB

G12 (Lite) 20-30 pin, 2-16 KB G1x (Entry)

Sub 20 pins

G14 (High Function) 30-100 pin, 16-256 KB

G1A (Enhanced Analog) 25-64 pin, 16-64 KB

Capacitive Touch

L1x (High Function)


Scalability: RL78 Line-up (Over 300 products from 2KB to 512KB of flash memory)


RL78: Next Generation Concept


SMART15 Concept

Smart

Power

Asynchronous Architecture

SMART Snooze (in combination with more peripherals)

Intelligent-Wake-up (Quick wake-

up + lowest current)

Smart

Analog

Intelligent connection

between Analog-to-Analog &

Analog-to-Digital)

16/24-bit ADC & 12-bit DAC

Fast Comp, Op-Amps

SMART Integration

SMART Data Transfer Controller

SMART integration:

RF, Touch, Eink Display, BAN

Super SAFE: DOC, CAC, MPU


General Purpose

HMI

Application Specific

G15

sub Ghz Meter

Lighting

GP-Next (20-100 pin)

W/ Touch

W/LCD

GP-L next 10-20-pin

ASSP

GP

with LCD

G12 G13

G14

WCP

G10

RL78

Core

130um process

Next Generation Process

Remote

RL78/SMART15: Roadmap Concept


Summary

What should engineers care about?


Questions?


Challenge: Digital revolution is fuelling the exponential demand to manage the society more smarter and in a eco friendly way.

Solution:

In order to address the complex requirements of the Smart Society a scalable microcontroller portfolio which is supported by a rich eco system would be the most important selection criteria.

‘Enabling The Smart Society’


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