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Microcode Store

COMP375 1

More onMore on

MicrocodeMicrocode

Organization

Fetch Execute Cycle

1. Fetch the instruction from the memory

a ress n e rogram oun er reg s er

2. Increment the Program Counter

3. Decode the type of instruction

4. Fetch the operands

5. Execute the instruction6. Store the results

Simple CPU Instruction Fetch

1. Fetch the instruction from the memory

a ress n e rogram oun er reg s er

Copy the program counter to the MemoryAddress Register

Tell the memory system to read.

Copy from the Memory Data Register to

the Instruction Register

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Microcode Store

COMP375 2

Instruction Fetch

bu IR res A bus bus PC bus R1 bus R2 bus bus M A Mem

s

IR

adr

bus

ult

bus

L

U

res

ult

opr

nd

PC

bus

R1

bus

R2

bus

M

A

R

M

B

R

B

R

bus

L

U

fun

func

X X read

wait

X X

2. Increment the Program Counter

Copy the Program Counter to the ALU

npu reg s er.

Set the ALU function to increment.

Copy the ALU output register to the

Program Counter

2. Increment the Program Counter

bu

s

IR

IR

adr

bus

res

ult

bus

A

L

U

res

ult

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

M

AR

bus

M

BR

M

B

R

bus

A

L

U

fun

Mem

func

X X inc

4. Fetch the operands

Assuming direct addressing

Copy the address portion of the instruction

register to the Memory Address Register. Tell the memory system to read.

Wait for the read to complete

Copy from the Memory Data Register to

the appropriate data or ALU Register

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Microcode Store

COMP375 3

4. Fetch the operands

bu IR res A bus bus PC bus R1 bus R2 bus bus M ALU Mem

s

IR

adr

bus

ult

bus

L

U

res

ult

opr

nd

PC

bus

R1

bus

R2

bus

M

A

R

M

B

R

B

R

bus

func func

X X read

wait

? X

5. Execute the instruction

Assume an arithmetic instruction

Copy the operand from a data register to

an ALU input register.

Set the ALU function according to the

opcode field of the instruction register

5. Execute the instruction

bu

s

IR

IR

adr

bus

res

ult

bus

A

L

U

res

ult

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

M

AR

bus

M

BR

M

B

R

bu

s

ALU

func

Mem

func

X X add

X X

Assume adding R1 and R2

6. Store the results

Copy the output ALU register to the

appropr a e a a reg s er.

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Microcode Store

COMP375 4

6. Store the results

bu

s

IR

IR

adr

bus

res

ult

bus

A

L

U

res

ult

bus

opr

nd

bus

PC

PC

bu

s

bus

R1

R1

bus

bus

R2

R2

bus

bus

M

A

R

bus

M

B

R

M

B

R

bu

s

ALU

func

Mem

func

X X

Add R1, xyz (memory direct)bu

sIR

IR

adr

bus

res

ult

bus

A

LU

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

M

A

bus

M

B

M

BR

ALU

func

Mem

func

ult

X X read

wait

X X

X X inc

X X read

X X wait

X X add

X X

What control lines are set to copy

the value from the result reg to R1?bu

s

IR

adr

res

ult

A

L

U

A

L

U

bus

opr

bus

PC

P

C

bus

R1

R1

bus

bus

R2

R2

bus

bus

M

bus

M

M

B

R

Mem

func

IR bus bus res

ult

fun nd bu

s

A

R

B

R

bu

s

A B C E D

.

2. B & C

3. A & D

4. A & C

Layers

Applications

Middleware

High level languages

Machine Language

Microcode

Lo ic circuits

Gates

Transistors

Silicon structures

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Microcode Store

COMP375 5

Implementing Machine Language

Each machine language instruction is

mp emen e y a ser es o m croco e

steps.

Each instruction uses common microcode

steps to fetch the instruction and

increment the ro ram counter.

Example Layers

C++

A = A + B;

Assembler

Load R1, A

Add R1, B

Store R1, A

Load R1, A

Instruction fetch not shown

bus

IR

IR

adr

bus

resu

ltbus

A

L

U

resu

lt

bus

oprnd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

MAR

bus

MB

R

M

B

R

bus

A

L

Ufun

Mem

func

X X read

wait

X X

Add R1, B

Instruction fetch not shown

bus

IR

IR

adr

bus

resu

ltbus

A

L

U

resu

lt

bus

oprnd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

MAR

bus

MB

R

M

B

R

bus

A

L

Ufun

Mem

func

X X read

X X wait

X X add

X X

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Microcode Store

COMP375 6

Store R1, A

Instruction fetch not shown

bus

IR

IR

adr

bus

resu

ltbus

A

L

U

resu

lt

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

MA

R

bus

M

B

R

M

B

R

bus

A

L

U

fun

Mem

func

X X

X X write

wait

Microcode Steps

A microcode step is executed each clock

cyc e.

For each microcode step, the next line of

the microcode store is read.

The microcode data determines the state

bus.

Microcode Store Where is the Microcode kept?

1. RAM

2. Cache

3. ROM in CPU4. Registers

Mi d St

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Microcode Store

COMP375 7

Simple CPU Microcode Programs

The sequence of switch settings in the

m croco e s ore s a m croco e program.

Real microcode programs can

conditionally jump to another line in the

program.

a field with the address of the next

microcode step.

Try It

add R1, R2

Add to R2 to R1 and save the result in R1.

add R1, R2

Instruction fetch not shown

bus

IR

IR

adr

bus

resu

ltbus

A

L

Uresu

lt

bus

oprnd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

MAR

bus

MB

R

M

B

Rbus

A

L

Ufun

Mem

func

X X

X X add

X X

Mi d St

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Microcode Store

COMP375 8

Try It

add R1,[R2]

Add to R1 the value pointed to by R2

add R1, [R2]

Instruction fetch not shown

bus IR resu A bus bus PC bus R1 bus R2 bus bus M A Mem

IR

adr

bus

ltbus

L

U

resu

lt

opr

nd

PC

bus

R1

bus

R2

bus

MA

R

M

B

R

B

R

bus

L

U

fun

func

X X read

X X wait

X X add

X X

Opcode Determines Microcode Steps

After the microcode steps to fetch the

ns ruc on an ncremen e program

counter, the next microcode step executed

depends on the opcode of the instruction.

Opcode and Microcode Step

Microcode Store

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Microcode Store

COMP375 9

Internal CPU Bus

Only one register can put its value on the

us a a me.

The value on the bus can be copied into

many registers at the same time.

Jump Instruct ion

Jump to the address given in the instruction

Direct Addressing

bus

IR

IR

adr

bus

resu

ltbus

A

L

U

resu

lt

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

MA

R

bus

M

B

R

M

B

R

bus

A

L

U

fun

Mem

func

X X

add R1, dog[R2]Register Indirect with Offset

The operand address is the sum of R2 and the address

field of the instruction.bus

IR

IR

adr

bus

resu

ltbus

A

L

U

resu

lt

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

MA

R

bus

M

B

R

M

B

R

bus

A

L

U

fun

Mem

func

X X

X X read

X X wait

X X add

X X

Optimizing Microcode

The more microcode steps required, the

lon er an instruction will take to execute.

The value on the bus can be copied into

multiple registers Instead of copying A to B then B to C, the

value in A can be copied to both B and C.

Unrelated microcode steps can be

executed before waiting for a memory

access to complete.

Microcode Store

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Microcode Store

COMP375 10

Instruction Fetch &

Program Counter Increment

bus

IR

IR

adr

bus

resu

ltbus

A

L

U

resu

lt

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

MA

R

bus

M

B

R

M

B

R

bus

A

L

U

fun

Mem

func

X X read

wait

X X

X X inc

X X

Instruction Fetch &

Program Counter IncrementCombining steps to reduce total time

bus

IR

IR

adr

bus

resu

ltbus

A

L

U

resu

lt

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

MA

R

bus

M

B

R

M

B

R

bus

A

L

U

fun

Mem

func

X X X inc read

X X wait

X X