Microchip NANOWatt Technology

© 2003 Microchip Technology Incorporated. All Rights Reserved.© 2003 Microchip Technology Incorporated. All Rights Reserved. 704 NWF Low Power Features of the 704 NWF Low Power Features of the nanoWattnanoWatt Family Devices Family Devices 11

704 NWF704 NWF704 NWF704 NWF

Low Power Features of the Low Power Features of the nanoWattnanoWatt Family Devices Family Devices



IntroductionIntroductionIntroductionIntroduction

PresentersPresenters PIC16 nanoWattPIC16 nanoWatt

PIC16F87/88,PIC16F87/88,PIC16F818/819PIC16F818/819

PIC18 nanoWattPIC18 nanoWatt PIC18F1220/1320, PIC18F1220/1320,

PIC18F2220/2320/4220/4320PIC18F2220/2320/4220/4320

Feel free to ask questions!Feel free to ask questions!

PresentersPresenters PIC16 nanoWattPIC16 nanoWatt

PIC16F87/88,PIC16F87/88,PIC16F818/819PIC16F818/819

PIC18 nanoWattPIC18 nanoWatt PIC18F1220/1320, PIC18F1220/1320,

PIC18F2220/2320/4220/4320PIC18F2220/2320/4220/4320

Feel free to ask questions!Feel free to ask questions!


AgendaAgendaAgendaAgenda

This 4 hour class will consist ofThis 4 hour class will consist of 2 Hours of lecture2 Hours of lecture

Ask questions at any timeAsk questions at any time A short break during the lectureA short break during the lecture

2 Hours of lab time2 Hours of lab time Take a break any timeTake a break any time Feel free to experimentFeel free to experiment Use either PIC16F88 or PIC18F1320Use either PIC16F88 or PIC18F1320

(Students choice)(Students choice)

This 4 hour class will consist ofThis 4 hour class will consist of 2 Hours of lecture2 Hours of lecture

Ask questions at any timeAsk questions at any time A short break during the lectureA short break during the lecture

2 Hours of lab time2 Hours of lab time Take a break any timeTake a break any time Feel free to experimentFeel free to experiment Use either PIC16F88 or PIC18F1320Use either PIC16F88 or PIC18F1320

(Students choice)(Students choice)


TopicsTopicsTopicsTopics

What is nanoWatt Technology?What is nanoWatt Technology? Clock SystemClock System 2-Speed Start-up2-Speed Start-up Fail-Safe Clock Monitor (FSCM)Fail-Safe Clock Monitor (FSCM) Watch Dog Timer (WDT)Watch Dog Timer (WDT) Power Managed ModesPower Managed Modes

Clock Sources and Clock Status FlagsClock Sources and Clock Status Flags Entry and Exit from Power Managed ModesEntry and Exit from Power Managed Modes Discuss each modeDiscuss each mode




What is What is nanoWattnanoWatt Technology? Technology?What is What is nanoWattnanoWatt Technology? Technology?

Microchip took the existing portfolio of Microchip took the existing portfolio of products and made several improvementsproducts and made several improvements Redesigned existing modules for lower current Redesigned existing modules for lower current

operationoperation Added a new Internal Oscillator and Oscillator Added a new Internal Oscillator and Oscillator

modesmodes Added new Power Managed features and Added new Power Managed features and

modes to PIC16 and PIC18 devicesmodes to PIC16 and PIC18 devices

Microchip took the existing portfolio of Microchip took the existing portfolio of products and made several improvementsproducts and made several improvements Redesigned existing modules for lower current Redesigned existing modules for lower current

operationoperation Added a new Internal Oscillator and Oscillator Added a new Internal Oscillator and Oscillator

modesmodes Added new Power Managed features and Added new Power Managed features and

modes to PIC16 and PIC18 devicesmodes to PIC16 and PIC18 devices


nanoWatt nanoWatt Family DevicesFamily DevicesnanoWatt nanoWatt Family DevicesFamily Devices

PIC16 FamilyPIC16 FamilyPIC16F87 / PIC16F87 / 8888

PIC16F628APIC16F628A

PIC16F630PIC16F630

PIC16F676PIC16F676

PIC16F818PIC16F818


PIC16F628APIC16F628A

PIC16F630PIC16F630

PIC16F676PIC16F676

PIC16F818PIC16F818


PIC18F2220 / 2320PIC18F2220 / 2320

PIC18F4220 / 4320PIC18F4220 / 4320

This class focuses on This class focuses on PIC16F88 and PIC16F88 and PIC18F1320 devicesPIC18F1320 devices


PIC18F2220 / 2320PIC18F2220 / 2320

PIC18F4220 / 4320PIC18F4220 / 4320

This class focuses on This class focuses on PIC16F88 and PIC16F88 and PIC18F1320 devicesPIC18F1320 devices

PIC12 FamilyPIC12 FamilyPIC12F629PIC12F629

PIC12F675PIC12F675

PIC12 FamilyPIC12 FamilyPIC12F629PIC12F629

PIC12F675PIC12F675


Clock SystemClock SystemClock SystemClock System

PIC16 and PIC18 clock systemsPIC16 and PIC18 clock systems Clock SourcesClock Sources

PrimaryPrimary SecondarySecondary Internal Oscillator Block (8 MHz)Internal Oscillator Block (8 MHz) INTRC (31 kHz)INTRC (31 kHz)

OSCTUNE RegisterOSCTUNE Register

PIC16 and PIC18 clock systemsPIC16 and PIC18 clock systems Clock SourcesClock Sources

PrimaryPrimary SecondarySecondary Internal Oscillator Block (8 MHz)Internal Oscillator Block (8 MHz) INTRC (31 kHz)INTRC (31 kHz)

OSCTUNE RegisterOSCTUNE Register


Clock System: PIC16Clock System: PIC16Clock System: PIC16Clock System: PIC16

Prescaler

Timer1Oscillator

PrimaryOscillator(EC, RC,

LP, XT, HS)

Timer 1 Enable

To CPU andPeripherals

To Timer 1

FS Clock Monitor

Bias

INTRC (31kHz)

Post- 1:2scaler 1:4

1:81:161:321:64

INTOSC

(8 MHz)

OSCCON

CONFIG1 &OSCCON

WDTPS

WDT / TMR0Multiplexer

1ms -2.1sec32us Prescaler

1:32 to 1:65536



Prescaler

Timer1Oscillator

PrimaryOscillator

(RC, EC, LP, XT,HS, HSPLL)

IDLEMode

Timer 1 Enable

To CPU Clock

To Peripherals

To Timer 1

FS Clock Monitor

WDT Postscaler1:1 to 1:32768

Bias

INTRC (31kHz)

Post- 1:2scaler 1:4

1:81:161:321:64

INTOSC

(8 MHz)

CONFIG1H &OSCCON

32us1:125

4ms WDTTime-out


Clock System: Primary ClocksClock System: Primary ClocksClock System: Primary ClocksClock System: Primary Clocks

Config Word defines Primary Clock SourceConfig Word defines Primary Clock Source 10 Modes - 4 mode bits (3 bits for PIC16)10 Modes - 4 mode bits (3 bits for PIC16) FOSC3:FOSC0 (_CONFIG1H<3:0>)FOSC3:FOSC0 (_CONFIG1H<3:0>)

External Clock - EC, ECIOExternal Clock - EC, ECIO Crystal Oscillator - LP, XT, HS, HSPLLCrystal Oscillator - LP, XT, HS, HSPLL** External RC Oscillator - RC, RCIOExternal RC Oscillator - RC, RCIO Internal Oscillator Block (IOB) - Internal Oscillator Block (IOB) -

INTIO1, INTIO2INTIO1, INTIO2

*PIC18 family only*PIC18 family only

Config Word defines Primary Clock SourceConfig Word defines Primary Clock Source 10 Modes - 4 mode bits (3 bits for PIC16)10 Modes - 4 mode bits (3 bits for PIC16) FOSC3:FOSC0 (_CONFIG1H<3:0>)FOSC3:FOSC0 (_CONFIG1H<3:0>)

External Clock - EC, ECIOExternal Clock - EC, ECIO Crystal Oscillator - LP, XT, HS, HSPLLCrystal Oscillator - LP, XT, HS, HSPLL** External RC Oscillator - RC, RCIOExternal RC Oscillator - RC, RCIO Internal Oscillator Block (IOB) - Internal Oscillator Block (IOB) -

INTIO1, INTIO2INTIO1, INTIO2

*PIC18 family only*PIC18 family only


Clock System: Primary ClocksClock System: Primary ClocksClock System: Primary ClocksClock System: Primary Clocks

When the Internal Oscillator Block is When the Internal Oscillator Block is selected as primary clock source:selected as primary clock source:

OSC1 pin functions as RA7 for input and OSC1 pin functions as RA7 for input and outputoutput

OSC2 pinOSC2 pin Outputs FOutputs FOSCOSC/4 or/4 or Functions as RA6 for input and outputFunctions as RA6 for input and output

When the Internal Oscillator Block is When the Internal Oscillator Block is selected as primary clock source:selected as primary clock source:

OSC1 pin functions as RA7 for input and OSC1 pin functions as RA7 for input and outputoutput

OSC2 pinOSC2 pin Outputs FOutputs FOSCOSC/4 or/4 or Functions as RA6 for input and outputFunctions as RA6 for input and output


Clock System:Clock System:Secondary ClockSecondary Clock


Legacy Timer1 OscillatorsLegacy Timer1 Oscillators Legacy devices do not control oscillator Legacy devices do not control oscillator

amplitudeamplitude Amplitude varies when VAmplitude varies when VDDDD and Temperature and Temperature

changechange Loading capacitors are criticalLoading capacitors are critical Oscillator current is 20-30 uAOscillator current is 20-30 uA

Legacy Timer1 OscillatorsLegacy Timer1 Oscillators Legacy devices do not control oscillator Legacy devices do not control oscillator

amplitudeamplitude Amplitude varies when VAmplitude varies when VDDDD and Temperature and Temperature

changechange Loading capacitors are criticalLoading capacitors are critical Oscillator current is 20-30 uAOscillator current is 20-30 uA




New Low Power Timer1 OscillatorNew Low Power Timer1 Oscillator About 3ua vs 30ua in other devicesAbout 3ua vs 30ua in other devices Oscillator amplitude is regulatedOscillator amplitude is regulated Constant current across VConstant current across VDDDD and Temperature and Temperature Loading capacitors are not as criticalLoading capacitors are not as critical Robust operationRobust operation

New Low Power Timer1 OscillatorNew Low Power Timer1 Oscillator About 3ua vs 30ua in other devicesAbout 3ua vs 30ua in other devices Oscillator amplitude is regulatedOscillator amplitude is regulated Constant current across VConstant current across VDDDD and Temperature and Temperature Loading capacitors are not as criticalLoading capacitors are not as critical Robust operationRobust operation




Secondary Oscillator (Timer1 Oscillator)Secondary Oscillator (Timer1 Oscillator) Enabled by T1OSCEN (T1CON<3>)Enabled by T1OSCEN (T1CON<3>) Commonly 32.768 kHz for a RTC time baseCommonly 32.768 kHz for a RTC time base User code is responsible for determining when User code is responsible for determining when

Secondary Clock is readySecondary Clock is ready

Secondary Oscillator (Timer1 Oscillator)Secondary Oscillator (Timer1 Oscillator) Enabled by T1OSCEN (T1CON<3>)Enabled by T1OSCEN (T1CON<3>) Commonly 32.768 kHz for a RTC time baseCommonly 32.768 kHz for a RTC time base User code is responsible for determining when User code is responsible for determining when

Secondary Clock is readySecondary Clock is ready


Clock System:Clock System:Internal Oscillator BlockInternal Oscillator Block


Internal 8MHz Oscillator (INTOSC)Internal 8MHz Oscillator (INTOSC) Calibrated to 8 MHz, 1% Typ, 2% Max at 25CCalibrated to 8 MHz, 1% Typ, 2% Max at 25C

‘F’ parts calibrated at 5V, ‘LF’ at 3V‘F’ parts calibrated at 5V, ‘LF’ at 3V Drives postscaler Drives postscaler Multiplexer selects 8, 4, 2, 1 MHz,Multiplexer selects 8, 4, 2, 1 MHz,

500, 250, 125 kHz, or 31 kHz clock sources500, 250, 125 kHz, or 31 kHz clock sources

Internal 8MHz Oscillator (INTOSC)Internal 8MHz Oscillator (INTOSC) Calibrated to 8 MHz, 1% Typ, 2% Max at 25CCalibrated to 8 MHz, 1% Typ, 2% Max at 25C

‘F’ parts calibrated at 5V, ‘LF’ at 3V‘F’ parts calibrated at 5V, ‘LF’ at 3V Drives postscaler Drives postscaler Multiplexer selects 8, 4, 2, 1 MHz,Multiplexer selects 8, 4, 2, 1 MHz,

500, 250, 125 kHz, or 31 kHz clock sources500, 250, 125 kHz, or 31 kHz clock sources

INTRC (31kHz)

Post- 1:2scaler 1:4

1:81:161:321:64

INTOSC

(8 MHz)SystemClock




Internal Oscillator Block (IOB)Internal Oscillator Block (IOB)(INTOSC 8 MHz output)(INTOSC 8 MHz output) Requires 1ms to 4ms to become stableRequires 1ms to 4ms to become stable

(check datasheet)(check datasheet) Code execution continues while stabilizingCode execution continues while stabilizing IOFSIOFS flag (OSCCON<2>) is set when INTOSC flag (OSCCON<2>) is set when INTOSC

8MHz output becomes stable8MHz output becomes stable Time critical code should wait for Time critical code should wait for IOFSIOFS flag flag

to be setto be set

Internal Oscillator Block (IOB)Internal Oscillator Block (IOB)(INTOSC 8 MHz output)(INTOSC 8 MHz output) Requires 1ms to 4ms to become stableRequires 1ms to 4ms to become stable

(check datasheet)(check datasheet) Code execution continues while stabilizingCode execution continues while stabilizing IOFSIOFS flag (OSCCON<2>) is set when INTOSC flag (OSCCON<2>) is set when INTOSC

8MHz output becomes stable8MHz output becomes stable Time critical code should wait for Time critical code should wait for IOFSIOFS flag flag

to be setto be set


Clock System: INTRCClock System: INTRCClock System: INTRCClock System: INTRC

Internal RC oscillator (INTRC)Internal RC oscillator (INTRC) Nominally 31 kHz (32us)Nominally 31 kHz (32us)

Fixed within 28 - 34 kHz rangeFixed within 28 - 34 kHz range Relatively insensitive to changes in Temp Relatively insensitive to changes in Temp

or Vor VDDDD compared to external RC Oscillator compared to external RC Oscillator Instantly readyInstantly ready When INTRC (31 kHz) is selected as system When INTRC (31 kHz) is selected as system

clock sourceclock source INTOSC output is disabled - saves currentINTOSC output is disabled - saves current Postscaler is disabled - saves currentPostscaler is disabled - saves current

Internal RC oscillator (INTRC)Internal RC oscillator (INTRC) Nominally 31 kHz (32us)Nominally 31 kHz (32us)

Fixed within 28 - 34 kHz rangeFixed within 28 - 34 kHz range Relatively insensitive to changes in Temp Relatively insensitive to changes in Temp

or Vor VDDDD compared to external RC Oscillator compared to external RC Oscillator Instantly readyInstantly ready When INTRC (31 kHz) is selected as system When INTRC (31 kHz) is selected as system

clock sourceclock source INTOSC output is disabled - saves currentINTOSC output is disabled - saves current Postscaler is disabled - saves currentPostscaler is disabled - saves current


Clock System: INTRCClock System: INTRCClock System: INTRCClock System: INTRC

INTRCINTRC enabled forenabled for Watch Dog TimerWatch Dog Timer

(check datasheet for periods)(check datasheet for periods) PIC16 - TPIC16 - TWDTWDT = 1ms (Nom.) = 1ms (Nom.) PIC18 - TPIC18 - TWDTWDT = 4ms (Nom.) = 4ms (Nom.)

Two-Speed StartupTwo-Speed Startup(Resets and Wake from SLEEP mode)(Resets and Wake from SLEEP mode)

Fail-Safe Clock MonitorFail-Safe Clock Monitor

INTRCINTRC enabled forenabled for Watch Dog TimerWatch Dog Timer

(check datasheet for periods)(check datasheet for periods) PIC16 - TPIC16 - TWDTWDT = 1ms (Nom.) = 1ms (Nom.) PIC18 - TPIC18 - TWDTWDT = 4ms (Nom.) = 4ms (Nom.)

Two-Speed StartupTwo-Speed Startup(Resets and Wake from SLEEP mode)(Resets and Wake from SLEEP mode)

Fail-Safe Clock MonitorFail-Safe Clock Monitor


Clock System: OSCTUNEClock System: OSCTUNEClock System: OSCTUNEClock System: OSCTUNE

OSCTUNE registerOSCTUNE register User adjustable FREQUENCY User adjustable FREQUENCY

6-bits, range is up to ±12.5%, 0.4% / step6-bits, range is up to ±12.5%, 0.4% / step AffectsAffects

8MHz INTOSC output frequency8MHz INTOSC output frequency 31kHz INTRC output frequency31kHz INTRC output frequency WDT periodWDT period Fail-Safe Clock Monitor periodFail-Safe Clock Monitor period 2-Speed Start-up frequency2-Speed Start-up frequency

OSCTUNE registerOSCTUNE register User adjustable FREQUENCY User adjustable FREQUENCY

6-bits, range is up to ±12.5%, 0.4% / step6-bits, range is up to ±12.5%, 0.4% / step AffectsAffects

8MHz INTOSC output frequency8MHz INTOSC output frequency 31kHz INTRC output frequency31kHz INTRC output frequency WDT periodWDT period Fail-Safe Clock Monitor periodFail-Safe Clock Monitor period 2-Speed Start-up frequency2-Speed Start-up frequency


Clock System: Clock System: INTOSC Freq and StatusINTOSC Freq and Status


When clocking from the INTOSC block, When clocking from the INTOSC block, code can select a higher clock frequency code can select a higher clock frequency when required forwhen required for Greater workload - CPU must do more workGreater workload - CPU must do more work Peripherals need higher speed clockPeripherals need higher speed clock

Code can select lower frequencyCode can select lower frequency Light workloadLight workload Peripherals can use lower resolution clockPeripherals can use lower resolution clock Reduce current consumptionReduce current consumption

When clocking from the INTOSC block, When clocking from the INTOSC block, code can select a higher clock frequency code can select a higher clock frequency when required forwhen required for Greater workload - CPU must do more workGreater workload - CPU must do more work Peripherals need higher speed clockPeripherals need higher speed clock

Code can select lower frequencyCode can select lower frequency Light workloadLight workload Peripherals can use lower resolution clockPeripherals can use lower resolution clock Reduce current consumptionReduce current consumption


IRCF<2:0> Frequency Notes IOFS Flag

000 31 kHz INTOSC Disabled 0

001 125 kHz 1:64 1 (delayed)

010 250 kHz 1:32 1 (delayed)

011 500 kHz 1:16 1 (delayed)

100 1 MHz 1:8 1 (delayed)



111 8 MHz INTOSC direct 1 (delayed)



Select desired INTOSC FrequencySelect desired INTOSC Frequency IOFS gets set when INTOSC becomes stableIOFS gets set when INTOSC becomes stable

Select desired INTOSC FrequencySelect desired INTOSC Frequency IOFS gets set when INTOSC becomes stableIOFS gets set when INTOSC becomes stable


Clock System: Clock System: OSCCON RegisterOSCCON Register

Clock System: Clock System: OSCCON RegisterOSCCON Register

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0R/W-0 R/W-0 R/W-0 R/W-0 R-q R-0 R/W-0 R/W-0

IDLENIDLEN Controls CPU clocking (PIC18 Only)Controls CPU clocking (PIC18 Only)

IRCF<2:0>IRCF<2:0> Selects tap from INTOSC PostscalerSelects tap from INTOSC Postscaler

OSTSOSTS =1 if Primary clock is currently providing the =1 if Primary clock is currently providing the system clock system clock

IOFSIOFS =1 if INTOSC (8 MHz) output is stable=1 if INTOSC (8 MHz) output is stable

SCS<1:0>SCS<1:0> Selects the power managed mode clock Selects the power managed mode clock sourcesource


Clock System:Clock System:Clock SwitchingClock SwitchingClock System:Clock System:

Clock SwitchingClock Switching

Modifying IRCF<2:0> bits immediately Modifying IRCF<2:0> bits immediately selects a different selects a different INTOSCINTOSC postscaler tap postscaler tap

If VIf VDDDD <2.9V, care must be taken to avoid <2.9V, care must be taken to avoid selecting the 8MHz output by mistakeselecting the 8MHz output by mistake CPU may not operate properly outside CPU may not operate properly outside

specified Frequency / Vspecified Frequency / VDDDD limits limits Recommended ProcedureRecommended Procedure

Read OSCCON to shadow registerRead OSCCON to shadow register Modify shadowModify shadow Write shadow back to OSCCONWrite shadow back to OSCCON

Modifying IRCF<2:0> bits immediately Modifying IRCF<2:0> bits immediately selects a different selects a different INTOSCINTOSC postscaler tap postscaler tap

If VIf VDDDD <2.9V, care must be taken to avoid <2.9V, care must be taken to avoid selecting the 8MHz output by mistakeselecting the 8MHz output by mistake CPU may not operate properly outside CPU may not operate properly outside

specified Frequency / Vspecified Frequency / VDDDD limits limits Recommended ProcedureRecommended Procedure

Read OSCCON to shadow registerRead OSCCON to shadow register Modify shadowModify shadow Write shadow back to OSCCONWrite shadow back to OSCCON


Clock System: Clock System: INTOSC Frequency SwitchINTOSC Frequency Switch

Clock System: Clock System: INTOSC Frequency SwitchINTOSC Frequency Switch

; This code safely modifies OSCCON; This code safely modifies OSCCON

movf OSCCON,W movf OSCCON,W ; copy OSCCON to WREG; copy OSCCON to WREG

andlw B’10001111’ andlw B’10001111’ ; clear IRCF bits; clear IRCF bits

iorlw B’01010000’ iorlw B’01010000’ ; new IRCF bits (2MHz); new IRCF bits (2MHz)

movwf OSCCON movwf OSCCON ; copy result to OSCCON; copy result to OSCCON

; This eliminates the possibility of selecting; This eliminates the possibility of selecting; 8MHz even for one instruction cycle.; 8MHz even for one instruction cycle.

; Operations on OSCCON,IRCF bits have; Operations on OSCCON,IRCF bits have; immediate effects!; immediate effects!

; This code safely modifies OSCCON; This code safely modifies OSCCON

movf OSCCON,W movf OSCCON,W ; copy OSCCON to WREG; copy OSCCON to WREG

andlw B’10001111’ andlw B’10001111’ ; clear IRCF bits; clear IRCF bits

iorlw B’01010000’ iorlw B’01010000’ ; new IRCF bits (2MHz); new IRCF bits (2MHz)

movwf OSCCON movwf OSCCON ; copy result to OSCCON; copy result to OSCCON

; This eliminates the possibility of selecting; This eliminates the possibility of selecting; 8MHz even for one instruction cycle.; 8MHz even for one instruction cycle.

; Operations on OSCCON,IRCF bits have; Operations on OSCCON,IRCF bits have; immediate effects!; immediate effects!


Two Speed Start-up:Two Speed Start-up:OverviewOverview

Two Speed Start-up:Two Speed Start-up:OverviewOverview

Allows code execution to start before the Allows code execution to start before the Primary clock source becomes readyPrimary clock source becomes ready

Internal Oscillator Block (IOB) provides Internal Oscillator Block (IOB) provides clocks before Primary clock source becomes clocks before Primary clock source becomes readyready

Automatically switches to Primary when it Automatically switches to Primary when it becomes readybecomes ready

Used forUsed for Start from ResetStart from Reset Wake from SLEEP ModeWake from SLEEP Mode

Allows code execution to start before the Allows code execution to start before the Primary clock source becomes readyPrimary clock source becomes ready

Internal Oscillator Block (IOB) provides Internal Oscillator Block (IOB) provides clocks before Primary clock source becomes clocks before Primary clock source becomes readyready

Automatically switches to Primary when it Automatically switches to Primary when it becomes readybecomes ready

Used forUsed for Start from ResetStart from Reset Wake from SLEEP ModeWake from SLEEP Mode


Two Speed Start-up:Two Speed Start-up:OperationOperation


Primary clocks might not be available due to Primary clocks might not be available due to startup delaysstartup delays Crystal / Resonator oscillator start timeCrystal / Resonator oscillator start time OST delay (counts 1024 oscillator cycles)OST delay (counts 1024 oscillator cycles) PLL delay (additional 2ms delay for HS/PLL)PLL delay (additional 2ms delay for HS/PLL)

The IOB can provide system clocks during The IOB can provide system clocks during this timethis time Code can select operating frequencyCode can select operating frequency Code may finish work quickly and go back to Code may finish work quickly and go back to

SLEEP before Primary is readySLEEP before Primary is ready

Primary clocks might not be available due to Primary clocks might not be available due to startup delaysstartup delays Crystal / Resonator oscillator start timeCrystal / Resonator oscillator start time OST delay (counts 1024 oscillator cycles)OST delay (counts 1024 oscillator cycles) PLL delay (additional 2ms delay for HS/PLL)PLL delay (additional 2ms delay for HS/PLL)

The IOB can provide system clocks during The IOB can provide system clocks during this timethis time Code can select operating frequencyCode can select operating frequency Code may finish work quickly and go back to Code may finish work quickly and go back to

SLEEP before Primary is readySLEEP before Primary is ready




When primary becomes readyWhen primary becomes ready Clock source switched to Primary clockClock source switched to Primary clock OSTS (OSCCON<3>) is setOSTS (OSCCON<3>) is set IOB may shut downIOB may shut down

INTRC may be required for other featuresINTRC may be required for other features Watch Dog Timer (WDT)Watch Dog Timer (WDT) Fail-Safe Clock Monitor (FSCM)Fail-Safe Clock Monitor (FSCM)

When primary becomes readyWhen primary becomes ready Clock source switched to Primary clockClock source switched to Primary clock OSTS (OSCCON<3>) is setOSTS (OSCCON<3>) is set IOB may shut downIOB may shut down

INTRC may be required for other featuresINTRC may be required for other features Watch Dog Timer (WDT)Watch Dog Timer (WDT) Fail-Safe Clock Monitor (FSCM)Fail-Safe Clock Monitor (FSCM)


Two Speed Start-up: Two Speed Start-up: OperationOperation

Two Speed Start-up: Two Speed Start-up: OperationOperation

Enable by setting the IESO bit Enable by setting the IESO bit (_CONFIG2<1>) (PIC16)(_CONFIG2<1>) (PIC16)(_CONFIG1H<7>) (PIC18)(_CONFIG1H<7>) (PIC18)(Internal External Switch Over)(Internal External Switch Over)

Used with crystal based modes onlyUsed with crystal based modes only OST delay used with crystal modesOST delay used with crystal modes

(LP, XT, HS, and HS/PLL modes)(LP, XT, HS, and HS/PLL modes) HS/PLL (PIC18) adds 2msHS/PLL (PIC18) adds 2ms Other oscillator modes do not require 2-speed Other oscillator modes do not require 2-speed

startupsstartups

Enable by setting the IESO bit Enable by setting the IESO bit (_CONFIG2<1>) (PIC16)(_CONFIG2<1>) (PIC16)(_CONFIG1H<7>) (PIC18)(_CONFIG1H<7>) (PIC18)(Internal External Switch Over)(Internal External Switch Over)

Used with crystal based modes onlyUsed with crystal based modes only OST delay used with crystal modesOST delay used with crystal modes

(LP, XT, HS, and HS/PLL modes)(LP, XT, HS, and HS/PLL modes) HS/PLL (PIC18) adds 2msHS/PLL (PIC18) adds 2ms Other oscillator modes do not require 2-speed Other oscillator modes do not require 2-speed

startupsstartups


Two Speed Start-up:Two Speed Start-up: Assumptions Assumptions


Compare INTRC speed to typical crystal Compare INTRC speed to typical crystal startup times and delaysstartup times and delays LP mode oscillators start in 100’s of mSLP mode oscillators start in 100’s of mS XT mode oscillators start in 1’s of mSXT mode oscillators start in 1’s of mS HS mode oscillators start in 10’s of uSHS mode oscillators start in 10’s of uS HS/PLL mode starts in 2ms (PLL start delay)HS/PLL mode starts in 2ms (PLL start delay)

CPU requires 5 - 10 uS following wake CPU requires 5 - 10 uS following wake event to become ready to execute codeevent to become ready to execute code Assume 7usAssume 7us

Compare INTRC speed to typical crystal Compare INTRC speed to typical crystal startup times and delaysstartup times and delays LP mode oscillators start in 100’s of mSLP mode oscillators start in 100’s of mS XT mode oscillators start in 1’s of mSXT mode oscillators start in 1’s of mS HS mode oscillators start in 10’s of uSHS mode oscillators start in 10’s of uS HS/PLL mode starts in 2ms (PLL start delay)HS/PLL mode starts in 2ms (PLL start delay)

CPU requires 5 - 10 uS following wake CPU requires 5 - 10 uS following wake event to become ready to execute codeevent to become ready to execute code Assume 7usAssume 7us




Wake from SLEEP mode Wake from SLEEP mode OSCCON register loaded before entering OSCCON register loaded before entering

SLEEP modeSLEEP mode 31 kHz for LP mode (same as crystal)31 kHz for LP mode (same as crystal) 4 MHz for XT mode (same as crystal)4 MHz for XT mode (same as crystal) 8 MHz for HS and HS/PLL modes8 MHz for HS and HS/PLL modes

Wake from SLEEP mode Wake from SLEEP mode OSCCON register loaded before entering OSCCON register loaded before entering

SLEEP modeSLEEP mode 31 kHz for LP mode (same as crystal)31 kHz for LP mode (same as crystal) 4 MHz for XT mode (same as crystal)4 MHz for XT mode (same as crystal) 8 MHz for HS and HS/PLL modes8 MHz for HS and HS/PLL modes


Two Speed Start-up:Two Speed Start-up:What to expectWhat to expect


32.7 kHz LP mode (30.5us, 1T32.7 kHz LP mode (30.5us, 1TCYCY=122 us)=122 us) Without Two-Speed StartWithout Two-Speed Start

Crystal oscillator starts in about 750 msCrystal oscillator starts in about 750 ms OST adds 31.3 ms (1024 * 30.5 us = 31.3 ms)OST adds 31.3 ms (1024 * 30.5 us = 31.3 ms) 781 ms before instructions begin executing781 ms before instructions begin executing

With Two-Speed StartWith Two-Speed Start(INTRC @ 31 kHz, 1 T(INTRC @ 31 kHz, 1 TCYCY = 128 us) = 128 us) CPU requires 7us to start from wakeCPU requires 7us to start from wake In 774 ms, 6.0k instructions could be executed In 774 ms, 6.0k instructions could be executed

before clock switch occursbefore clock switch occurs

32.7 kHz LP mode (30.5us, 1T32.7 kHz LP mode (30.5us, 1TCYCY=122 us)=122 us) Without Two-Speed StartWithout Two-Speed Start

Crystal oscillator starts in about 750 msCrystal oscillator starts in about 750 ms OST adds 31.3 ms (1024 * 30.5 us = 31.3 ms)OST adds 31.3 ms (1024 * 30.5 us = 31.3 ms) 781 ms before instructions begin executing781 ms before instructions begin executing

With Two-Speed StartWith Two-Speed Start(INTRC @ 31 kHz, 1 T(INTRC @ 31 kHz, 1 TCYCY = 128 us) = 128 us) CPU requires 7us to start from wakeCPU requires 7us to start from wake In 774 ms, 6.0k instructions could be executed In 774 ms, 6.0k instructions could be executed





4 MHz XT mode (250ns, 1T4 MHz XT mode (250ns, 1TCYCY=1us)=1us) Without Two-Speed StartWithout Two-Speed Start

Crystal oscillator starts in about 1 msCrystal oscillator starts in about 1 ms OST adds 256 us (1024 * .25 us = 256 us)OST adds 256 us (1024 * .25 us = 256 us) 1.26 ms before instructions begin executing1.26 ms before instructions begin executing

With Two-Speed StartWith Two-Speed Start(INTOSC @ 4MHz, T(INTOSC @ 4MHz, TCYCY = 1us) = 1us) In 1.25 ms, 1.25K instructions could be In 1.25 ms, 1.25K instructions could be

executed before clock switch occursexecuted before clock switch occurs

4 MHz XT mode (250ns, 1T4 MHz XT mode (250ns, 1TCYCY=1us)=1us) Without Two-Speed StartWithout Two-Speed Start

Crystal oscillator starts in about 1 msCrystal oscillator starts in about 1 ms OST adds 256 us (1024 * .25 us = 256 us)OST adds 256 us (1024 * .25 us = 256 us) 1.26 ms before instructions begin executing1.26 ms before instructions begin executing

With Two-Speed StartWith Two-Speed Start(INTOSC @ 4MHz, T(INTOSC @ 4MHz, TCYCY = 1us) = 1us) In 1.25 ms, 1.25K instructions could be In 1.25 ms, 1.25K instructions could be

executed before clock switch occursexecuted before clock switch occurs




20MHz HS mode (T20MHz HS mode (TOSCOSC=50ns, 1T=50ns, 1TCYCY=200ns)=200ns) Without Two-Speed StartWithout Two-Speed Start

Crystal oscillator starts in about 10 usCrystal oscillator starts in about 10 us OST adds 51.2 us (1024 * .05 us = 51.2 us)OST adds 51.2 us (1024 * .05 us = 51.2 us) 61.2 uS before instructions begin executing61.2 uS before instructions begin executing

With Two-Speed StartWith Two-Speed Start(INTOSC @ 8MHz, 1 T(INTOSC @ 8MHz, 1 TCYCY = 500 ns) = 500 ns) CPU requires 7us to start from wakeCPU requires 7us to start from wake In 54.4 uS, 109 instructions could be executed In 54.4 uS, 109 instructions could be executed


20MHz HS mode (T20MHz HS mode (TOSCOSC=50ns, 1T=50ns, 1TCYCY=200ns)=200ns) Without Two-Speed StartWithout Two-Speed Start

Crystal oscillator starts in about 10 usCrystal oscillator starts in about 10 us OST adds 51.2 us (1024 * .05 us = 51.2 us)OST adds 51.2 us (1024 * .05 us = 51.2 us) 61.2 uS before instructions begin executing61.2 uS before instructions begin executing

With Two-Speed StartWith Two-Speed Start(INTOSC @ 8MHz, 1 T(INTOSC @ 8MHz, 1 TCYCY = 500 ns) = 500 ns) CPU requires 7us to start from wakeCPU requires 7us to start from wake In 54.4 uS, 109 instructions could be executed In 54.4 uS, 109 instructions could be executed





40MHz HS/PLL mode (25ns , 1T40MHz HS/PLL mode (25ns , 1TCYCY=100ns)=100ns) Without Two-Speed StartWithout Two-Speed Start

Crystal oscillator (10MHz) starts in about 10 usCrystal oscillator (10MHz) starts in about 10 us OST adds 102 us (1024 * 0.1 us = 102 us)OST adds 102 us (1024 * 0.1 us = 102 us) PLL adds 2ms (dominates startup delays)PLL adds 2ms (dominates startup delays) 2.1 ms before instructions begin executing2.1 ms before instructions begin executing

With Two-Speed StartWith Two-Speed Start(INTOSC @ 8MHz, 1 T(INTOSC @ 8MHz, 1 TCYCY = 500 ns) = 500 ns) CPU requires 7us to start from wakeCPU requires 7us to start from wake In 2.1 ms, 4.2k instructions could be executed In 2.1 ms, 4.2k instructions could be executed

before clock switchbefore clock switch

40MHz HS/PLL mode (25ns , 1T40MHz HS/PLL mode (25ns , 1TCYCY=100ns)=100ns) Without Two-Speed StartWithout Two-Speed Start

Crystal oscillator (10MHz) starts in about 10 usCrystal oscillator (10MHz) starts in about 10 us OST adds 102 us (1024 * 0.1 us = 102 us)OST adds 102 us (1024 * 0.1 us = 102 us) PLL adds 2ms (dominates startup delays)PLL adds 2ms (dominates startup delays) 2.1 ms before instructions begin executing2.1 ms before instructions begin executing

With Two-Speed StartWith Two-Speed Start(INTOSC @ 8MHz, 1 T(INTOSC @ 8MHz, 1 TCYCY = 500 ns) = 500 ns) CPU requires 7us to start from wakeCPU requires 7us to start from wake In 2.1 ms, 4.2k instructions could be executed In 2.1 ms, 4.2k instructions could be executed

before clock switchbefore clock switch


Fail-Safe Clock Monitor Fail-Safe Clock Monitor (FSCM)(FSCM)

Fail-Safe Clock Monitor Fail-Safe Clock Monitor (FSCM)(FSCM)

How Does It Work?How Does It Work? How To Enable ItHow To Enable It

When is it usedWhen is it used Operation DuringOperation During

Clock Source FailureClock Source Failure System Start-UpSystem Start-Up Wake from SLEEP modeWake from SLEEP mode

How Does It Work?How Does It Work? How To Enable ItHow To Enable It

When is it usedWhen is it used Operation DuringOperation During

Clock Source FailureClock Source Failure System Start-UpSystem Start-Up Wake from SLEEP modeWake from SLEEP mode


FSCM: How Does It Work?FSCM: How Does It Work?FSCM: How Does It Work?FSCM: How Does It Work?

Sample Clock(INTRC/64 - Clear)

Peripheral Clock(Clock/4 - Set)

CM F/FQ Output

OSCFIF

OscillatorFailure

FailureDetected

Set OSCFIF

INTRC(32 us)

64

Set Q

Clear !Q

Peripheral clockClock Monitor F/F

~2ms period

CM F/FTested

CM F/FTested

CM F/FTested


FSCM: How To EnableFSCM: How To EnableFSCM: How To EnableFSCM: How To Enable

Enable by setting the FSCMEN bit Enable by setting the FSCMEN bit (_CONFIG2<0>) (PIC16)(_CONFIG2<0>) (PIC16)(_CONFIG1H<6>) (PIC18)(_CONFIG1H<6>) (PIC18)(Fail-Safe Clock Monitor ENable)(Fail-Safe Clock Monitor ENable)

Used to detect a loss of externally based Used to detect a loss of externally based clocked sourcesclocked sources Only IOB is fully internalOnly IOB is fully internal

Enable by setting the FSCMEN bit Enable by setting the FSCMEN bit (_CONFIG2<0>) (PIC16)(_CONFIG2<0>) (PIC16)(_CONFIG1H<6>) (PIC18)(_CONFIG1H<6>) (PIC18)(Fail-Safe Clock Monitor ENable)(Fail-Safe Clock Monitor ENable)

Used to detect a loss of externally based Used to detect a loss of externally based clocked sourcesclocked sources Only IOB is fully internalOnly IOB is fully internal


FSCM: During FailureFSCM: During FailureFSCM: During FailureFSCM: During Failure

On Primary or Secondary clock failureOn Primary or Secondary clock failure Clears WDT (may not be enabled)Clears WDT (may not be enabled) Clock source switched to IOBClock source switched to IOB

OSTS is cleared if Primary failedOSTS is cleared if Primary failed T1RUN (T1CON<6>) cleared if Secondary T1RUN (T1CON<6>) cleared if Secondary

failedfailed OSCCON is OSCCON is NOTNOT updated updated

OSCFIF (PIR2<7>) is setOSCFIF (PIR2<7>) is set If interrupts enabled, causes wake If interrupts enabled, causes wake withoutwithout

clock switch to Primary clock sourceclock switch to Primary clock source

On Primary or Secondary clock failureOn Primary or Secondary clock failure Clears WDT (may not be enabled)Clears WDT (may not be enabled) Clock source switched to IOBClock source switched to IOB

OSTS is cleared if Primary failedOSTS is cleared if Primary failed T1RUN (T1CON<6>) cleared if Secondary T1RUN (T1CON<6>) cleared if Secondary

failedfailed OSCCON is OSCCON is NOTNOT updated updated

OSCFIF (PIR2<7>) is setOSCFIF (PIR2<7>) is set If interrupts enabled, causes wake If interrupts enabled, causes wake withoutwithout

clock switch to Primary clock sourceclock switch to Primary clock source


When clocked by internal RC clock sourceWhen clocked by internal RC clock source If IRCF bits are If IRCF bits are == 000 000

Clocked from INTRC at 31kHzClocked from INTRC at 31kHz If IRCF bits are If IRCF bits are 000 000

Clocked from Clocked from INTOSCINTOSC at higher speed at higher speed The IRCF bits may be set prior to the clock The IRCF bits may be set prior to the clock

failure, i.e. during device startupfailure, i.e. during device startup

When clocked by internal RC clock sourceWhen clocked by internal RC clock source If IRCF bits are If IRCF bits are == 000 000

Clocked from INTRC at 31kHzClocked from INTRC at 31kHz If IRCF bits are If IRCF bits are 000 000

Clocked from Clocked from INTOSCINTOSC at higher speed at higher speed The IRCF bits may be set prior to the clock The IRCF bits may be set prior to the clock

failure, i.e. during device startupfailure, i.e. during device startup

FSCM: During FailureFSCM: During FailureFSCM: During FailureFSCM: During Failure


FSCM: Normal StartupFSCM: Normal Startup(Reset or Wake from SLEEP)(Reset or Wake from SLEEP)

FSCM: Normal StartupFSCM: Normal Startup(Reset or Wake from SLEEP)(Reset or Wake from SLEEP)

During start-up (reset or wake from sleep)During start-up (reset or wake from sleep) Internal Oscillator Block provides system Internal Oscillator Block provides system

clocks until Primary clock is ready (similar toclocks until Primary clock is ready (similar to2-speed start)2-speed start)

When the primary is ready, an automatic clock When the primary is ready, an automatic clock switch selects the primary clockswitch selects the primary clock

FSCM then becomes active, and OSTS is setFSCM then becomes active, and OSTS is set INTOSC (8MHz) is disabledINTOSC (8MHz) is disabled

INTRC (31 kHz) runs for FSCM (and WDT)INTRC (31 kHz) runs for FSCM (and WDT) This prevents false fails at startupThis prevents false fails at startup

During start-up (reset or wake from sleep)During start-up (reset or wake from sleep) Internal Oscillator Block provides system Internal Oscillator Block provides system

clocks until Primary clock is ready (similar toclocks until Primary clock is ready (similar to2-speed start)2-speed start)

When the primary is ready, an automatic clock When the primary is ready, an automatic clock switch selects the primary clockswitch selects the primary clock

FSCM then becomes active, and OSTS is setFSCM then becomes active, and OSTS is set INTOSC (8MHz) is disabledINTOSC (8MHz) is disabled

INTRC (31 kHz) runs for FSCM (and WDT)INTRC (31 kHz) runs for FSCM (and WDT) This prevents false fails at startupThis prevents false fails at startup


FSCM: FSCM: Startup with Failed PrimaryStartup with Failed Primary

FSCM: FSCM: Startup with Failed PrimaryStartup with Failed Primary

During start-up (reset or wake from sleep)During start-up (reset or wake from sleep) If the Primary clock never becomes ready, no If the Primary clock never becomes ready, no

clock failure will be detectedclock failure will be detected Firmware will need to detect this conditionFirmware will need to detect this condition

Check OSTS flag after suitable delayCheck OSTS flag after suitable delay FSCM becomes active if SEC_(mode) is FSCM becomes active if SEC_(mode) is

selected before Primary becomes readyselected before Primary becomes ready

During start-up (reset or wake from sleep)During start-up (reset or wake from sleep) If the Primary clock never becomes ready, no If the Primary clock never becomes ready, no

clock failure will be detectedclock failure will be detected Firmware will need to detect this conditionFirmware will need to detect this condition

Check OSTS flag after suitable delayCheck OSTS flag after suitable delay FSCM becomes active if SEC_(mode) is FSCM becomes active if SEC_(mode) is

selected before Primary becomes readyselected before Primary becomes ready


Watch Dog TimersWatch Dog TimersWatch Dog TimersWatch Dog Timers

General WDTGeneral WDT PIC16 WDTPIC16 WDT PIC18 WDTPIC18 WDT

General WDTGeneral WDT PIC16 WDTPIC16 WDT PIC18 WDTPIC18 WDT


Watch Dog TimersWatch Dog TimersWatch Dog TimersWatch Dog Timers

Clocked by INTRC (32us period)Clocked by INTRC (32us period) Has same characteristics as INTRC across Has same characteristics as INTRC across

temperature and Vtemperature and VDDDD

Greatly improved stability compared with Greatly improved stability compared with previous WDTsprevious WDTs

WDT may be enabled by firmware if WDT may be enabled by firmware if configured disabled by configuration wordconfigured disabled by configuration word SWDTEN (WDTCON<0>)SWDTEN (WDTCON<0>)

Clocked by INTRC (32us period)Clocked by INTRC (32us period) Has same characteristics as INTRC across Has same characteristics as INTRC across

temperature and Vtemperature and VDDDD

Greatly improved stability compared with Greatly improved stability compared with previous WDTsprevious WDTs

WDT may be enabled by firmware if WDT may be enabled by firmware if configured disabled by configuration wordconfigured disabled by configuration word SWDTEN (WDTCON<0>)SWDTEN (WDTCON<0>)


1ms - 2.097s

Watch Dog Timer: PIC16Watch Dog Timer: PIC16Watch Dog Timer: PIC16Watch Dog Timer: PIC16

INTRC

(31kHz)16-bit

PostscalerWDT Time-out

TMR0Sync

TMR0Register

RA4 / T0CKI

Fosc/4

TMR0IF

PSA

T0CS

0

1

1

1

18-bit Postscaler

0

0

0

OPTIONPS<2:0>WDTCON

WDTPS<3:0>

PSA = 0PSA = 0 OPTION postscaler OPTION postscaler

assigned to TMR0assigned to TMR0 WDT uses only WDT uses only

WDTCON postscalerWDTCON postscaler


assigned to TMR0assigned to TMR0 WDT uses only WDT uses only

WDTCON postscalerWDTCON postscaler


assigned to WDTassigned to WDT WDT uses both WDT uses both

postscalerspostscalers


assigned to WDTassigned to WDT WDT uses both WDT uses both

postscalerspostscalers

32us

INTOSC(8MHz)

PSA

PSA

(resets to 1:512)

(16.4ms)



WDTCON controls WDTCON postscaler WDTCON controls WDTCON postscaler Ratios 1:32 to 1:64K (1ms to 2.1s)Ratios 1:32 to 1:64K (1ms to 2.1s) Resets to 1:512 (16.4ms)Resets to 1:512 (16.4ms)

OPTION_REG controls OPTION postscalerOPTION_REG controls OPTION postscaler Ratios 1:1 to 1:128Ratios 1:1 to 1:128 Timer0 and WDT share postscalerTimer0 and WDT share postscaler

Postscalers may be used in seriesPostscalers may be used in series Ratios 1:1 to 1:8.4MRatios 1:1 to 1:8.4M Time-out range: 1ms to 268 sec / 4.5 minTime-out range: 1ms to 268 sec / 4.5 min

WDTCON controls WDTCON postscaler WDTCON controls WDTCON postscaler Ratios 1:32 to 1:64K (1ms to 2.1s)Ratios 1:32 to 1:64K (1ms to 2.1s) Resets to 1:512 (16.4ms)Resets to 1:512 (16.4ms)

OPTION_REG controls OPTION postscalerOPTION_REG controls OPTION postscaler Ratios 1:1 to 1:128Ratios 1:1 to 1:128 Timer0 and WDT share postscalerTimer0 and WDT share postscaler

Postscalers may be used in seriesPostscalers may be used in series Ratios 1:1 to 1:8.4MRatios 1:1 to 1:8.4M Time-out range: 1ms to 268 sec / 4.5 minTime-out range: 1ms to 268 sec / 4.5 min



Prescaler

Timer1Oscillator

PrimaryOscillator

(RC, EC, LP, XT,HS, HSPLL)

IDLEMode

Timer 1 Enable

To CPU Clock

To Peripherals

To Timer 1

FS Clock Monitor

WDT Postscaler1:1 to 1:32768

Bias

INTRC (31kHz)

Post- 1:2scaler 1:4

1:81:161:321:64

INTOSC

(8 MHz)

CONFIG1H &OSCCON

32us1:125

4msWDT

Time-out



WDT postscaler offers more ratiosWDT postscaler offers more ratios WDT period is 4.0 ms (125 * 32us)WDT period is 4.0 ms (125 * 32us) 1:1 to 1:32,768 (4 ms to 131 sec / 2.2 min)1:1 to 1:32,768 (4 ms to 131 sec / 2.2 min) Ratio selected by CONFIG2H (fixed)Ratio selected by CONFIG2H (fixed)

WDT postscaler offers more ratiosWDT postscaler offers more ratios WDT period is 4.0 ms (125 * 32us)WDT period is 4.0 ms (125 * 32us) 1:1 to 1:32,768 (4 ms to 131 sec / 2.2 min)1:1 to 1:32,768 (4 ms to 131 sec / 2.2 min) Ratio selected by CONFIG2H (fixed)Ratio selected by CONFIG2H (fixed)


Power Managed ModesPower Managed ModesPower Managed ModesPower Managed Modes

How to reduce current consumption?How to reduce current consumption? How to reduce current consumption?How to reduce current consumption? Disable a clock source that is not neededDisable a clock source that is not needed Disable clocks to peripherals and/or CPUDisable clocks to peripherals and/or CPU Select a lower clock frequencySelect a lower clock frequency

Clock peripherals at lower speedClock peripherals at lower speed Execute code at lower speedExecute code at lower speed

Reduce or eliminate startup delaysReduce or eliminate startup delays Use low power peripheralsUse low power peripherals

Disable a clock source that is not neededDisable a clock source that is not needed Disable clocks to peripherals and/or CPUDisable clocks to peripherals and/or CPU Select a lower clock frequencySelect a lower clock frequency

Clock peripherals at lower speedClock peripherals at lower speed Execute code at lower speedExecute code at lower speed

Reduce or eliminate startup delaysReduce or eliminate startup delays Use low power peripheralsUse low power peripherals



What are Power Managed Modes?What are Power Managed Modes? Clock SourcesClock Sources Clock switch exampleClock switch example Clock source status FlagsClock source status Flags CPU Operation CPU Operation (PIC18 only)(PIC18 only) Entry to Power Managed ModesEntry to Power Managed Modes Exit from Power Managed ModesExit from Power Managed Modes

What are Power Managed Modes?What are Power Managed Modes? Clock SourcesClock Sources Clock switch exampleClock switch example Clock source status FlagsClock source status Flags CPU Operation CPU Operation (PIC18 only)(PIC18 only) Entry to Power Managed ModesEntry to Power Managed Modes Exit from Power Managed ModesExit from Power Managed Modes


Power Managed Modes:Power Managed Modes:What are they?What are they?

Power Managed Modes:Power Managed Modes:What are they?What are they?

Power Managed Modes allow the user to:Power Managed Modes allow the user to: Select System clock sourceSelect System clock source Select System clock frequencySelect System clock frequency Disable clocks to the CPU Disable clocks to the CPU (PIC18 only)(PIC18 only)

These options provide code with the means These options provide code with the means to control power consumption as neededto control power consumption as needed

Power Managed Modes allow the user to:Power Managed Modes allow the user to: Select System clock sourceSelect System clock source Select System clock frequencySelect System clock frequency Disable clocks to the CPU Disable clocks to the CPU (PIC18 only)(PIC18 only)

These options provide code with the means These options provide code with the means to control power consumption as neededto control power consumption as needed


Power Managed Modes:Power Managed Modes:Clock SourcesClock Sources


Select desired clock sourceSelect desired clock source Most Primary clock sources are fixed Most Primary clock sources are fixed

frequency (i.e. not controllable by code)frequency (i.e. not controllable by code) Secondary clock source (Timer1 Oscillator) is Secondary clock source (Timer1 Oscillator) is

fixed frequencyfixed frequency Required for Real-Time Clock time baseRequired for Real-Time Clock time base

Internal Oscillator Block allows selection of Internal Oscillator Block allows selection of clock frequencyclock frequency Code can select system frequency Code can select system frequency

according to needaccording to need

Select desired clock sourceSelect desired clock source Most Primary clock sources are fixed Most Primary clock sources are fixed

frequency (i.e. not controllable by code)frequency (i.e. not controllable by code) Secondary clock source (Timer1 Oscillator) is Secondary clock source (Timer1 Oscillator) is

fixed frequencyfixed frequency Required for Real-Time Clock time baseRequired for Real-Time Clock time base

Internal Oscillator Block allows selection of Internal Oscillator Block allows selection of clock frequencyclock frequency Code can select system frequency Code can select system frequency

according to needaccording to need




Select desired clock sourceSelect desired clock source Set the SCS<1:0> bits (OSCCON(<1:0>) for Set the SCS<1:0> bits (OSCCON(<1:0>) for

the desired clock sourcethe desired clock source PRI = 00 SEC = 01 INTOSC = 1XPRI = 00 SEC = 01 INTOSC = 1X

PIC18PIC18 - Execute SLEEP instruction - Execute SLEEP instruction PIC16 PIC16 - Clock switch is immediate- Clock switch is immediate

Consider using a shadow registerConsider using a shadow register

Select desired clock sourceSelect desired clock source Set the SCS<1:0> bits (OSCCON(<1:0>) for Set the SCS<1:0> bits (OSCCON(<1:0>) for

the desired clock sourcethe desired clock source PRI = 00 SEC = 01 INTOSC = 1XPRI = 00 SEC = 01 INTOSC = 1X

PIC18PIC18 - Execute SLEEP instruction - Execute SLEEP instruction PIC16 PIC16 - Clock switch is immediate- Clock switch is immediate

Consider using a shadow registerConsider using a shadow register


Power Managed Modes:Power Managed Modes:Clock Switching ExampleClock Switching ExamplePower Managed Modes:Power Managed Modes:

Clock Switching ExampleClock Switching Example

Switching from XT (old) to Timer1 (new)Switching from XT (old) to Timer1 (new) Execution pauses at the end of Q4 clockExecution pauses at the end of Q4 clock 8 cycles from the new clock are counted8 cycles from the new clock are counted Execution resumes clocked by the new clockExecution resumes clocked by the new clock

This example is repeated for every clock This example is repeated for every clock switching eventswitching event

Switching from XT (old) to Timer1 (new)Switching from XT (old) to Timer1 (new) Execution pauses at the end of Q4 clockExecution pauses at the end of Q4 clock 8 cycles from the new clock are counted8 cycles from the new clock are counted Execution resumes clocked by the new clockExecution resumes clocked by the new clock

This example is repeated for every clock This example is repeated for every clock switching eventswitching event

OSC1

TMR1

SysClkQ1 Q2 Q3 Q4 Q1 Q2 Q3

1 2 7 8//Q4Execution Pauses for 8 of the new clocks

Original clock is disabled (shut down)


Power Managed Modes:Power Managed Modes:Clock Status FlagsClock Status Flags


Each clock source sets a status bit to Each clock source sets a status bit to indicate when it is providing the system indicate when it is providing the system clockclock Primary clock - OSTS bit (OSCCON<3>)Primary clock - OSTS bit (OSCCON<3>) Secondary clock - T1RUN bit (T1CON<6>)Secondary clock - T1RUN bit (T1CON<6>) Internal Oscillator Block - IOFS bit Internal Oscillator Block - IOFS bit

(OSCCON<2>)(OSCCON<2>) Only one clock status bit will be set at any Only one clock status bit will be set at any

timetime

Each clock source sets a status bit to Each clock source sets a status bit to indicate when it is providing the system indicate when it is providing the system clockclock Primary clock - OSTS bit (OSCCON<3>)Primary clock - OSTS bit (OSCCON<3>) Secondary clock - T1RUN bit (T1CON<6>)Secondary clock - T1RUN bit (T1CON<6>) Internal Oscillator Block - IOFS bit Internal Oscillator Block - IOFS bit

(OSCCON<2>)(OSCCON<2>) Only one clock status bit will be set at any Only one clock status bit will be set at any

timetime




If no bits are set, If no bits are set, INTOSC is providing clocks but not yet stableINTOSC is providing clocks but not yet stable

OROR

INTRC is providing clocks at 31kHzINTRC is providing clocks at 31kHz

To determine IOB clock source, check To determine IOB clock source, check IOFS bit after suitable delay or IOFS bit after suitable delay or IRCF bitsIRCF bits

If no bits are set, If no bits are set, INTOSC is providing clocks but not yet stableINTOSC is providing clocks but not yet stable

OROR

INTRC is providing clocks at 31kHzINTRC is providing clocks at 31kHz

To determine IOB clock source, check To determine IOB clock source, check IOFS bit after suitable delay or IOFS bit after suitable delay or IRCF bitsIRCF bits




Register T1CON OSCCON

Clock T1RUN OSTS IOFS

PRI CLK 0 1 0

T1OSC 1 0 0

INTOSC 0 0 1 or 0

Register T1CON OSCCON

Clock T1RUN OSTS IOFS

PRI CLK 0 1 0

T1OSC 1 0 0

INTOSC 0 0 1 or 0

IOFS always =0 if IRCF<2:0>=000 (31kHz)IOFS always =0 if IRCF<2:0>=000 (31kHz) IOFS set after startup delay ifIOFS set after startup delay if

IRCF<2:0> =000IRCF<2:0> =000

IOFS always =0 if IRCF<2:0>=000 (31kHz)IOFS always =0 if IRCF<2:0>=000 (31kHz) IOFS set after startup delay ifIOFS set after startup delay if

IRCF<2:0> =000IRCF<2:0> =000



MODE CPU Periph IDLENSCS<1:0>

PRI_RUN PRI CLK PRI CLK X XXSEC_RUN T1OSC T1OSC 0 01RC_RUN INTOSC INTOSC 0 1XSLEEP OFF OFF 0 00

PRI_IDLE OFF PRI CLK 1 00SEC_IDLE OFF T1OSC 1 01RC_IDLE OFF INTRC 1 1X

MODE CPU Periph IDLENSCS<1:0>

PRI_RUN PRI CLK PRI CLK X XXSEC_RUN T1OSC T1OSC 0 01RC_RUN INTOSC INTOSC 0 1XSLEEP OFF OFF 0 00

PRI_IDLE OFF PRI CLK 1 00SEC_IDLE OFF T1OSC 1 01RC_IDLE OFF INTRC 1 1X


PRI_RUN ModePRI_RUN ModePRI_RUN ModePRI_RUN Mode

This is the normal full power execution modeThis is the normal full power execution mode Exits from all other power managed modes Exits from all other power managed modes

return to PRI_RUN modereturn to PRI_RUN mode CPU and peripherals are clocked by Primary CPU and peripherals are clocked by Primary

clock sourceclock source T1RUN, IOFS clearedT1RUN, IOFS cleared

OSTS setOSTS set

This is the normal full power execution modeThis is the normal full power execution mode Exits from all other power managed modes Exits from all other power managed modes

return to PRI_RUN modereturn to PRI_RUN mode CPU and peripherals are clocked by Primary CPU and peripherals are clocked by Primary

clock sourceclock source T1RUN, IOFS clearedT1RUN, IOFS cleared

OSTS setOSTS set


This is the sleep mode in other Microchip This is the sleep mode in other Microchip controllerscontrollers

IDLEN = 0 (PIC18 only), SCS<1:0> = 00IDLEN = 0 (PIC18 only), SCS<1:0> = 00 Execute SLEEP instructionExecute SLEEP instruction

CPU not clockedCPU not clocked Peripherals depending on system clocks are Peripherals depending on system clocks are

not clockednot clocked Primary oscillator is disabledPrimary oscillator is disabled

This is the only power managed mode This is the only power managed mode where no system clock sources are runningwhere no system clock sources are running

This is the sleep mode in other Microchip This is the sleep mode in other Microchip controllerscontrollers

IDLEN = 0 (PIC18 only), SCS<1:0> = 00IDLEN = 0 (PIC18 only), SCS<1:0> = 00 Execute SLEEP instructionExecute SLEEP instruction

CPU not clockedCPU not clocked Peripherals depending on system clocks are Peripherals depending on system clocks are

not clockednot clocked Primary oscillator is disabledPrimary oscillator is disabled

This is the only power managed mode This is the only power managed mode where no system clock sources are runningwhere no system clock sources are running

SLEEP ModeSLEEP ModeSLEEP ModeSLEEP Mode


This mode replaces the clock switching This mode replaces the clock switching mechanism in other PIC18 controllersmechanism in other PIC18 controllers

Adjust peripherals for T1OSC frequencyAdjust peripherals for T1OSC frequency IDLEN = 0 IDLEN = 0 (PIC18 only)(PIC18 only), SCS<1:0> = 01, SCS<1:0> = 01 Execute a SLEEP instruction (PIC18 only)Execute a SLEEP instruction (PIC18 only)

CPU and Peripherals clocked using T1OSCCPU and Peripherals clocked using T1OSC Primary oscillator is disabledPrimary oscillator is disabled IOFS, OSTS clearedIOFS, OSTS cleared

T1RUN setT1RUN set

This mode replaces the clock switching This mode replaces the clock switching mechanism in other PIC18 controllersmechanism in other PIC18 controllers

Adjust peripherals for T1OSC frequencyAdjust peripherals for T1OSC frequency IDLEN = 0 IDLEN = 0 (PIC18 only)(PIC18 only), SCS<1:0> = 01, SCS<1:0> = 01 Execute a SLEEP instruction (PIC18 only)Execute a SLEEP instruction (PIC18 only)

CPU and Peripherals clocked using T1OSCCPU and Peripherals clocked using T1OSC Primary oscillator is disabledPrimary oscillator is disabled IOFS, OSTS clearedIOFS, OSTS cleared

T1RUN setT1RUN set

SEC_RUN ModeSEC_RUN ModeSEC_RUN ModeSEC_RUN Mode


Adjust peripherals for new clock frequencyAdjust peripherals for new clock frequency IRCF<2:0> selects clock speed (optional)IRCF<2:0> selects clock speed (optional) IDLEN = 0 IDLEN = 0 (PIC18 only)(PIC18 only), SCS<1:0> = 1X, SCS<1:0> = 1X Execute a SLEEP instruction (PIC18 only)Execute a SLEEP instruction (PIC18 only)

Primary oscillator is disabledPrimary oscillator is disabled CPU and Peripherals clocked using IOBCPU and Peripherals clocked using IOB OSTS, T1RUN clearedOSTS, T1RUN cleared IOFS set after 1-4 ms delay if Freq IOFS set after 1-4 ms delay if Freq 31 kHz 31 kHz

Check datasheet for INTOSC delayCheck datasheet for INTOSC delay

Adjust peripherals for new clock frequencyAdjust peripherals for new clock frequency IRCF<2:0> selects clock speed (optional)IRCF<2:0> selects clock speed (optional) IDLEN = 0 IDLEN = 0 (PIC18 only)(PIC18 only), SCS<1:0> = 1X, SCS<1:0> = 1X Execute a SLEEP instruction (PIC18 only)Execute a SLEEP instruction (PIC18 only)

Primary oscillator is disabledPrimary oscillator is disabled CPU and Peripherals clocked using IOBCPU and Peripherals clocked using IOB OSTS, T1RUN clearedOSTS, T1RUN cleared IOFS set after 1-4 ms delay if Freq IOFS set after 1-4 ms delay if Freq 31 kHz 31 kHz

Check datasheet for INTOSC delayCheck datasheet for INTOSC delay

RC_RUN ModeRC_RUN ModeRC_RUN ModeRC_RUN Mode


Power Managed Modes:Power Managed Modes:CPU Operation CPU Operation (PIC18 only)(PIC18 only)

Power Managed Modes:Power Managed Modes:CPU Operation CPU Operation (PIC18 only)(PIC18 only)

Code can disable clocks to the CPUCode can disable clocks to the CPU Stops code execution without affecting Stops code execution without affecting

peripheral operationperipheral operation CPU is in a sleep-like stateCPU is in a sleep-like state WDT, Interrupts and resets restart CPUWDT, Interrupts and resets restart CPU

Disable CPU clocks by setting the IDLEN bit Disable CPU clocks by setting the IDLEN bit (OSCCON<7>) and executing a SLEEP (OSCCON<7>) and executing a SLEEP instructioninstruction

Code can disable clocks to the CPUCode can disable clocks to the CPU Stops code execution without affecting Stops code execution without affecting

peripheral operationperipheral operation CPU is in a sleep-like stateCPU is in a sleep-like state WDT, Interrupts and resets restart CPUWDT, Interrupts and resets restart CPU

Disable CPU clocks by setting the IDLEN bit Disable CPU clocks by setting the IDLEN bit (OSCCON<7>) and executing a SLEEP (OSCCON<7>) and executing a SLEEP instructioninstruction


IDLE Modes IDLE Modes (PIC18 only)(PIC18 only)IDLE Modes IDLE Modes (PIC18 only)(PIC18 only)

Configure IDLEN (OSCCON<7>)Configure IDLEN (OSCCON<7>) Choose whether CPU is clocked or notChoose whether CPU is clocked or not Peripherals are always clockedPeripherals are always clocked Sleep mode is exception - No clocks operateSleep mode is exception - No clocks operate

Configure IDLEN (OSCCON<7>)Configure IDLEN (OSCCON<7>) Choose whether CPU is clocked or notChoose whether CPU is clocked or not Peripherals are always clockedPeripherals are always clocked Sleep mode is exception - No clocks operateSleep mode is exception - No clocks operate

CPUClocked

IDLEN Mode

Yes 0 (any)_RUN, SLEEPNo 1 (any)_IDLE


PRI_IDLE Mode PRI_IDLE Mode (PIC18 only)(PIC18 only)PRI_IDLE Mode PRI_IDLE Mode (PIC18 only)(PIC18 only)

IDLEN = 1, SCS<1:0> = 00IDLEN = 1, SCS<1:0> = 00 Execute a SLEEP instructionExecute a SLEEP instruction

CPU not clockedCPU not clocked Peripherals that need system clocks are Peripherals that need system clocks are

clocked by Primary oscillatorclocked by Primary oscillator Primary oscillator is continues to runPrimary oscillator is continues to run

IDLEN = 1, SCS<1:0> = 00IDLEN = 1, SCS<1:0> = 00 Execute a SLEEP instructionExecute a SLEEP instruction


clocked by Primary oscillatorclocked by Primary oscillator Primary oscillator is continues to runPrimary oscillator is continues to run


SEC_IDLE Mode SEC_IDLE Mode (PIC18 only)(PIC18 only)SEC_IDLE Mode SEC_IDLE Mode (PIC18 only)(PIC18 only)

Adjust peripherals for new clock frequencyAdjust peripherals for new clock frequency IDLEN = 1, SCS<1:0> = 01IDLEN = 1, SCS<1:0> = 01 Execute a SLEEP instructionExecute a SLEEP instruction


clocked by T1OSC oscillatorclocked by T1OSC oscillator Primary oscillator is disabledPrimary oscillator is disabled OSTS, IOFS clearedOSTS, IOFS cleared

T1RUN T1RUN setset

Adjust peripherals for new clock frequencyAdjust peripherals for new clock frequency IDLEN = 1, SCS<1:0> = 01IDLEN = 1, SCS<1:0> = 01 Execute a SLEEP instructionExecute a SLEEP instruction


clocked by T1OSC oscillatorclocked by T1OSC oscillator Primary oscillator is disabledPrimary oscillator is disabled OSTS, IOFS clearedOSTS, IOFS cleared

T1RUN T1RUN setset


RC_IDLE Mode RC_IDLE Mode (PIC18 only)(PIC18 only)RC_IDLE Mode RC_IDLE Mode (PIC18 only)(PIC18 only)

IDLEN = 1, SCS<1:0> = 1XIDLEN = 1, SCS<1:0> = 1X Adjust peripherals for new clock frequencyAdjust peripherals for new clock frequency Execute a SLEEP instructionExecute a SLEEP instruction


clocked by Internal Oscillator Blockclocked by Internal Oscillator Block Primary oscillator is disabledPrimary oscillator is disabled OSTS, T1RUN clearedOSTS, T1RUN cleared

IOFS may be set after delayIOFS may be set after delay

IDLEN = 1, SCS<1:0> = 1XIDLEN = 1, SCS<1:0> = 1X Adjust peripherals for new clock frequencyAdjust peripherals for new clock frequency Execute a SLEEP instructionExecute a SLEEP instruction


clocked by Internal Oscillator Blockclocked by Internal Oscillator Block Primary oscillator is disabledPrimary oscillator is disabled OSTS, T1RUN clearedOSTS, T1RUN cleared

IOFS may be set after delayIOFS may be set after delay


(any)_RUN to (same)_IDLE (any)_RUN to (same)_IDLE (PIC18 only)(PIC18 only)

(any)_RUN to (same)_IDLE (any)_RUN to (same)_IDLE (PIC18 only)(PIC18 only)

; Switch from (any)_RUN to (same)_IDLE; Switch from (any)_RUN to (same)_IDLE; Uses same clock source / frequency; Uses same clock source / frequency

bsfbsf OSCCON,IDLENOSCCON,IDLEN ; select IDLE mode; select IDLE modesleepsleep ; enters (*)_IDLE ; enters (*)_IDLE

modemode

; Execution pauses here, waits for; Execution pauses here, waits for; wake by interrupt, reset,; wake by interrupt, reset,; or WDT timeout.; or WDT timeout.

; CPU not clocked, peripherals run from; CPU not clocked, peripherals run from; same clock source (not changed).; same clock source (not changed).

; Switch from (any)_RUN to (same)_IDLE; Switch from (any)_RUN to (same)_IDLE; Uses same clock source / frequency; Uses same clock source / frequency

bsfbsf OSCCON,IDLENOSCCON,IDLEN ; select IDLE mode; select IDLE modesleepsleep ; enters (*)_IDLE ; enters (*)_IDLE

modemode

; Execution pauses here, waits for; Execution pauses here, waits for; wake by interrupt, reset,; wake by interrupt, reset,; or WDT timeout.; or WDT timeout.

; CPU not clocked, peripherals run from; CPU not clocked, peripherals run from; same clock source (not changed).; same clock source (not changed).


Exit from Power Managed Exit from Power Managed ModeMode


What wakes a device from SLEEP?What wakes a device from SLEEP?(Any controller, not just nanoWatt)(Any controller, not just nanoWatt)

What wakes a device from SLEEP?What wakes a device from SLEEP?(Any controller, not just nanoWatt)(Any controller, not just nanoWatt) Any InterruptAny Interrupt Any ResetAny Reset WDT time-outWDT time-out

Any InterruptAny Interrupt Any ResetAny Reset WDT time-outWDT time-out




On Exit by InterruptOn Exit by Interrupt Program flow is controlled GIE/GIEHProgram flow is controlled GIE/GIEH

If set, branch to ISRIf set, branch to ISR If clear, resume at next instructionIf clear, resume at next instruction

Primary clock is started (if not already running)Primary clock is started (if not already running) Automatic clock switch occurs if / when Automatic clock switch occurs if / when

Primary becomes readyPrimary becomes ready

On Exit by InterruptOn Exit by Interrupt Program flow is controlled GIE/GIEHProgram flow is controlled GIE/GIEH

If set, branch to ISRIf set, branch to ISR If clear, resume at next instructionIf clear, resume at next instruction

Primary clock is started (if not already running)Primary clock is started (if not already running) Automatic clock switch occurs if / when Automatic clock switch occurs if / when

Primary becomes readyPrimary becomes ready




On Exit by InterruptOn Exit by Interrupt CPU and peripherals are clocked using CPU and peripherals are clocked using

selected clock until Primary becomes readyselected clock until Primary becomes ready Exit from SLEEP mode:Exit from SLEEP mode:

No clock is selected, execution resumes No clock is selected, execution resumes when Primary becomes readywhen Primary becomes ready

Execution can begin immediately if either Execution can begin immediately if either Two-Speed Startup or Fail-Safe Clock Two-Speed Startup or Fail-Safe Clock Monitor is enabledMonitor is enabled

On Exit by InterruptOn Exit by Interrupt CPU and peripherals are clocked using CPU and peripherals are clocked using

selected clock until Primary becomes readyselected clock until Primary becomes ready Exit from SLEEP mode:Exit from SLEEP mode:

No clock is selected, execution resumes No clock is selected, execution resumes when Primary becomes readywhen Primary becomes ready





On Exit by ResetOn Exit by Reset Primary clock is startedPrimary clock is started Execution pauses until Primary becomes readyExecution pauses until Primary becomes ready


OSTS bit in OSCCON register is set when OSTS bit in OSCCON register is set when Primary is providing system clocksPrimary is providing system clocks

On Exit by ResetOn Exit by Reset Primary clock is startedPrimary clock is started Execution pauses until Primary becomes readyExecution pauses until Primary becomes ready


OSTS bit in OSCCON register is set when OSTS bit in OSCCON register is set when Primary is providing system clocksPrimary is providing system clocks




On Exit by WDT Time-outOn Exit by WDT Time-out On Exit by WDT Time-outOn Exit by WDT Time-out

Reset if in any RUN modeReset if in any RUN mode(CPU clocked, executing code)(CPU clocked, executing code)

Wake if in SLEEP or any IDLE modeWake if in SLEEP or any IDLE mode(CPU not clocked, not executing code)(CPU not clocked, not executing code)

Reset if in any RUN modeReset if in any RUN mode(CPU clocked, executing code)(CPU clocked, executing code)

Wake if in SLEEP or any IDLE modeWake if in SLEEP or any IDLE mode(CPU not clocked, not executing code)(CPU not clocked, not executing code)

TO bit is clearedTO bit is cleared PIC16 - STATUS<4>PIC16 - STATUS<4>PIC18 - RCON<3>PIC18 - RCON<3>

Exit process depends on if CPU was executing Exit process depends on if CPU was executing codecode

TO bit is clearedTO bit is cleared PIC16 - STATUS<4>PIC16 - STATUS<4>PIC18 - RCON<3>PIC18 - RCON<3>

Exit process depends on if CPU was executing Exit process depends on if CPU was executing codecode


Lab ExercisesLab ExercisesLab ExercisesLab Exercises

Please choose a device to usePlease choose a device to use

for the labs that follow:for the labs that follow:

PIC16F88PIC16F88

oror

PIC18F1320PIC18F1320

Please choose a device to usePlease choose a device to use

for the labs that follow:for the labs that follow:

PIC16F88PIC16F88

oror

PIC18F1320PIC18F1320


Lab #1 -Lab #1 -Fail-Safe Clock MonitorFail-Safe Clock Monitor

Lab #1 -Lab #1 -Fail-Safe Clock MonitorFail-Safe Clock Monitor

Configure code for 8 MHz Canned Oscillator.Configure code for 8 MHz Canned Oscillator. Write code to handle Fail-Safe interrupt. Write code to handle Fail-Safe interrupt. When the Fail-Safe interrupt occurs, the code When the Fail-Safe interrupt occurs, the code

should operate as before the Fail-Safe should operate as before the Fail-Safe condition was detected.condition was detected.

Hints:Hints:

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Configure code for 8 MHz Canned Oscillator.Configure code for 8 MHz Canned Oscillator. Write code to handle Fail-Safe interrupt. Write code to handle Fail-Safe interrupt. When the Fail-Safe interrupt occurs, the code When the Fail-Safe interrupt occurs, the code

should operate as before the Fail-Safe should operate as before the Fail-Safe condition was detected.condition was detected.

Hints:Hints:

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Lab #2 - Clock SwitchingLab #2 - Clock SwitchingLab #2 - Clock SwitchingLab #2 - Clock Switching

Configure the clock system to minimize current Configure the clock system to minimize current consumption.consumption.

Communication to the I/O expander (and LCD) Communication to the I/O expander (and LCD) cannot be affected.cannot be affected.

Measure IMeasure IDDDD

Hints:Hints:

________________________________________

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Configure the clock system to minimize current Configure the clock system to minimize current consumption.consumption.

Communication to the I/O expander (and LCD) Communication to the I/O expander (and LCD) cannot be affected.cannot be affected.


Hints:Hints:

________________________________________

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Lab #3 - Analog I/O Pin Lab #3 - Analog I/O Pin Lab #3 - Analog I/O Pin Lab #3 - Analog I/O Pin

Write code in the Voltmeter block that Write code in the Voltmeter block that minimizes current consumption.minimizes current consumption.


Hints:Hints:

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Write code in the Voltmeter block that Write code in the Voltmeter block that minimizes current consumption.minimizes current consumption.


Hints:Hints:

________________________________________

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Lab #4 - CommunicationLab #4 - CommunicationLab #4 - CommunicationLab #4 - Communication

Review the PICDEM™ 4 SchematicReview the PICDEM™ 4 Schematic Write code in the AUSART block that Write code in the AUSART block that

minimizes current consumption.minimizes current consumption. Measure IMeasure IDDDD

Hints:Hints:

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Review the PICDEM™ 4 SchematicReview the PICDEM™ 4 Schematic Write code in the AUSART block that Write code in the AUSART block that

minimizes current consumption.minimizes current consumption. Measure IMeasure IDDDD

Hints:Hints:

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Lab #5 - Real Time ClockLab #5 - Real Time ClockLab #5 - Real Time ClockLab #5 - Real Time Clock

Write code within the Timer 1 block that Write code within the Timer 1 block that minimizes current consumption.minimizes current consumption.


Hints:Hints:

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Write code within the Timer 1 block that Write code within the Timer 1 block that minimizes current consumption.minimizes current consumption.


Hints:Hints:

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