Micro Electro Mechanical Systems (MEMS) - Lecture 07

23
Department of Instrumentation & Control Engineering, MIT, Manipal Lecture #07 Basics of CMOS 1

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Micro Electro Mechanical Systems (MEMS)

Transcript of Micro Electro Mechanical Systems (MEMS) - Lecture 07

Page 1: Micro Electro Mechanical Systems (MEMS) - Lecture 07

Department of Instrumentation & Control Engineering, MIT, Manipal

Lecture #07

Basics of CMOS

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Page 2: Micro Electro Mechanical Systems (MEMS) - Lecture 07

Department of Instrumentation & Control Engineering, MIT, Manipal

Contents

1. Introduction – Transistor Types

2. Silicon Lattice

3. Dopants

4. p n Junction Diodes

5. n MOS Transistors

6. p MOS Transistors

7. Transistors as Switches

8. CMOS Inverters and NAND Gates

9. Compound Gates

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Page 3: Micro Electro Mechanical Systems (MEMS) - Lecture 07

Introduction – Transistor Types

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• Bipolar transistors

– npn or pnp silicon structure

– Small current into very thin base layer controls large currents between emitter and collector

– Base currents limit integration density (power dissipation issue)

• Metal Oxide Semiconductor Field Effect Transistors

– nMOS and pMOS MOSFETs

– Voltage applied to insulated gate controls current between source and drain

– Low power allows very high integration (ideally zero static power)

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

Page 4: Micro Electro Mechanical Systems (MEMS) - Lecture 07

Silicon Lattice

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• Transistors are built on a silicon substrate

• Silicon is a Group IV material

• Forms crystal lattice with bonds to four neighbours

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

Si SiSi

Si SiSi

Si SiSi

Page 5: Micro Electro Mechanical Systems (MEMS) - Lecture 07

Dopants

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• Silicon is a semiconductor

• Pure silicon has no free carriers and conducts poorly

• Adding dopants increases the conductivity

• Group V (Arsenic): extra electron (n-type)

• Group III (Boron): missing electron, called hole (p-type)

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-

Page 6: Micro Electro Mechanical Systems (MEMS) - Lecture 07

p n Junctions

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• A junction between p-type and n-type semiconductor forms adiode.

• Current flows only in one direction

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

p-type n-type

anode cathode

Page 7: Micro Electro Mechanical Systems (MEMS) - Lecture 07

nMOS Transistors

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• Four terminals: gate, source, drain, body

• Gate – oxide – body stack looks like a capacitor

– Gate and body are conductors

– SiO2 (oxide) is a very good insulator

– Called metal – oxide – semiconductor (MOS) capacitor

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

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nMOS Operation

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• Body is commonly tied to ground (0 V)

• When the gate is at a low voltage:

– P-type body is at low voltage

– Source-body and drain-body diodes are OFF

– No current flows, transistor is OFF

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S

Page 9: Micro Electro Mechanical Systems (MEMS) - Lecture 07

nMOS Operation Contd…

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• When the gate is at a high voltage:

– Positive charge on gate of MOS capacitor

– Negative charge attracted to body

– Inserts a channel under gate to n-type

– Now current can flow through n-type silicon from source

through channel to drain, transistor is ON

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S

Page 10: Micro Electro Mechanical Systems (MEMS) - Lecture 07

pMOS Operation

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• Similar, but doping and voltages reversed

– Body tied to high voltage (VDD)

– Gate low: transistor ON

– Gate high: transistor OFF

– Bubble indicates inverted behavior

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+

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Power Supply Voltage

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• GND = 0 V

• In 1980’s, VDD = 5V

• VDD has decreased in modern processes due to scaling

– High VDD would damage modern tiny transistors

– Lower VDD saves power (Dynamic power is proportional to

C.VDD2.f.a)

• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

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Transistors as Switches

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• We can view MOS transistors as electrically controlled

switches

• Voltage at gate controls path from source to drain

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFFON

ONOFF

Page 13: Micro Electro Mechanical Systems (MEMS) - Lecture 07

CMOS Inverter

13S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A Y

0

1

VDD

A Y

GNDA Y

Page 14: Micro Electro Mechanical Systems (MEMS) - Lecture 07

CMOS Inverter

14S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A Y

0 1

1 0

VDD

A=0 Y=1

GND

OFF

ON

A Y

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CMOS Inverter

15S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A Y

0 1

1 0

VDD

A=1 Y=0

GND

ON

OFF

A Y

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CMOS NAND Gate

16S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A B Y

0 0

0 1

1 0

1 1

A

B

Y

Page 17: Micro Electro Mechanical Systems (MEMS) - Lecture 07

CMOS NAND Gate

17S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A B Y

0 0 1

0 1

1 0

1 1

A=0

B=0

Y=1

OFF

ON ON

OFF

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CMOS NAND Gate

18S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A B Y

0 0 1

0 1 1

1 0

1 1

A=0

B=1

Y=1

OFF

OFF ON

ON

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CMOS NAND Gate

19S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A B Y

0 0 1

0 1 1

1 0 1

1 1

A=1

B=0

Y=1

ON

ON OFF

OFF

Page 20: Micro Electro Mechanical Systems (MEMS) - Lecture 07

CMOS NAND Gate

20S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

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Series and Parallel

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• nMOS: 1 = ON

• pMOS: 0 = ON

• Series: both must be ON

• Parallel: either can be ON

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

(a)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

OFF OFF OFF ON

(b)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

ON OFF OFF OFF

(c)

a

b

a

b

g1 g2 0 0

OFF ON ON ON

(d) ON ON ON OFF

a

b

0

a

b

1

a

b

11 0 1

a

b

0 0

a

b

0

a

b

1

a

b

11 0 1

a

b

g1 g2

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Compound Gates

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• Compound gates can do any inverting function

• Ex:

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

(AND-AND-OR-INVERT, AOI22)Y A B C D= +i i

A

B

C

D

A

B

C

D

A B C DA B

C D

B

D

YA

CA

C

A

B

C

D

B

D

Y

(a)

(c)

(e)

(b)

(d)

(f)

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Compound Gates

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• O3AI

• Ex:

S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

( )Y A B C D= + + i

A B

Y

C

D

DC

B

A