8051 Interfacing: Address Map Generation

EE4380 Fall02Class 6

Pari vallal KannanCenter for Integrated Circuits and SystemsUniversity of Texas at Dallas

8051 Interfacing

Address Mapping– Use address bus and data bus

– Interfaced device show up as memory locations from the processor

– They use up some of the address space

– Memories, displays etc

I/O Mapping– Connect the devices to the I/O Ports of the processor

– Don’t use up address space

– Sensors, pushbuttons, LCDs, motors, LEDs etc

212-Sep-02

8051 – Address Generator

Address Generator is a piece of hardware that produces unique addresses to each interfaced deviceEach Interfaced Device can use up 1 or more locations from the address space of the processor

Device 1 A[15:0]

f1 Addr. Gen f2

f3

8051 Device 2D[7:0]

A[15:0]– Memories typically use up in

Kilobytes (2K, 4K, 8K etc) D[7:0]D[7:0]

– Other devices typically use a Device 3A[15:0]A[15:0]few (<16) addresses CE

CECE

D[7:0]Addresses of devices should not overlap

312-Sep-02

What is needed ?

Need to know the following for all the devices before address generator can be designed LCD 8b

LEd 2b

– Base address of each device Code RAM 4K

RAM1 32K

Where it starts in the address map 0x1000

0x5000Code ROM1 4K0x00000x4000

0x00000x80000xF000

– Size of the device Code Memory Data MemoryHow much of the address

space it uses up

412-Sep-02

Example –1 : 2K Memory at 0x0000

Pins : address - A10 to A0, Data – D7 to D0, _RD, _WR, _CEBase address = 0x0000 Size = 2k (2 *1024 = 2048 bytes = 0x0800)Address Map occupancy

– 0x0000 to 0x07FF that is,– 0000 - 0000 - 0000 - 0000 binary to– 0000 - 0111 - 1111 - 1111 binary

11 lowest address bits A10 to A0 have to be connected to the address pins on the memory

512-Sep-02

Example –1 : (contd.)

Unused address bits are Truth-Table for CE– A15 to A11

Base address is 0x0000CE has to be generated if all the unused address bits are logic-0

_CEA11A12A13A14A15 011111

01

0000XXXX

XXX

XX

X XXXX

1XXX

1– CE is active lowXX

_CE = A15 + A14 + A13 + A12 + A11Then connect _RD and _WR

1X1

612-Sep-02

Ex-2: Same Memory at 0x4000

Base address is 0x4000 _CEA11A12A13A14A15

101111111

011111

– 0100 0000 0000 0000 XXXX 00101

Size is 2KUnused address bits

000 XXXX

XXXX

XX11

– A15 to A11

CE has to be generated as per the truth-tableExpression is

onsoand

1112131415_ AAAAACE ••••=

712-Sep-02

(In)Complete AddressingComplete addressing:– Use all unused address bits to generate CE

Incomplete addressing– Use a sub-set of the unused address bits– Used to reduce the address generator complexity– Produces address aliases (same device at multiple addresses)

Example– 2K memory at 0x0000, we used A15 to A11– Instead just connect A11 to _CE– Same 2K memory device will then be aliased for all values of

A15 to A120x0000, 0x1000, 0x2000, 0x3000, …. , 0xF000

– Address generator became very simple, but we lost a lot of address space

812-Sep-02

74138 Decoder for Address Gen.

3 to 8 decoder, available in a single DIP package.Takes 3 address lines and generates complete addressing among thoseExample

CBA

Y0Y1Y2

A15A14A13

G2G1

GNDVcc

– Connect A15, A14, A13 to the Y7decoder inputs

– Decoder outputs give base 74LS138addresses for

0x0000, 0x2000, 0x4000, 0x6000, 0x8000, 0xA000, 0xC000, 0xE000

For more complicated address decoding use programmable devices like PALs, PLDs or FPGAs

912-Sep-02

External (pure) Code Memory

Could be RAM or ROMAddress generation as per standard procedureConnect _PSEN to the _OE of the memory device_RD and _WR are ignored

– Don’t connect these 8051 pins to the memory device

Connect Data bits D7-D0 of the memory and the 8051

1012-Sep-02

External (pure) Data Memory

Could be RAM or ROMAddress generation as per standard procedureConnect _RD from the 8051 to OE of the memoryConnect _WR from the 8051 to WR of the memoryIgnore _PSENConnect Data bits D7-D0 of the memory and the 8051

1112-Sep-02

External Code + Data Memory

Could be RAM or ROMAddress generation as per standard procedureLogically AND _PSEN and _RD and then connect to the OE of the memoryConnect _WR from the 8051 to WR of the memoryConnect Data bits D7-D0 of the memory and the 8051

1212-Sep-02

External Non-Memory Devices

Same procedure as for interfacing memoryOnly difference is that these devices have smaller sizes and use lesser portions of the address spaceExample:

– 8 LEDS connected to a 8bit latch. The latch is address mapped to 0xF000. Size is 1byte

– 8255 I/O device memory mapped at 0xD000. Size is 4 bytes

1312-Sep-02

Case Study - Sample 8051 System

1412-Sep-02

Case study – Sample 8051 System8031 based– No on-chip ROM, 128 bytes on -chip RAM, 18.432MHz oscillator,

74HC373 based ADBUS demuxer– 8Kx8 external code memory in 28C64 EEPROM– Code memory at 0x0000– 32Kx8 external code+data overlapped in 62256 SRAM.– SRAM mapped at 0x8000

SRAM and EEPROM share code memory space. So decoding needed. – A15 line is used for the purpose– A15 = 0 EEPROM is selected (hence 0x0000)– A15 = 1 SRAM is selected (hence 0x8000)

RS232 serial interface available for PC communicationMonitor programs available

1512-Sep-02

Reverse Engineering

Given a system with little or no docs, determine the function, schematic, etcVendors provide poor support.Reverse Engineering is fun !Usually No schematics are availableSoftware is also undocumented !On-chip code could be copy protected !!

1612-Sep-02

Next Class

8051 I/O Mapped interfacing8051 and the 8255 I/O deviceExample – Interfacing a character LCD

1712-Sep-02