IEEE Micro

ABOUr 1HE COVERIn late 1975 a small group was formed

at Intel to develop a high-end microcom-puter system. That group's early focuswas the long-term relationship betweencomputer architecture and VLSI semi-conductor technology. Recognizing thatthe functional densities of MOS inte-grated circuits are increasing by a factorof two to three every two years, the groupperceived that they could design a VLSIcomputer system that would gracefullyabsorb rapid improvements in semicon-ductor technology without requiring con-tinual changes in its basic architecture.The result of this perception is three VLSIchips-one with 110,000 transistors and adie size of 320 mil2, one with 49,000 tran-sistors and a die size of 338 mil2, and onewith 60,000 transistors and a die size of341 mil2 (pictured on this month's cover).These chips are designed for a multipleprocessor system that can achieve a perfor-mance equal to a midrange mainframecomputer.

Figure 1, showing the number ofMOSdevices on a microcomputer chip in rela-tionship to the year of introduction, dem-onstrates the rapid increase in functionaldensities in the last few years. This in-crease is caused by three forces workingsimultaneously:

* general improvements in semicon-ductor manufacturing technology,

* the use of regular structures and mi-crocode in the design of micropro-

cessor chips, and* the recognition that an architecture

can grow to take advantage of rapidimprovements in functional densities.

These forces give new generations of mi-croprocessors larger die sizes, higherclock rates, and more architectural fea-tures than ever before, as the iAPX 432shows (Table 1). Since this microproces-

cont'd on page 6

Figure 1. Transistors per CPU vs. year ofintroduction.

Table 1.A 32-bit microcomputer provides greater functionality than a 16-bit system.

iAPX 432FUNCTIONALITY

ADDRESS SPACEINSTANTANEOUSVIRTUAL

DATA TYPES

INSTRUCTIONSET

1/0

PROTECTION

2322408, 16, 32, 64 AND 80-BITBOOLEAN, CHARACTERORDINAL, INTEGER, REALLONG ORDINAL, INTEGER, REALHIGH LEVEL (e.g., A=B+C)MULTIOPERAND (0-3)VECTOR, RECORDINDEPENDENTPARALLELFINELY GRAINEDPER DATA STRUCTURE

TYPICAL 16-BITFUNCTIONALITY

216 - 218NO SUPPORT8, 16-BITBOOLEAN, CHARACTERORDINAL, INTEGER

ASSEMBLY LEVELTWO-OPERANDREGISTER-BASEDDEPENDENTSLAVEDCOARSESUPERVISOR/USER

Senior EditorRichard C. Jaeger

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sor provides a level of functionalitypreviously associated only with main-frame computers, the developers coined anew term for it-"micromainframe."

The three-chip set comprises approx-imately 225,000 MOS devices and repre-sents over 100 man-years of design andlayout effort. A two-chip general dataprocessor performs instruction decoding,address generation, and data manipula-tion. It provides a virtual address space of240 bytes and a physical address space of224 bytes. The third chip (pictured on thecover) is an interface processor that pro-vides a bridge from an 1/0 subsystem tothe protected access environment of thecentral system. An 1/0 subsystem uses an8- or 16-bit microprocessor as an attachedprocessor, thus making 1/0 completely in-dependent of the central system (Figure 2).

Design methods. The iAPX 432 repre-sents one of the largest single programsever undertaken by Intel. To accomplishit, the company developed a new ap-proach to chip design called "large chipmethodology."

A large project like the iAPX 432 pro-gram requires special documentation, newdesign practices, and new CAD tools. Themajor problem with implementing suchcomplex systems on silicon is that describ-ing, understanding, analyzing, and de-signing complex VLSI circuits involve atleast five conceptual levels. Each level ischaracterized by a distinct language forrepresenting its elements (Table 2) andeach level has its own data base and its ownprimary CAD tool. In the iAPX 432 pro-gram, the CAD tools were focused at two

areas-reducing errors within a descrip-tion level and reducing errors when trans-lating between description levels. The fol-lowing tools were developed and used ateach level:

* macrosimulator-to simulate thebasic architecture;

* microsimulator-to simulate themicroarchitecture of the machine;

* logic simulator-to simulate themachine at the logic level;

* circuit-level simulator-to simulatethe circuits; and

* mask-level description-to describethe basic devices generated at theabove levels.

Each level has programs to check forerrors within that level. The development

Table 2.The five conceptual levels fordescribing, understanding, andanalyzing complex VLSI circuits.

LEVEL

ARCHITECTURAL

JiARCH ITECTU RAL

LOGICAL

PHYSICAL

MASK

DATA BASETEXT AND PICTURES

REGISTER TRANSFERDESCRIPTION

UNSIZED SCHEMATICDESCRIPTION

SIZED SCHEMATICDESCRIPTION

DIGITIZED MASKDESCRIPTION

Figure 2. Microarchitecture of a 32-bit iAPX 432-based "micromainframe" system.

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group also devised programs to check be-tween levels.

Table 3 outlines the group's experiencewith the large chip methodology. Eachsuccessive design became more regular,had higher layout productivity, and fewererrors. -

This is an edited version ofapaperpre-sented on February 18, 1981, at the Inter-national Solid-State Circuits Conference;a shorter version appeared in the ISSCCDigest of Technical Papers. The presenterwas William W. Lattin of Intel Corpora-tion; members of the iAPX 432 develop-ment group included Lattin, John A. Bay-liss, David L. Budde, Stephen R. Collev,George W. Cox, Allan L. Goodman, Jus-tin R. Rattner, William S. Richardson,and Roger C. Swanson.

Cover photo is courtesy ofJim Jarrett,Intel Corporation.

Table 3.Intel's experience with large chip methodology, as demonstrated by the

design of the three chips for the iAPX 432.

432/01 432/02 432/03DIE SIZE (MILS) 318x323 366x313 358x326TOTAL DEVICEPLACEMENTS llOK 49K 60KTOTAL ACTUALDEVICES

DRAWN DEVICES

NO OF SCHEMATICS

LAYOUT PRODUCTIVITY(DRAWN DEVICES)

(MAN-DAY)FATAL LAYOUT ERRORS

ON FIRST LINE CHECK

FATAL LAYOUT ERRORSON SECOND LINE CHECK

FATAL LAYOUT ERRORSON THIRD LINE CHECK

LAYOUT ERRORSON FIRST STEPPING

LAYOUT ERRORSON SECOND STEPPING

60K

5591

39

2 79

274

133

10

10

37K

9500

64

3.97

49K

5700

52

5.10

170 CVS*

29

CVS *

2 0

5

'CVS indicates the use of a CAD tool to compare the mask descriptionagainst the logic description (i e. the schematic)

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