MICE Tracker Readout Update
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Transcript of MICE Tracker Readout Update
1
MICE Tracker Readout Update• Introduction/Overview• TriP-t hardware tests• AFE IIt firmware development• VLSB firmware development• Hardware progress• Summary
Terry Hart, MICE CM 18, June 13, 2007
2
MICE Tracker Acronyms
• AFE IIt – Analog Front End, Version II, with time
• VLSB – VME LVDS Serdes Buffer– Versa Module Eurocard– Low Voltage Differential Signalling– Serialing/Deserializing
• FPGA – Field Programmable Gate Array
• TriP-t – Trigger with Pipeline with time
• VLPC – Visible Light Photon Counter
Terry Hart, MICE CM 18, June 13, 2007
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Tracker Data Readout Basics
DFPGA
AFPGA AFPGA
ADC ADC ADC ADC
TriP-t TriP-t TriP-t TriP-t
1/4 of AFE-IIt
Data from VLPCs
X 4 …
X 4 …
X 4 …
X 4 …
X 4 …1/4 of VLSB Memory Bank
Trigger and Pipeline chips - Sends bitmaps to DFPGA - Stores raw data in pipeline until receipt of MICE event trigger
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Tracker Data Readout Basics
DFPGA
AFPGA AFPGA
ADC ADC ADC ADC
TriP-t TriP-t TriP-t TriP-t
1/4 of AFE-IIt
Data from VLPCs
X 4 …
X 4 …
X 4 …
X 4 …
X 4 …1/4 of VLSB Memory Bank
Trigger and Pipeline chips - Sends bitmaps to DFPGA - Stores raw data in pipeline until receipt of MICE event trigger
Event Trigger(L1ACCEPT)
Analog FPGA Controls operation of TriP-t’s and ADCs.
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Tracker Data Readout Basics
DFPGA
AFPGA AFPGA
ADC ADC ADC ADC
TriP-t TriP-t TriP-t TriP-t
1/4 of AFE-IIt
Data from VLPCs
X 4 …
X 4 …
X 4 …
X 4 …
X 4 …1/4 of VLSB Memory Bank
Analog to Digital Converters Digitizes raw charge and time data
Trigger and Pipeline chips - Sends bitmaps to DFPGA - Stores raw data in pipeline until receipt of MICE event trigger
Event Trigger(L1ACCEPT)
Analog FPGA Controls operation of TriP-t’s and ADCs.
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Tracker Data Readout Basics
DFPGA
AFPGA AFPGA
ADC ADC ADC ADC
TriP-t TriP-t TriP-t TriP-t
1/4 of AFE-IIt
Data from VLPCs
X 4 …
X 4 …
X 4 …
X 4 …
X 4 …1/4 of VLSB Memory Bank
Analog FPGA Controls operation of TriP-t’s and ADCs.
Digital FPGA Sets data protocol for - Bitmaps to AFPGA - Data from AFPGA
Analog to Digital Converters Digitizes raw charge and time data
Trigger and Pipeline chips - Sends bitmaps to DFPGA - Stores raw data in pipeline until receipt of MICE event trigger
Event Trigger(L1ACCEPT)
7
Tracker Data Readout Basics
DFPGA
AFPGA AFPGA
ADC ADC ADC ADC
TriP-t TriP-t TriP-t TriP-t
1/4 of AFE-IIt
Data from VLPCs
X 4 …
X 4 …
X 4 …
X 4 …
X 4 …1/4 of VLSB Memory Bank
Analog to Digital Converters Digitizes raw charge and time data
Formatted Data to VLSB Memory Banks
Trigger and Pipeline chips - Sends bitmaps to DFPGA - Stores raw data in pipeline until receipt of MICE event trigger
Digital FPGA Sets data protocol for - Bitmaps to AFPGA - Data from AFPGA
Analog FPGA Controls TriP-t and ADC operation.
Event Trigger(L1ACCEPT)
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AFE IIt/TriP-t Basics• For MICE, average time between triggers ~ 1700 ns,
but can be as short as 628 ns. (ISIS beam structure and MICE DAQ constraints)
• TriP-t chips– Pipeline stores analog charge and time data.
• L1ACCEPT event trigger takes time (~ 1000 ns) to be formed.
• Time to digitize analog data ~ 1500 – 2000 ns.
– Upon L1ACCEPT trigger, data is taken from pipeline and either • Digitized if 4-level buffer is empty or
• Placed in 4-level buffer if digitization of previous event not yet done
Terry Hart, MICE CM 18, June 13, 2007
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D0 AFE IIt firmware doesn’t
1. Implement TriP-t 4-level analog buffer.
2. Run data pipeline while ADCs digitize data.
TriP-t Modifications for MICE
Firmware modified to do these, but hardware tests needed to ensure that TriP-tchips operate as expected.
Terry Hart, MICE CM 18, June 13, 2007
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Hardware Tests of Increasing Fraction of Recorded Muons
• Completed TriP-t test stand– DG2020 Signal Generator– 2 Tektronix P3420 Variable Level Pods– Test board containing TriP-t chip
• Fed signals into TriP-t test board.
First results: TriP-t seems to function with input zero suppression signal sequence .
Next steps: - Check output signal integrity to see if input signals were digitized. - Check if buffering events works.
[Reported at MICE Collaboration Meeting, Feb. 22, 2007]
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Signal Inputs
Program Interface Signals
Pipeline Control Signals
TriP-t Chip
Preamplifier Signals
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TriP-t Output
0.8
0.9
1
1.1
1.2
1.3
1.4
0.00E+00 1.00E-06 2.00E-06 3.00E-06 4.00E-06 5.00E-06 6.00E-06 7.00E-06 8.00E-06
Time (sec)
Vo
ltag
e (V
)
Series1
PR1 (Pipeline Readout)
-0.1
0.4
0.9
1.4
1.9
2.4
2.9
0.00E+00 1.00E-06 2.00E-06 3.00E-06 4.00E-06 5.00E-06 6.00E-06 7.00E-06 8.00E-06
Time (sec)
Vo
lta
ge
(V
)
Series1
Channel Inputs4 channels in gate #1 (1,15,16,31)3 channels in gate #2 (1,15,31)3 channels in gate #3 (15,16,31)3 channels in gate #4 (1,16,31)
• Charges injected at four 324 ns intervals • Data placed in 4-level buffer
• PR1 starts pipeline readout
• Analog outputs from pipeline are correct
• Digitization times - 4 channels => 2268 ns - 3 channels => 1620 ns
2.268 µs 1.620 µs 1.620 µs 1.620 µs
2.268 µs 1.620 µs 1.620 µs 1.620 µs
1 15,16 31 1 15 31 15,16 31 1 16 31
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TriP-t Hardware Test Summary
• Test stand has demonstrated that TriP-t can
– Run pipeline while ADCs digitize raw data
– Store data in 4-level analog pipeline for later readout
Terry Hart, MICE CM 18, June 13, 2007
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AFE IIt Firmware Modifications
Modifications needed for data buffering
– Shorten time to digitize data• Zero suppression• End digitization series after last channel
above threshold These are done.
– Protocol for data transfers between DFPGA and AFPGA
• Bitmaps from DFPGA to AFPGA• Digitized data from AFPGA to DFPGA This is nearly done.
– Buffer triggers in DFPGA FIFO This is nearly done.
DFPGA
AFPGA AFPGA
ADC ADC ADC ADC
TriP-t TriP-t TriP-t TriP-t
Data from VLPCs
Memory Bank
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Immediate AFE IIt Firmware Tasks
• Synthesize AFGPA and DFPGA firmware modifications.– FNAL concentrating of AFPGA– RAL concentrating on DFPGA
• Test operation of entire board.– Check that modified firmware is compatible with
existing firmware.
Terry Hart, MICE CM 18, June 13, 2007
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VLSB Firmware• VLSB = VME LVDS Serdes Buffer
– Tracker data storage modules– Used for KEK test beam– Used by D0 for diagnostics
• Modifications for MICE– Event counter during spill
Should be straightforward
– Fast clear of VLSB memory
Should be straightforward
– Overwrite memory addresses when there’s null data so that data are stored in continuous memory blocks.
Initial code formulated to be tested
– Enable Direct Memory Access block transfers
Done
AFPGA controls ADC andTriP-t operation
DFPGAdirects
DFPGA and AFPGAdata flow
VLSBmemory banks storingcharge and time data
Done
Terry Hart, MICE CM 18, June 13, 2007
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Hardware Updates
• VLSB Boards– 9 boards are built (to be spares), – 15 more to be made.– Need 8 new production VLSB boards by August 1.
• AFE IIt boards/Cryostat– Data taken for 2 of 4 production cryostats– More details in Alan’s talk
Terry Hart, MICE CM 18, June 13, 2007
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Fallback for Tracker Readout• DAQ goal: Keep up with 600 kHz trigger rate.
• At start of MICE in Aug./Sept., original firmware is sufficient for initial low data rate.
• With TriP-t zero-suppression, tracker can keep up with almost 300 kHz now.
• Late June/early July: target time for firmware capable of keeping pace with 600 kHz trigger rate.
Terry Hart, MICE CM 18, June 13, 2007
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No Buffering
1-level Buffering2-level Buffering3-level Buffering4-level Buffering
Where we are.
1000 2000 3000 4000
120
0
240
360
480
600
Recordable Muon Rate (kHz)
Digitization Time (ns)
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TriP-t/ADC Control
Firmware
Hardware tests
DFPGA/AFPGA I/O Bus
Board test at 53.104 MHz
Board test at 55 MHz
Simulations at different frequencies
Data transfer protocol
AFPGA Firmware
Write firmware controlling bitmap transfers
Test pipeline/buffer operation
Test mode development
DFPGA Firmware
Make 4-level trigger buffer
Data format
VLSB Firmware
Event aggregation (VLSB)
Data block transfer
Fast clear of memory banks
Suppress writing zeros to memory
VLSB Board Manufacture (13 boards)
AFE IIt Board Preparation
Repairs for MICE
Firmware and hardware modifications
Board characterization in cryostats
Ship cryos/boards to RAL
Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec
Done
Done
Done
Done
Done
Conservative simulations indicate this is marginal
Conservative simulations this is marginal
Done
Done
Standalone routine written
Feedback loop testing previous version
Should be quick
Initial code written, needs to be tested
Low to middle priority
Follow up on existing MOU
Ongoing
Ongoing
Ongoing
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Summary
• TriP-t operation tested and verified to work
• AFE IIt firmware development to enable trigger buffering almost done.
• VLSB firmware development almost done.
Terry Hart, MICE CM 18, June 13, 2007