MICE III 68000/20/30
description
Transcript of MICE III 68000/20/30
MICE III 68000/20/30
MICETEK International Inc.
CPU
MICEIII
MICEView
Examples
Contents
Part 1: An introduction to the MC68000 ,MC68020 and 68030
Part 2: An introduction to MICE III 68000/20/30
Part 3: MICE III debug software, MICEView Part 4: Examples
CPU
MICEIII
MICEView
Examples
Part 1A: An introduction to the MC68000, MC68020 and 68030
Object Code Compatible with Earlier M68000 Microprocessors Complete 32-Bit Nonmultiplexed Address and Data Buses 16 32-Bit General-Purpose Data and Address Registers Two 32-Bit Supervisor Stack Pointers and 10 Special-Purpose Control
Registers 256-Byte Instruction Cache and 256-Byte Data Cache(68030 only) Can
Be Accessed Simultaneously Paged MMU that Translates Addresses in Parallel with Instruction
Execution and Internal Two Transparent Segments Allow Untranslated Access to Physical
Memory To Be Defined for Systems That Transfer Large Blocks of Data between Predefined Physical Addresses e.g., Graphics Applications
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MICEIII
MICEView
Examples
Part 1B: An introduction to the MC68020 and 68030
Pipelined Architecture with Increased Parallelism Allows Accesses to Internal Caches To Occur in Parallel with Bus Transfers and Instruction Execution To Be Overlapped
Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum), Synchronous Bus Cycles (two clocks minimum), and Burst Data Transfers (one clock minimum) all to the Physical Address Space
Dynamic Bus Sizing Supports 8-, 16-, 32-Bit Memories and Peripherals Support for Coprocessors with the M68000 Coprocessor Interface e.g.,
Full IEEE Floating-Point Support Provided by the MC68881/MC68882 Floating-Point Coprocessors
4-Gbyte Logical and Physical Addressing Range Processor Speeds:16.67, 20, 25 and 33 MHz
CPU
MICEIII
MICEView
Examples
Part 2: An introduction to MICE III 68000/ 68020/68030
Hardware structure Main features Set up
CPU
MICEIII
MICEView
Examples
2-1 Hardware structure
Main Chassis:1. Emulation Processor Module (EPM)2. Logic Analyzer Module (LAM/LAM- IIS)3. Emulation Memory Module (EMM/HEMM)4. Control Process Module (CPM)
EPOD 68000/68020/68030
Target Header 68000/ 68020/68030
CPU
MICEIII
MICEView
Examples
2-2A Main features
Real-Time Emulation– Up to 25 MHz no-wait-state operation from target memory– Auto-detection of target clock– Multi-processor Start/Stop synchronization control– PGA probe tip standard– Fully supports 68881/68882 coprocessor– Keyboard enable/disable of BERR/IPL0-
2,CDIS,MMUDIS,BR and CBACK control signals– Supports different processors by simply changing the
Emulator Personality Board
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MICEIII
MICEView
Examples
2-2B Main features
Real-Time Trace– 2K/32K-frame trace buffer with address,data,status,8-bit
external probe and time stamp. Time stamp resolution of 1uS to 10mS (Maximum duration at 10mS is 44 hours)
– PRE, POET CENTER trigger location– Use address and status qualifiers to trace only selected
bus cycles– Go/Run command provides logic-analyzer-like access to
the trace buffer during full-speed emulation– Trace buffer can be display as disassembled code or bus
cycle
CPU
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MICEView
Examples
2-2C Main features
Five/Seven Real-Time Hardware Breakpoints– Two/four bus breakpoints can be used to halt the CPU on
read,write,fetch,input,output or interrupt cycles– Two execution breakpoints, set in RAM or ROM, assure
emulation breaks on actual execution, not prefetch– External breakpoint – Event counter provides trigger-on-n times-occurrence– Wildcards in address, data or status parameters – External trigger-in/out signals to work with the scopes or
logic analyzers
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MICEIII
MICEView
Examples
2-2D Main features
High-performance Overlay Memory– 1MB of overlay RAM (no-wait-state)– 4K-bye mapping resolution (within 4 independent 256K
banks)– Read/write,read-only or guarded attributes– All mapping information is retained in non-volatile
memory– On-line assembler supports quick code patches– Build in memory test and checksum commands for
memory verification
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MICEView
Examples
2-3A Setup MICEIII
Select power voltage 110/220 Connect communication ports
– Parallel port: CHANNEL B<->MCE card on PC– Serial Port: CHANNEL A<->com port of PC/terminal
Power on sequence– Recommended: Power on target first, then MICE III
Debug software– MICEView/USD3– Terminal
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MICEIII
MICEView
Examples
2-3B Setup MICEIII
Using MICEView
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MICEIII
MICEView
Examples
2-3C Setup MICEIII
Using Terminal
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MICEIII
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Part 3: MICEView
3-1 Overview 3-2 Configuration MV.INS 3-3 Useful commands
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MICEIII
MICEView
Examples
3-1 Overview
Menu Bar
Register Breakpoint<ALT+ F5> to toggle
Stack /data<ALT+ F6> to toggle
CommandWindow
CODE Window
Message line
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MICEIII
MICEView
Examples
3-2 Configuration MV.INS
• rem ** serial port COM2, Baud rate:9600, 8 data bit, none parity• s:com2 9600,8,n• rem ** parallel port 200• rem p:200• rem ** Enable log capability to log MICE communication data in a file• rem o:log.1• rem ** start to execute include file xxx.inc• rem i:xxx.inc• rem ** select tarp handler address for S/W breakpoint (default is 3fc)• rem v:1000• rem ** skip self-testing when l:s is set (default is l:m)• rem l:s• rem l:m
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MICEView
Examples
3-3A Useful commands
Setup Group:– IDentify REAdy SETup– CLock INTerval RECall – CONtrol Map SIze– MAPI SAve Verify– Help WAit
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3-3B Useful commands
Memory Group:– Assemble COMpare Fill SEarch– Byte COpy LOng TEst– CHecksum Disassemble Memory Word
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3-3C Useful commands
Port Group:– Input Output
Emulation Group:– Cycle Register RESet Step– Jump
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MICEView
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3-3D Useful commands
Trace Group:– COVerage HAlt Qualify TRAce– Event INItialize SYnc Trigger– Go List TImebase
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MICEView
Examples
Examples:
Example1: Compile and use C source debug Example2: Trace Example3: Qualify Example4: Target connecting