Mercury-SA1 - Intel...combination because booting from SD-Card is not supported and the Mercury...

Enclustra GmbH – Technoparkstr. 1 – CH-8005 Zürich – Switzerland

Phone +41 43 343 39 43 – www.enclustra.com

Mercury-SA1

User Manual

Project Info

Project Manager Martin Heimlicher

Author(s) Bruno Pfiffner

Reviewer(s) Christoph Glattfelder

Version 1.06

Date 31.08.2015

31.08.2015 2 / 42 ME-SA1 User Manual V1.06

Copyright © 2015 Enclustra GmbH, Switzerland. All rights reserved.

Unauthorized duplication of this document, in whole or in part, by any means, is prohibited without

the prior written permission of Enclustra GmbH, Switzerland.

Although Enclustra GmbH believes that the information included in this publication is correct as of the

date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.

All information in this document is strictly confidential and may only be published by Enclustra GmbH,

Switzerland.

All referenced registered marks and trademarks are the property of their respective owners.

Document History

Version Date Author Comment

0.10 12.06.2014 Bruno Pfiffner First draft

1.00 23.10.2014 C. Glattfelder First release

1.01 16.03.2015 C. Glattfelder Added MGT section

1.02 30.03.2015 C. Glattfelder Added ordering codes

1.03 12.06.2015 G. Köppel Fixed Module Configurations

1.04 25.06.2015 G. Köppel Updated Module Images

1.05 07.07.2015 C. Glattfelder Updated flash programming sequence

1.06 31.08.2015 C. Glattfelder Updated Power Outputs


Table of Contents

1 Overview ........................................................................................................... 6

1.1 General .......................................................................................................................................... 6

1.1.1 Warranty ........................................................................................................................................................................ 6

1.1.2 RoHS ............................................................................................................................................................................... 6

1.1.3 Disposal and WEEE .................................................................................................................................................... 6

1.1.4 Safety Recommendations and Warnings ......................................................................................................... 6

1.1.5 Electro-Static Discharge .......................................................................................................................................... 7

1.1.6 EMC ................................................................................................................................................................................. 7

1.2 Features ......................................................................................................................................... 7

1.2.1 Deliverables .................................................................................................................................................................. 7

1.3 Accessories .................................................................................................................................... 8

1.3.1 Mercury PE1 base board ......................................................................................................................................... 8

1.3.2 Mercury Starter board ............................................................................................................................................. 8

2 Module Description ......................................................................................... 9

2.1 Block Diagram .............................................................................................................................. 9

2.2 Module Configurations ............................................................................................................. 10

2.3 Part Numbers and Ordering Codes ......................................................................................... 10

2.4 Top and bottom views .............................................................................................................. 12

2.4.1 Top view ..................................................................................................................................................................... 12

2.4.2 Bottom view .............................................................................................................................................................. 13

2.5 Module footprint ....................................................................................................................... 13

2.6 Mercury Module Connectors ................................................................................................... 14

2.6.1 J700/J701 (Mercury Module Connector A, B) .............................................................................................. 14

2.7 User I/O ....................................................................................................................................... 15

2.7.1 Pinout .......................................................................................................................................................................... 15

2.7.2 IO pin exceptions .................................................................................................................................................... 15

2.7.3 Differential I/O ......................................................................................................................................................... 16

2.7.4 I/O banks .................................................................................................................................................................... 16

2.7.5 VCC_IO usage ........................................................................................................................................................... 17

2.7.6 Signal terminations ................................................................................................................................................ 18

2.7.7 HPS I/0 pin’s ............................................................................................................................................................. 18

2.8 Multi Gigabit Transceiver (MGT) ............................................................................................. 19

2.9 Power ........................................................................................................................................... 19

2.9.1 Power generation overview ................................................................................................................................ 19

2.9.2 Power enable / Power good ............................................................................................................................... 19

2.9.3 Supply voltage inputs ........................................................................................................................................... 20

2.9.4 Supply voltage outputs ........................................................................................................................................ 20


2.9.5 Power consumption ............................................................................................................................................... 21

2.9.6 Heat dissipation ...................................................................................................................................................... 21

2.10 Clock generation ........................................................................................................................ 22

2.11 Reset ............................................................................................................................................ 22

2.12 LEDs .............................................................................................................................................. 22

2.13 DDR3 SDRAM ............................................................................................................................. 23

2.13.1 DDR3 SDRAM Type ................................................................................................................................................ 23

2.13.2 Termination ............................................................................................................................................................... 23

2.13.3 Parameters ................................................................................................................................................................ 23

2.14 QSPI flash .................................................................................................................................... 23

2.14.1 QSPI flash type ......................................................................................................................................................... 24

2.14.2 Signal description ................................................................................................................................................... 24

2.15 SD-Card ....................................................................................................................................... 24


2.16 Ethernet ....................................................................................................................................... 25

2.16.1 Ethernet PHY type .................................................................................................................................................. 25


2.16.3 External connectivity ............................................................................................................................................. 25

2.16.4 MDIO address .......................................................................................................................................................... 25

2.16.5 PHY configuration .................................................................................................................................................. 25

2.17 USB ............................................................................................................................................... 26

2.17.1 USB PHY type ........................................................................................................................................................... 26


2.18 Real-time clock (RTC) ................................................................................................................ 26

2.18.1 RTC type ..................................................................................................................................................................... 26

2.19 Secure EEPROM .......................................................................................................................... 27

3 Device configuration ..................................................................................... 28

3.1 JTAG ............................................................................................................................................. 28

3.1.1 JTAG on Mercury module connector .............................................................................................................. 28

3.1.2 HPS JTAG connector .............................................................................................................................................. 28

3.2 Boot mode .................................................................................................................................. 29

3.2.1 HPS Configuration pins ........................................................................................................................................ 30

3.3 Passive serial configuration ..................................................................................................... 30

3.4 QSPI bootmode .......................................................................................................................... 30

3.5 SD-Card bootmode ................................................................................................................... 30

3.6 SPI Flash programming via JTAG ............................................................................................ 30

3.7 SPI flash programming from an external SPI master .......................................................... 30

3.8 Enclustra Module Configuration Tool .................................................................................... 31


4 I2C communication ........................................................................................ 32

4.1 Overview ..................................................................................................................................... 32


4.2 I2C address map ......................................................................................................................... 32

4.2.1 I2C base address ...................................................................................................................................................... 32

4.3 Secure EEPROM .......................................................................................................................... 32

4.3.1 Memory map ............................................................................................................................................................ 33

5 Technical data ................................................................................................ 35

5.1 Absolute maximum ratings ...................................................................................................... 35

5.2 Recommended operating conditions ..................................................................................... 35

5.3 Mechanical data ......................................................................................................................... 36

6 Accessories ..................................................................................................... 37

6.1 Qsys reference design ............................................................................................................... 37

7 Ordering and support ................................................................................... 38

7.1 Ordering ...................................................................................................................................... 38

7.2 Support ........................................................................................................................................ 38

8 Appendix A ..................................................................................................... 39

8.1 Differential pairs net lengths ................................................................................................... 39


1 Overview

1.1 General

The Mercury SA1 FPGA module combines the Altera Cyclone® V ARM® Processor-based SoC FPGA

device with USB2.0,PCIe® x4 and Gigabit Ethernet interface, High-Speed interface, LVDS I/O and is

available in industrial temperate range, forming a complete and powerful embedded processing

system.

The use of Mercury SA1 FPGA modules, in contrast to building a custom FPGA hardware, significantly

simplifies system design and thus shortens time to market and decreases the development effort of

your product.

Together with the Mercury PE1 base board it enables you to quickly put together a prototyping system

and start developing your system “hands-on”.

1.1.1 Warranty

For information concerning the warranty please read through the “General Business Conditions” on

Enclustra’s website1.

1.1.2 RoHS

The Mercury module are designed and produced according to the Restriction of Hazardous

Substances (RoHS) Directive (2011/65/EC).

1.1.3 Disposal and WEEE

The Mercury modules must be disposed properly at the end of its life span. If a battery is installed onto

the board it must also be disposed correctly.

The Mercury modules are not designed “ready for operation” for the end-user. The Waste Electrical

and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mercury boards.

Nonetheless users should still dispose the product properly at the end of life.

1.1.4 Safety Recommendations and Warnings

Ensure that the power supply is disconnected from the board before inserting or removing a Mercury

module, connecting interfaces, replacing SD-Cards and batteries, connecting jumpers, etc.

Take special care with the mounting orientation of Mercury modules – they can fit in the connectors

both ways round. The base board and the module may be damaged if inserted the wrong way and

powered up.

Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage.

Over-voltage on power or signal lines can cause permanent damage.


1.1.5 Electro-Static Discharge

Electronic boards are sensitive to Electro-Static Discharge (ESD). Please ensure that the product is

handled with care and only in an ESD protected environment.

1.1.6 EMC

This is a Class A product and is not intended to be used in domestic environments. The product may

cause electromagnetic interference in which appropriate measures must be taken.

1.2 Features

Altera Cyclon V SOC 5CSXFC6C6U23I7N

ARM dual-core Cortex A9

Altera Cyclon V 28nm FPGA fabric

150 user I/Os

16 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART)

134 FPGA I/Os (single-ended,differential or analog)

6 x 3.125 Gbps MGTs

Up to 4 GByte DDR3L SDRAM

Up to 128 MByte Quad SPI Flash

PCIe Gen1 x4

Gigabit Ethernet

USB 2.0 host/device

2 x CAN, 2 x UART, SPI, 2 x I2C, SDIO/MMC

5 to 15 V supply voltage

1.2.1 Deliverables

Mercury SA1 FPGA module

Mercury SA1 user manual (this document)

Mercury SA1 QSys Reference Design2

Mercury SA1 module VHDL Top-Level and constraint files

Mercury SA1 FPGA pinout excel sheet3

Mercury Master Pinout7 and Module Pin Connection Guidelines8

Mercury SA1 IO Netlength excel sheet4


1.3 Accessories

1.3.1 Mercury PE1 base board

Dual 168-pin Hirose FX10 connectors for Enclustra Mercury FPGA modules

Low-jitter clock generator

System monitor

System controller

eMMC Managed NAND flash

PCIe 2.0 x4 interface

USB 3.0 device interface

4 × USB 2.0 host interface

USB 2.0 device (UART, SPI, I2C, JTAG)

mPCIe/mSATA card holder

FMC LPC connector

2 × 40-pin Anios pin header

3 × 12-pin Pmod™ pin header

5 to 15V or USB bus power (with restrictions)

More information about the Mercury PE1 Baseboard is found on our webpage5.

1.3.2 Mercury Starter board

The Mercury Starter board can be used with the Mercury ZX5. But we don’t recommend this

combination because booting from SD-Card is not supported and the Mercury Starter has no USB-

UART for the console of boot loaders and operating systems.


2 Module Description

2.1 Block Diagram

Figure 1: Hardware block diagram

The heart of the Mercury SA1 module is the Altera Cyclone V SoC device. Most of its I/O pins are

connected to the Mercury module connector, making 150 user I/Os available at the Mercury module

connector.

The SoC device can either boot from the onboard QSPI flash or a SD card located on the baseboard.

For development the JTAG interface is connected to Mercury module connector.

The memory subsystem is built from a 64 MB QSPI Flash and up to 1024MB SDRAM in the standard

configuration.

Further, the module is equipped with a gigabit Ethernet and a USB 2.0 PHY, making it ideal for

communication applications.

A real time clock is available on the I2C bus for SOPC applications.

The on board clock generation is done based on a 50 MHz crystal oscillator.


The module-internal supply voltages (1.1 V, 1.2 V, 1.35V, 1.8 V, 2.5 V, 3.3 V) are generated from the

single input supply of 5..15 V DC. Some of these supplies are available on the Mercury module

connector to supply circuits on the base board.

2.2 Module Configurations

Table 1 shows the available standard module configurations. Custom module configurations are

possible. Please contact us for further information.

Product Number SoC FPGA

DDR3L

SDRAM

PCI

Express

Temp.

Range

ME-SA1-C6-8C-D10 5CSXFC6C6U23C8N 1GB 0..+70°C

ME-SA1-C6-7I-D10 5CSXFC6C6U23I7N 1GB -40..+85°C

Table 1: Standard module configurations

2.3 Part Numbers and Ordering Codes

Every module has a label with a marking specifying the part number and the serial number, as shown

in Figure 2:

Figure 2: Module label

Table 2 shows the correspondence between part number and ordering code.

Part number Ordering code

EN100638 ME-SA1-C6-8C-D10-R1

EN100639 ME-SA1-C6-7I-D10-R1

EN100999 ME-SA1-C6-8C-D10-R2

EN101000 ME-SA1-C6-7I-D10-R2

Table 2: Part Numbers and Ordering Codes

EN100000

SN123456

Part Number

Serial Number


Figure 3 describes the fields of the ordering code.

Figure 3: Ordering Code Fields

FPGA Density

C5: 5CSXFC5C6

ME-SA1 - C5 - 1C - D10 - NDEFKTU

Product Series

ME-SA1: Mercury SA1

FPGA Grade

Speed grade 8, commercial temperature8C:

DDR3 SDRAM Size

D10: 1024MB

- X1 - R2

Custom options

- None

Product RevisionNot Equipped

K:

E:

F:

No battery holder

No Ethernet PHY

No QSPI Flash

D: No DDR3 SDRAM

T: No RTC

U: No USB PHY

C6: 5CSXFC6C6

Speed grade 7, industrial temperature7I:

X1: TBD


2.4 Top and bottom views

2.4.1 Top view


2.4.2 Bottom view

2.5 Module footprint

Figure 4 shows the dimensions of the module footprint on the base board. The Mercury SA1 is 56 mm

wide, but there are other 72 mm wide Mercury modules. If both types shall be fixed by screws

additional mounting holes are required.

Maximum component height on the baseboard under the module is dependent on the connector

type. Please refer to the Hirose FX10 Series Product Website6 for detailed connector information.

The two connectors are called A (J700) and B (J701) in this document.


Figure 4: Module footprint (top view)

2.6 Mercury Module Connectors

2.6.1 J700/J701 (Mercury Module Connector A, B)

Two Hirose FX10 168pin 0.5mm pitch headers with a total of 336 pins have to be integrated on the

base board. Up to four M3 screws may be used to mechanically fasten a Mercury module to the base

board.

The pinout of the module connector is found in the Mercury Master Pinout Excel sheet7.

The connector is available with different packaging options (only tray packaging listed below, see

datasheet for detailed options) and different stacking heights.

Reference Type Description Digikey Part Number

Mercury SA1

Connector

FX10A-168S-SV Hirose FX10, 168-pin, 0.5 mm

pitch

Connector A

J700

Connector B

J701

4x3.2mm

4x2.6mm

1.1mm 1.2mm

1,6mm

2,5mm

PCB

Components

Bottom

Components

Top

Module

Connectors

1,5mm

Warning

The Mercury SX1 SoC module may be placed the wrong way around on the base board.

Always check that the mounting hole positions on the base board and the Mercury SA1

module are aligned!


Reference Type Description Digikey Part Number

Baseboard

Connector

FX10A-168P-SV(71) Hirose FX10, 168-pin, 0.5 mm

pitch, 4mm stacking height

FX10A-168P-SV(71)-ND

Baseboard

Connector

FX10A-168P-SV1(71) Hirose FX10, 168-pin, 0.5 mm

pitch, 5mm stacking height

FX10A-168P-SV1(71)-ND

Table 3: Mercury Connector Types

Figure 5 shows the pin numbering for the Mercury module connectors on the baseboard on top view.

The pins of the Mercury module connector A are numbered J700-1 to J709-168 while the pins of the

Mercury module connector B are numbered J701-1 to J701-168.

Figure 5: Pin Numbering for the Mercury Module Connector

2.7 User I/O

2.7.1 Pinout

The pinout of the module connector is found in the Mercury Master Pinout7 Excel sheet. Please also

refer to the Enclustra Module Pin Connection Guidelines8 for more information about pins and pin

groups.

The bold text of the I/O signal names (e.g. B21 in IO_B3A_TX_B2_Y5_P) indicates the pin number of the

package.

2.7.2 IO pin exceptions

Table 4 shows IO pins with special functions or restrictions.

IO Mercury module

connector pin

Description

1 167

2 168

Warning

Do not use excessive force to latch a Mercury module into the Mercury connectors on

the base board as this could damage the Mercury module as well as the base board.

Always make sure that the Mercury module is oriented the right way before plugging it

into the base board.


IO Mercury module

connector pin

Description

IO_B5A_RX_R6_PERST#_W15_N

HPS_GPIO59_MISO

A-36

A-104

47k resistor to HPS_GPIO59_MISO for PCIe

PERST#

Table 4: IO pin exceptions

2.7.3 Differential I/O

Please note that Cyclone V devices can only use IO pins with “RX” in the name as differential inputs

and only pins with “TX” as differential outputs. All pins can be used as single ended in or output.

Please check your pinout with Quartus before producing your own hardware!

2.7.4 I/O banks

The FPGA’s I/O pins are grouped into four I/O banks. All I/O pins within a particular I/O bank must use

the same I/O (VCC_IO) and reference (VREF) voltages. Table 5 shows the main attributes of the FPGA

I/O banks, and which peripherals are connected to each I/O bank.

Bank Connectivity VCC_IO VREF

MGT

Bank L0 Mercury module connector 1.1V -

MGT

Bank L1 Mercury module connector 1.1V -

Bank 3A Mercury module connector User selectable

VCC_CFG_HPS_B3A_B8A 0V

Bank 3B Mercury module connector User selectable

VCC_IO_B3B_B4A 0.5*VCC_IO_B3B_B4A

Bank 4A Mercury module connector,

LEDs

User selectable

VCC_IO_B3B_B4A 0.5*VCC_IO_B3B_B4A

Bank 5A Mercury module connector User selectable

VCC_IO_B5A_B5B 0.5*VCC_IO_B5A_B5B

Bank 5B Mercury module connector User selectable

VCC_IO_B5A_B5B 0.5*VCC_IO_B5A_B5B

Bank 8A Mercury module connector,

FPGA_CLK, CLOCK_SEL VCC_CFG_HPS_B3A_B8A 0V


Bank Connectivity VCC_IO VREF

HPS

Bank 6A DDR3L SDRAM 1.35V 0.68V

HPS

Bank 6B DDR3L SDRAM 1.35V 0.68V

HPS

Bank 7A

Mercury module connector

I2C VCC_CFG_HPS_B3A_B8A 0V

HPS

Bank 7B Ethernet PHY, SPI flash VCC_CFG_HPS_B3A_B8A 0V

HPS

Bank 7C Mercury module connector VCC_CFG_HPS_B3A_B8A 0V

HPS

Bank 7D USB PHY VCC_CFG_HPS_B3A_B8A 0V

Table 5: I/O banks

2.7.5 VCC_IO usage

The VCC_IO for the I/O banks located on Mercury module connector are configurable by applying the

required voltage to the VCC_IO_B[x] pins. All VCC_IO_B[x] pins of the same bank must be connected to

the same voltage.

For compatibility with other Enclustra Mercury modules we suggest to use only one IO voltage per

connector.

Please refer also to the Enclustra Module Pin Connection Guidelines8 for general rules.

Signal name FPGA Pins Supported

Voltages

Connector

A Pins

Connector

B Pins

VCC_IO_B3B_B4A

VCCIO_3B,

VCCIO_4A,

VCCPD3B4A

1.2V-3.3V

+/-5% -

64, 67, 88,

95, 140, 143

VCC_IO_B5A_B5B

VCCIO5A,

VCCPD5A,

VCCIO5B,

VCCPD5B,

1.2V-3.3V

+/-5% 38, 41 -

VCC_CFG_HPS_B3

A_B8A

VCCIO8A,

VCCPD8A,

VCCIO7A-D

1.8V,

2.5-3.3V

+/-5%

74, 77 -

Table 6: VCC_IO pins


2.7.6 Signal terminations

2.7.6.1 Differential inputs

There are no external differential termination resistors on the Mercury SA1 FPGA module for

differential inputs. Differential input pairs on the Mercury module connector may be terminated either

by external termination resistors on the base board (close to the module pins), or by the FPGA-internal

termination resistors.

Please note that Cyclone V devices can only use IO pins with “RX” in the name as differential inputs.

2.7.6.2 Single-ended outputs

There are no series termination resistors on the Mercury SA1 FPGA module for single-ended outputs. If

required, series termination resistors may be equipped on the base board (close to the module pins).

2.7.7 HPS I/0 pin’s

All HPS that are routed to the module connector can be used as GPIO. The suggested functions below

are for reference only. Always verify your HPS pinout with the Altera device handbook.

Table 7 gives an overview over the HPS pin connections on the Mercury SA1.

HPS_GPIO Function Connection

0-13 USB 2.0 USB PHY

14-27 Ethernet Ethernet PHY (RGMII)

29-34 SPI flash SPI flash

36, 38, 39, 45-47

SD-Card, GPIO Module connector

37 Ethernet interrupt (input, active low) Ethernet PHY

40 Boot Mode BOOT_MODE0

41 Ethernet Link status (ETH_LED2#, input, active low)

Ethernet PHY

42 Boot Mode BOOT_MODE1

43 Power good (input, active high) PWR_GOOD

44 Ethernet PHY reset (output, active low) Ethernet PHY

Warning

Only use VCC_IO voltages compliant with the equipped SoC device. Any other voltages

may damage the equipped SoC device as well as other devices on the Mercury SA1 SoC

module.

Do not leave a VCC_IO pin floating. Doing so may damage the equipped Soc device as

well as other devices on the Mercury SA1 SoC module.


HPS_GPIO Function Connection

48-51 LEDs (parallel to FPGA IOs) Onboard LEDs

54-56 I2C Onboard I2C bus and module connector via level shifter

57-60 SPI, GPIO Module connector

61-62 CAN, GPIO Module connector

63-64 UART1, GPIO Module connector

65-66 UART0, GPIO Module connector

Table 7: HPS pin connections

2.8 Multi Gigabit Transceiver (MGT)

All IO pairs of the six multi gigabit transceivers as well as the two reference clock pairs are routed

directly to the module connector. No AC coupling capacitors are placed on the Mercury SA1.

2.9 Power

2.9.1 Power generation overview

The Mercury SA1 SoC module uses a 5-15V DC power input for generating the on-board supply

voltages (1.1V, 1.2V, 1.35V, 1.8V, 2.5V, 3.3V). Some of these voltages (1.8V, 2.5V, 3.3V) are also

accessible on the Mercury module connector.

The 1.0V and 3.3V supplies are rated 9A and fed from VCC_MOD. The 1.35V and 1.8V supplies are

rated 1.5A and fed from VCC_3V3. The 1.2V and 2.5V supplies are rated 1A and fed from VCC_3V3.

Please refer also to the Enclustra Module Pin Connection Guidelines8 for general rules about the

power pins.

2.9.2 Power enable / Power good

The Mercury SA1 SoC module provides a power enable input on the Mercury module connector. This

input may be used to shut down the DC/DC converters for 1.0V, 1.2V, 1.5V, 1.8V and 2.5V. The 3.3V

supply is always active.

The PWR_EN input is pulled to 3.3V on the Mercury SA1 module with a 4.7kΩ pull-up resistor.

The PWR_GOOD signal is pulled to 3.3 V on the Mercury SA1 module with a 4.7kΩ pull-up resistor. The

signal is pulled to GND if any of the on board regulators fail.


Pin Name Module Connector Pin

Remarks

PWR_EN A-10 Floating/3.3 V: Module power enabled Tied to GND: FPGA power disabled

PWR_GOOD A-12 0V: Module supplies not ok 3.3V: Module supplies ok

Table 8: Module power pins

2.9.3 Supply voltage inputs

Table 9 shows the power supply inputs on the Mercury SA1 module.

Pin Name Module

Connector Pin(s) Voltage

Description

VCC_MOD A-1, 3, 5, 7, 9, 11

A-2, 4, 6, 8

5-15 V

+/- 5%

Supply for the 1.0V and 3.3V regulators.

All other supplies are generated from the 3.3V

supply.

The input current should be max 3A (0.3A per

connector pin)

VBAT A-168 2.0-3.6 V Battery for the RTC and SoC encryption key.

Table 9: Supply voltage inputs

2.9.4 Supply voltage outputs

Three of the supply voltages generated on the Mercury SA1 are available on the Mercury module

connector.

Pin Name Module Connector

Pin(s) Voltage Maximum Current

1 Comment

VCC_3V3 A: 26, 29, 50, 86

B: 55, 79, 115, 127,

152, 155

3.3V +/- 5% 3.0 A

(and max 0.3A per pin)

Always active

1 The maximum available output current is depending on your design. See sections 2.9.1 and 2.9.5 for

more details.

Warning

Do not connect VCC_3V3 to VCC_IO directly if PWR_EN is used to disable the module.

Then VCC_IO needs to be switched off as well.


Pin Name Module Connector

Pin(s) Voltage Maximum Current

1 Comment

VCC_2V5 A: 53, 62, 65, 89 2.5V +/- 5% 0.5 A Controlled by

PWR_EN

VCC_1V8 B: 52, 76, 108, 128 1.8V +/- 5% 0.5 A Controlled by

PWR_EN

Table 10: Supply voltage outputs

2.9.5 Power consumption

Please note that the power consumption of SoC/FPGA devices depends strongly on the application. To

estimate the power consumption of your design, please use the Altera PowerPlay Early Power

Estimator or PowerPlay Power Analyzer.

2.9.6 Heat dissipation

High performance FPGAs as the Altera Cyclon V SoC need cooling in most applications. Always make

sure the FPGA is cooled sufficiently.

The suitable heatsink can be found for example at http://www.qats.com. It is preferable the following

series maxiGrip and superGrip. Important for the selection of the heat sink is the height of the

assembled FPGA's.

Further the 4 mounting holes around the FPGA can be used for a custom heat sink. For more

measurments refer to section 2.5.

The UBGA676 package is 23x23 mm wide. Table 11 shows the height of the package. For more details

about the packages refer to the Altera UBGA 672 package datasheet9.

Package Height (min) Height (nom) Height (max)

UBGA676 1.55 mm 1.70 mm 1.85 mm

Table 11: FPGA package height

Warning

Always make sure that the required airflow is available. A heat sink for the Mercury

SA1 module’s SoC device may be required in most cases. Overheating may damage

the Mercury SA1 module.

Warning

Do not connect any power supply to the supply outputs or short circuit them to GND.

Doing so may damage the Mercury SA1 SoC module.

http://www.qats.com/


2.10 Clock generation

A 50 MHz oscillator is heart of the Mercury SA1 clock generation. The 50 MHz clock is fed to the HPS

system and the FPGA logic. A clock divider generates a 25 MHz clock for Ethernet and the 2nd

HPS

clock.

Signal

Name Frequency Destination Remark

CLK_HPS1 50 MHz HPS_CLK1 HPS clock 1

CLK_HPS2 25 MHz HPS_CLK2 HPS clock 2

CLK_ETH 25 MHz Gigabit Ethernet PHY

FPGA_CLK 50 MHz 2.10.1 Pin D12 / CLK7P / Bank

8A

FPGA clock

Table 12: Module clock resources

2.11 Reset

The power-on reset (POR) as well as the HPS soft reset of the SoC device are available on the Mercury

module connector.

Pulling HPS_POR# low resets the SoC device as well as the SPI flash. Further the NCONFIG pin is pulled

low to retrigger the FPGA configuration.

Please refer also to the Enclustra Module Pin Connection Guidelines8 for general rules about the

connection of the reset pins.

Table 13 shows the available reset signals. Both, HPS_POR# and HPS_RST#, have on-board 4.7kΩ pull-

up resistors to VCC_CFG_HPS_B3A_B8A.

Signal Name Connector Pin FPGA Pin Type Description

HPS_POR# A-132 PS_POR_B Hard Reset

HPS_RST# A-124 PS_SRST_B Soft Reset

Table 13: Reset resources

2.12 LEDs

The 4 LEDs on the Mercury SA1 are connected to the FPGA logic and the HPS system in parallel. The

LEDs must only be driven from one side at once. Since the LEDs are active low it is recommended to

use the IOs in open drain mode.


Signal Name HPS_GPIO FPGA Pin Remarks

LED0# 48 AH12 User function / Active low

LED1# 49 AF18 User function / Active low

LED2# 50 AG21 User function / Active low

LED3# 51 AH21 User function / Active low

Table 14: LEDs

2.13 DDR3 SDRAM

The DDR3 SDRAM on the Mercury SA1 is always operated in the 1.35V low power mode. Four 8 bit

memory chips are used to build a 32 bit wide memory.

2.13.1 DDR3 SDRAM Type

For the memory sizes of the Mercury modules please refer to section 2.2.

Module SDRAM Type Density Configuration Manufacturer

ME-SA1-D9 MT41K128M8-125 1 Gbit 128M x 8bit Micron

ME-SA1-D10 MT41K256M8-125 2 Gbit 256M x 8bit Micron

Table 15: DDR3 SDRAM types

2.13.2 Termination

External termination is implemented on the Mercury SA1 with an EV1320QI termination converter.

2.13.3 Parameters

Please refer to the Mercury SA1 reference design2 for the DDR3 settings.

2.14 QSPI flash

The QSPI flash can only be used to boot the HPS system, the FPAG bitstream needs to be loaded via

the HPS (bootloader). The SPI flash can also be used to store ARM application code and other user

data.

Warning

Other DDR3 memory devices might be equipped in future. Please check regularly the

user manual for updates.


2.14.1 QSPI flash type

Table 16 shows the equipped QSPI Flash device type.

Type Size Manufacturer

S25FL512SAGBHIA13 512 Mbit Spansion

Table 16: QSPI flash type

2.14.2 Signal description

The QSPI flash is connected to the HPS GPIOs 30-34 and to the FPGA SPI configuration port.

Some of the signals are also available on the Mercury module connector to program the SPI flash from

an external source. Please refer to section 3 for more details about programming the flash memory.

2.15 SD-Card

An SD-Card can be connected to the HPS_GPIOs available on the Mercury module connector. This

allows the Mercury SA1 to boot from the SD-Card as well as data access after booting.

Please note that external pull-ups are need for SD-Card operation. And depending on the selected

voltage on VCC_CFG_HPS_B3A_B8A a level-shifter to 3.3V might be needed.


HPS_GPIO SD-Card signal Connector Pin

36 CMD A-93

38 D0 A-95

39 D1 A-97

45 CLK A-91

46 D2 A-101

47 D3 A-103

Table 17: SD-Card signals

Warning

Be careful when connecting the QSPI flash signals on the baseboard.

Long traces or high capacitances may disturb the data communication between the

Cyclone V and the flash devices.


2.16 Ethernet

There is one 10/100/1000 Mbit Ethernet PHY on the Mercury SA1 module, connected to the HPS via

RGMII interface.

2.16.1 Ethernet PHY type

Table 18 shows the equipped Ethernet PHY device type.

Type Manufacturer Type

KSZ9031RNXIA Micrel 10/100/1000 Mbit

Table 18: Ethernet PHY type


The RGMII interface is connected to HPS pins for use with the hard macro MAC.

Ethernet reset has a pulldown resistor and needs to be driven high to release the PHY from reset.

A detailed list of the HPS connections is found in section 2.7.7.

2.16.3 External connectivity

The Ethernet lines can be connected directly to the magnetics. Please refer to the Enclustra Module Pin

Connection Guidelines8 for more details about the connection of Ethernet signals.

2.16.4 MDIO address

The PHY uses address 3 on the MDIO bus.

2.16.5 PHY configuration

The configuration of the Ethernet PHY is boot-strapped when the PHY is released from reset. Make

sure all IOs on the RGMII interface are initialized and any pull-up or pull-down resistors disabled at

that moment.

The boot-strap options of the Ethernet PHY are set as shown in Table 19.

Please note that the RGMII delays in the Ethernet PHY need to be configured before the Ethernet

interface can be used. This is done in the patch for the bootloader (SPL) provided in the Mercury SA2

reference design2.

Pin Signal

Value Description

MODE[3-0] 1110 RGMII Mode: advertise all capabilities (10/100/1000, half/full

duplex) except 1000Base-T half duplex.

PHYAD[2-0] 011 MDIO address 3


Pin Signal

Value Description

Clk125_EN 1 125 MHz clock output enabled

LED_MODE 1 Single LED mode

Table 19: PHY configuration

2.17 USB

The Mercury SA1 has an onboard USB 2.0 PHY connected to the Cyclone V SoC device. The USB

interface can be operated either in master or slave mode.

2.17.1 USB PHY type

Table 20 shows the equipped USB PHY device type.

Type Manufacturer Type

USB3320C Microchip USB 2.0 PHY

Table 20: USB PHY type


The ULPI interface is connected to HPS pins for use with the integrated USB controller.

USB reset has a pulldown resistor and needs to be driven high to release the PHY from reset.

A detailed list of the HPS connections is found in section 2.7.7.

2.18 Real-time clock (RTC)

A real time clock is connected to the I2C bus. VBAT of the RTC is connected to VCC_BAT on the

Mercury module connector, and can be connected directly to a 3 V battery or tied to GND if not used

(please refer to the RTC datasheet). The RTC also features a battery-buffered 128 bytes user SRAM and

a temperature sensor. See section section 4 for more details about the I2C bus on the Mercury SA1

SoC module.

Please note that the frequency out function of the RTC must be disabled in order to use I2C interrupts.

Otherwise I2C_INT# is periodically pulled down by the RTC. This is done by setting bits 3-0 of the RTC

register 8 to zero.

2.18.1 RTC type

Table 21 shows the equipped RTC device type.


Type Manufacturer

ISL12020M Intersil

Table 21: RTC type

2.19 Secure EEPROM

The secure EEPROM is used to store the module type and serial number as well as the Ethernet MAC

address and other information. It is connected to the I2C bus. See section 4.3 for more details. The

EEPROM must not be used to store user data.

Table 22 shows the equipped EEPROM device type.

Type Manufacturer

DS28CN01 Maxim

Table 22: EEPROM type


3 Device configuration

3.1 JTAG

Normally the FPGA and the HPS JTAG interfaces are connected into one single chain available on the

Mercury module connector. If needed for a third party ARM debugger the HPS JTAG interface is also

routed to an optional JTAG connector (J1000) on the Mercury SA1.

3.1.1 JTAG on Mercury module connector

Signal Name Module Connector Pin Resistors

JTAG_TCK A-123 Pulldown 4k7

JTAG_TMS A-119 Pullup 4k7

JTAG_TDI A-117 Pullup 4k7

JTAG_TDO A-121 -

Table 23: JTAG interface

3.1.2 HPS JTAG connector

Figure 6 shows the pinout of the HPS JTAG connector. To enable the HPS JTAG port on J1000

JTAG_PRESENT# (pin 9) must be pulled low.

The connector is a 10 pin SMD header with 1.27mm pitch (e.g. Sullins GRPB052VWQS-RC).

Figure 6: HPS JTAG connector


3.2 Boot mode

The BOOT_MODE signals determines whether the SoC device boots from the SPI flash or from a SD

card connected to the SD0 port on the MIO bank. Further also JTAG boot mode is available for

development.

Table 24 shows the available boot modes and the according levels for the boot mode signals.

BOOT_MODE1 BOOT_MODE0 HPS boot FPGA boot MSEL[4:0] CSEL[1:0] BSEL[2:0]

0 0 from

FPGA passive serial 10000 00 001

0 1 reserved reserved 10010 00 10V2

1 0 QSPI from HPS 00010 00 11V2

1 1 SDIO from HPS 00010 00 10V2

Table 24: Boot modes

Table 25 shows the connection of the most important configuration pins.

Signal Name FPGA Pin HPS Pin SPI Flash

Pin

Module

Connector

Pin

Resistor on

Board

FLASH_CLK DCLK GPIO34 CLK A-118 Pull-Up, 4.7kΩ

FLASH_CS# NCSO GPIO33 CS# A-116 Depending on

boot mode

FLASH_DI ASDATA0 GPIO29 SI/IO0 A-114 Pull-Up, 4.7kΩ

FLASH_DO ASDATA1 GPIO30 SO/IO1 A-122 Pull-Up, 4.7kΩ

FLASH_D2 ASDATA2 GPIO31 IO2 - -

FLASH_D3 ASDATA3 GPIO32 IO3 - -

HPS_RST# - HPS_RST# - A-124 Pull-Up, 4.7kΩ

HPS_POR# FPGA_CONFIG# HPS_POR# RESET# A-132 Pull-Up, 4.7kΩ

FPGA_CONFDONE CONFDONE - - A-130 Pull-Up, 1kΩ

BOOT_MODE0 - GPIO40 - A-126 Pull-Up, 4.7kΩ

BOOT_MODE1 - GPIO42 - A-112 Pull-Up, 4.7kΩ

Table 25: FPGA configuration pins

2 BSEL[0] is depending on the VCC_CFG_HPS_B3A_B8A voltage: it is set to 0 for 1.8V and 1 for 2.5-3.3V


3.2.1 HPS Configuration pins

The BSEL and CSEL pins determine which memory interface has the boot loader and how to clock the

interface. For booting the HPS, the BSEL and CSEL pins details are covered in Altera’s Cyclone V

Booting and Configuration Introduction10

.

3.3 Passive serial configuration

In passive serial configuration mode the FPGA bitstream is programmed form an external source into

the SPI port of the FPGA. The HPS is configured afterwards with the HPS2FPGA Bridge. For more

information please refer to the Cyclone V datasheet12

.

3.4 QSPI bootmode

In the QSPI bootmode the HPS boots from the SPI flash and configures the FPGA logics from the HPS.

The HPS configuration and the FPGA bitstream need to be stored in a preloader image. For more

information please refer to the Cyclone V datasheet12

.

3.5 SD-Card bootmode

In the SD-Card bootmode the HPS boots from the SD-Card locard on the baseboard and configures

the FPGA logics from the HPS. The HPS configuration and the FPGA bitstream need to be stored in a

preloader image. For more information please refer to the Cyclone V datasheet12

.

3.6 SPI Flash programming via JTAG

The Altera Quartus software offers flash programming support via JTAG. For more information please

refer to the Quartus user manual.

3.7 SPI flash programming from an external SPI

master

The signals of the SPI Flash are directly connected to the module connector. Because the Flash signals

are also connected to the SOC device, the SOC device pins must be tri-stated while accessing the SPI

slash directly from an external device. This is ensured by pulling the HPS_RST# signal to GND followed

Warning

All configuration signals except BOOT_MODE must be high impedance as soon as the

device is released from reset! Violating this rule may damage the equipped FPGA

device as well as other devices on the Mercury SA1 FPGA module.


by a pulse on HPS_POR#, which puts the SoC into reset state and tri-states all I/O pins. HPS_RST# must

be low when HPS_POR# is released and kept low until the flash programming has finished. After

programming the SPI flash all SPI lines and HPS_RST# must be tristated and another reset impulse

applied to HPS_POR#.

3.8 Enclustra Module Configuration Tool

In connection with an Enclustra baseboard the SPI flash can also be programmed with our free Module

Configuration Tool (Enclustra MCT)11

.


4 I2C communication

4.1 Overview

The I2C bus on the Mercury SA1 SoC module connects the FPGA, EEPROM and the RTC and is also

available on the module connector. This allows external devices to read the module type and to

connect more devices to the I2C bus.

Please note that the RTC must be configured correctly to use I2C interrupts. For more details refer to

section 2.18.


Table 26 shows the signals of the I2C interface. All signals must only be connected to open collector

outputs and have on board pull up resistors to VCC_3V3. Do not drive the I2C signals high from any

source. I2C_INT# is an input on the FPGA and must not be driven from the FPGA.

There are level shifter between the I2C bus and the HPS pins.

Signal name SoC Pin Connector Pin Pull up Resistor

I2C_SDA HPS_GPIO55 A-113 2.2k

I2C_SCL HPS_GPIO56 A-111 2.2k

I2C_INT# HPS_GPIO54 A-115 4.7k

Table 26: I2C signal description

4.2 I2C address map

4.2.1 I2C base address

Address (7-bit) Description 0x5C / 0x64 Secure EEPROM (depending on assembly option)

0x57 RTC User SRAM

0x6F RTC Registers

Table 27: I2C addresses

4.3 Secure EEPROM

The secure EEPROM is used to store the module serial number and configuration.


In future, it will also be used for copy protection and licensing features. Please contact us for further

information. Do not write any data to the secure EEPROM!

4.3.1 Memory map

Address Length (bits) Description 0x00 32 Module serial number

0x04 32 Module product number

0x08 32 Module configuration

0x0C 32 Reserved

0x10 48 Ethernet MAC address

0x16 48 Reserved

0x1C 32 Checksum

Table 28: EEPROM Sector 0 memory map

4.3.1.1 Module serial number

The module serial number is a unique 32 bit number that identifies the module. It is stored using big-

endian byte order (MSB on the lowest address).

4.3.1.2 Module product number

Module Product-

Family

Subtype Revision Product-

Number

Mercury SA1 0x0326 0x00 0x01 0x0326 0001

Table 29: Product number

4.3.1.3 Module configuration

Address Bits Comment Min. Value Max. Value Resolution 0x08 7-4 FPGA Type 0 2 See FPGA type

table

3-0 FPGA Speed Grade 6 8

0x09 7 Temperature Range 0 (Consumer) 1 (Industrial)

6 Power 0 (normal) 2 (low power)

5-4 No. of Ethernet Ports 0 2

3 Gigabit Ethernet 0 (Fast only) 1


Address Bits Comment Min. Value Max. Value Resolution 2 RTC equipped 0 1

1 Current monitor

equipped

- -

0 Reserved - -

0x0A 7-2 Reserved - -

1-0 USB Device Ports 0 3

0x0B 7-4 DDR3 RAM Size 0 MB 2 GB 8 MBytes

3-0 SPI Flash Memory

Size

0 MB 64 MB 1 MByte

0x0C 7-4 Reserved - -

3-0 Reserved - -

Table 30: Module configuration

The memory sizes are defined as Resolution*2(Value-1)

(e.g. DRAM=0: not Equipped, DRAM=1: 8MB,

DRAM=2: 16MB, DRAM=3: 32MB, etc).

Table 31 shows the available SoC types.

Value SoC device type

0 5CSEBA2U23

1 5CSCFC4U23

2 5CSXFC6U23

Table 31: SoC device types

4.3.1.4 Ethernet MAC address

The Ethernet MAC address is stored using big-endian byte order (MSB on the lowest address).

Each module has assigned two sequential MAC addresses. Only the lower one is stored in the

EEPROM.


5 Technical data

5.1 Absolute maximum ratings

Table 32 below is for reference only. For more details, please refer to the Cyclone V Device Datasheet12

.

Symbol Description Rating Unit

VCC_MOD Supply voltage relative to GND -0.5 to 16 V

VCC_3V3 3.3 V supply voltage relative to GND -0.5 to 3.6 V

VCC_BAT Voltage for the RTC and encryption key 2.0 to 3.6 V

VCC_IO[x] Output drivers supply voltage relative to GND -0.5 to 3.6 V

V_IO I/O input voltage relative to GND -0.5 to VCC_IO+0.5 V

Temperature Temperature range for commercial modules (C)

Temperature range for industrial modules (I)

0 to +70

-40 to +85 °C

Table 32: Absolute maximum ratings

5.2 Recommended operating conditions

Table 33 is for reference only. For more details, please refer to the Cyclone V Device Datasheet12

.

Symbol Description Rating Unit

VCC_MOD Supply voltage relative to GND 4.75 to 15.75 V

VCC_3V3 3.3 V supply voltage relative to GND 3.15 to 3.45 V

VCC_BAT Voltage for the RTC and encryption key 2.0 to 3.45 V

VCC_IO[x] Output drivers supply voltage relative to GND

For the allowed voltage ranges for each IO bank please

refer to section 2.7.5.

1.14 to 3.45

V

V_IO I/O input voltage relative to GND -0.2 to VCC_IO+0.2 V

Temp. Temperature range for commercial modules (C)

Temperature range for industrial modules (I)

0 to +70

-40 to +85 °C

Table 33: Recommended operating conditions


5.3 Mechanical data

Symbol Value

Size 55 x 54 mm

Component height top 2.5 mm

Component height bottom 1.5 mm

Weight 20 g

Table 34: Mechanical data


6 Accessories

6.1 Qsys reference design

The Qsys reference design features an example configuration for the Cyclon V SoC device as well as an

example top level file for the user logic as source and binary.

The Quartus II reference design can be downloaded from our server.

http://download.enclustra.com/


7 Ordering and support

7.1 Ordering

Please use Enclustra's online request/order form for ordering or requesting information:

http://www.enclustra.com/en/orderenquire/

7.2 Support

Please follow the instructions on Enclustra's online support site:

http://www.enclustra.com/en/support/

http://www.enclustra.com/en/orderenquire/

http://www.enclustra.com/en/support/


8 Appendix A

8.1 Differential pairs net lengths

If using differential pairs, a differential impedance of 100 Ohm should be met on the FPGA board.

Make sure that the two nets of a differential pair have the same length.

An Excel table that lists the length of the differential pairs on the Mercury SA1 FPGA module is

available on our download page4. This allows the user to match the total length of the differential

pairs on the FPGA board if required for the application.


Figures

Figure 1: Hardware block diagram .......................................................................................................................................... 9

Figure 2: Module label .............................................................................................................................................................. 10

Figure 3: Ordering Code Fields .............................................................................................................................................. 11

Figure 4: Module footprint (top view) ................................................................................................................................ 14

Figure 5: Pin Numbering for the Mercury Module Connector.................................................................................. 15

Figure 6: HPS JTAG connector ............................................................................................................................................... 28

Tables

Table 1: Standard module configurations ......................................................................................................................... 10

Table 2: Part Numbers and Ordering Codes .................................................................................................................... 10

Table 3: Mercury Connector Types ...................................................................................................................................... 15

Table 4: IO pin exceptions ....................................................................................................................................................... 16

Table 5: I/O banks ....................................................................................................................................................................... 17

Table 6: VCC_IO pins .................................................................................................................................................................. 17

Table 7: HPS pin connections ................................................................................................................................................. 19

Table 8: Module power pins ................................................................................................................................................... 20

Table 9: Supply voltage inputs .............................................................................................................................................. 20

Table 10: Supply voltage outputs ......................................................................................................................................... 21

Table 11: FPGA package height............................................................................................................................................. 21

Table 12: Module clock resources ........................................................................................................................................ 22

Table 13: Reset resources ........................................................................................................................................................ 22

Table 14: LEDs .............................................................................................................................................................................. 23

Table 15: DDR3 SDRAM types ............................................................................................................................................... 23

Table 16: QSPI flash type ......................................................................................................................................................... 24

Table 17: SD-Card signals ........................................................................................................................................................ 24

Table 18: Ethernet PHY type ................................................................................................................................................... 25

Table 19: PHY configuration ................................................................................................................................................... 26

Table 20: USB PHY type ............................................................................................................................................................ 26

Table 21: RTC type ...................................................................................................................................................................... 27

Table 22: EEPROM type ............................................................................................................................................................ 27

Table 23: JTAG interface ........................................................................................................................................................... 28


Table 24: Boot modes ............................................................................................................................................................... 29

Table 25: FPGA configuration pins ....................................................................................................................................... 29

Table 26: I2C signal description ............................................................................................................................................ 32

Table 27: I2C addresses ............................................................................................................................................................ 32

Table 28: EEPROM Sector 0 memory map ........................................................................................................................ 33

Table 29: Product number ....................................................................................................................................................... 33

Table 30: Module configuration ............................................................................................................................................ 34

Table 31: SoC device types ...................................................................................................................................................... 34

Table 32: Absolute maximum ratings ................................................................................................................................. 35

Table 33: Recommended operating conditions.............................................................................................................. 35

Table 34: Mechanical data ....................................................................................................................................................... 36

References

1 Enclustra General Business Conditions

http://www.enclustra.com/en/products/gbc/

2 Mercury SA1 Qsys Reference Design

http://download.enclustra.com/#Mercury_SA1

3 Mercury SA1 FPGA pinout excel sheet


4 Mercury ZX5 IO Netlength Excel sheet


5 Enclustra Mercury PE1 base board

http://www.enclustra.com/en/products/base-boards/mercury-pe1/

6 Hirose FX10 Series Product Website

http://www.hirose-connectors.com/

7 Enclustra Mercury Master Pinout, Enclustra GmbH

http://download.enclustra.com/public_files/Design_Guidelines/Mercury_Master_Pinout.xlsm

8 Enclustra Module Pin Connection Guidelines, Enclustra GmbH

http://download.enclustra.com/public_files/Design_Guidelines/Module_Pin_Connection_Guidelines.pdf

9 Altera UBGA 672 package datasheet

http://wl.altera.com/devicepackaging/04R00437-02.pdf

10 Booting and Configuration Introduction

http://www.altera.com/literature/hb/cyclone-v/cv_5400A.pdf

11 Enlustra Module Configuration Tool

http://www.enclustra.com/en/products/gbc/




http://www.enclustra.com/en/products/base-boards/mercury-pe1/

http://www.hirose-connectors.com/

http://download.enclustra.com/public_files/Design_Guidelines/Mercury_Master_Pinout.xlsm

http://download.enclustra.com/public_files/Design_Guidelines/Module_Pin_Connection_Guidelines.pdf

http://wl.altera.com/devicepackaging/04R00437-02.pdf

http://www.altera.com/literature/hb/cyclone-v/cv_5400A.pdf



12 Cyclone V Device Datasheet

http://www.altera.com/literature/hb/cyclone-v/cv_51002.pdf


http://www.altera.com/literature/hb/cyclone-v/cv_51002.pdf

Mercury-SA1 - Intel...combination because booting from SD-Card is not supported and the Mercury...

Documents

Transcript of Mercury-SA1 - Intel...combination because booting from SD-Card is not supported and the Mercury...