A 1.6-880MHz Synthesizable ADPLL in O.13um CMOS

Hsiang-Hui Chang, Shang-Ming Lee, Chao-Wen Chou, Yu-Tung Chang and Yi-Li Cheng

MediaTek Inc., Hsin-Chu, Taiwan

Fig.2 Conventional wide-range DCO

Fig.1 Proposed PLL architecture

"",--,""'CCDCO

1M

M[2:0]

1M

Cycle[8:0]

GAIN[8:0]

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TH[S:O]. ----"-MAXG 8:0 GainMING[8:0] controller

Offset compensationcircuit

Control codes

III. Circuit descriptionA. Cycle-controlled DCO

In Fig.2, a DCO with a post divider can achieve a wideoperating range. The period ofDCa is determined byT_conventional=Cycle[8:0]NTd (1)

a standard cell library and is suitable for advanceddeep-submicron technologies.

II. Architecture of the ADPLLThe architecture of the proposed ADPLL is shown in Fig.

I. It is composed of a PFD, a TDC, an offset compensationcircuit, a digital loop filter (DLP), a gain controller, adecoder, a programmable divider, and a cycle-controlledDCO (CCDCO). Initially, unavoidable static phase errorcaused by automatically synthesis of PFD and TOC can becalibrated by the offset compensation circuit. The TOCgenerates T[5:0] according to the phase difference betweenthe reference clock (REF) and feedback clock (FB). Thegain controller will continuously monitor the differencebetween T[5:0} and TH[5:0} and dynamically adjust thegain of the DLF to reduce lock time. The gain range of theDLF is limited by MAXG[8:0} and MING[8:0},respectively. After digital filtering, the decoder applies thefrequency-bouncing-reduced algorithm to determine theoptimal values of Cycle[8:0}, /[4:0}, and F[4:0},respectively, and controls the frequency of CCDeO. Withthe proposed algorithm, the AOPLL automatically locksover a wide range operation regardless of the initialcondition, without any auxiliary circuit. All building blocksin the ADPLL are RTL-based and are synthesizable,considerably reducing the design time and maintain efforts.

AbstractA synthesizable all digital phase-locked loop (ADPLL)

with an improved DCO and a frequency-bouncing-reducedalgorithm is presented. The ADPLL covers 1.6 - 880 MHzfrequency range while maintaining high frequencyresolution. The synthesizable ADPLL can be easily migratedto different processes and foundries; requires less designtime and maintain effort; and directly benefit from CMOStechnology scaling. The PLL is fabricated in a 0.13-umIP6M high-Vt CMOS process and occupies an active area of220x220 um2 The PLL consumes a maximum power of 16mW and has 114ps peak-to-peakjitter at 880MHz.

I. IntroductionTraditionally, analog phase-locked loops (PLLs) have

better jitter and skew performance when compared to digitalPLLs. However, their migration to different technologynodes requires time-consuming redesign. In addition, theassociated loop filter capacitor usually occupies considerablearea, and potentially has leakage problem if MOS capacitorsare used. The leakage problem becomes more severe asCMOS feature size continues to scale down. Alternatively,digital PLLs can easily migrate to different processes,provide re-configurability, and solve the leakage issue byusing digital loop filter. Thanks to process scaling, thedigital PLLs also operate at a lower supply voltage and hasthe potential for good power-management. [1-5]

To successfully achieve a wide operating range, theconventional digital PLL demands a digital-controlledoscillator (DCO) composed of high-bandwidth delay units.To implement such a PLL under reasonable area constraint,the tradeoff between the bandwidth ofa single delay unit andthe number of stages in a DCO will substantially limit theratio of the highest to the lowest operating frequency. ThePLLs usually need a calibration circuit to pre-determine thesuitable frequency band to achieve such as wide frequencyrange. Even if the PLLs are in lock both temperaturevariation and changing in dividing ratio can cause the PLLsto lose lock, and the correct sub-bands must be determinedagain through recalibration. If the reference clock varies tomeet different product's specifications, the calibrationcircuits must be redesigned accordingly.

In this paper, the proposed DCO breaks the trade offbetween the delay cell bandwidth and the number of delaystages. The overall hardware complexity is reduced at agiven operating frequency range and timing resolution. Thefrequency-bouncing-reduced algorithm maximizes there-configurability of the ADPLL. This algorithm guaranteesthe ADPLL lock without any aid from calibration circuits,even during sub-band switching, during dividing ratiochanging, or under temperature variation. No switchingback-and-forth between sub-bands also improves jitterperformance. The proposed ADPLL can be synthesized with

978-1-4244-1616-5/08/$25.00 2008 IEEE 9

DigitalInterpolatorWI2:0]

2nd-orderSigma-DeltaModulator

Digital phaseselector

F14:01

Pi(i=O-15)114:0J

Fig. 5 shows the L6 digital interpolator. The paralleltri-stage buffers serve as a digital interpolator. Theweighting number of interpolation is dithered by a 2nd orderdigital L6 modulator. An edge-triggered DFF is inserted inthe re-cycle loop to avoid incomplete switching of outputclock due to mismatch of NMOS and PMOS drivingcapability. No analog or custom-designed circuit is used.The synthesizability of the proposed CCDCO is especiallyattractive for advanced deep-submicron technologies.

DCO_CUD2)Dl=Cyclel [8:0]-Cycle_d[8:0]D2=Cycle2[8:0]-Cycle_d[8:0] (4)The MUX selects final output according to the value ofControl. An example operation of the proposed algorithm isdescribed in Fig. 7. The tuning characteristic of DCO isdistributed over multiples of overlapped sub-bands. ADCO with such a frequency characteristic can coverwide-range and produces low jitters. In this example, thePLL searches the optimal point upward and N=8. In step 1,Dl> D2, Cycle2[8:0J(=1) and 12[4:0J(=15) are selected asfinal outputs. In step 2, Dl< D2, Cyclel[8:0J(=2) and I[4:0J(=8) are selected as final outputs. When the frequencysearch approaches the band edges, the next searching point isset to the center of next sub-band. The new frequency ofDCO will be slightly different from the pervious decision.The frequency-bouncing-reduced algorithm produces m~chsmaller frequency discontinuity than the sequentIalfrequency search algorithm. In the sequential searchalgorithm, the next searching point will be in the beginningof the next sub-band. If the locked point is near the band

1[4:0),F[4:0)

') Normal loop

Re-cycle loop

-Nstages-') Re-cycle loop

D Trig01

02

Con

Fig.3 Schematic of the proposed CCDCO

o -.~-----JlJ1M--

..Normal loopFig.4 Timing diagram of the CCDCO

where Td is the delay time of one delay stage, N is thenumber of delay stage in the DCO, and Cycle[8:0J is thedividing ratio, respectively. As indicated in (I), theminimum timing step is increased by a factor of Cycle[8:0J,degrading the frequency resolution at larger frequencydividing ratio.

The proposed CCDCO in Fig.3 solves this problem. It iscomposed of a multiplexer (MUX), a de-multiplexer(DEMUX), one DFF, N delay stages in the re-cycle loop,2N delay stages in the nonnal loop, one control circuit, andone L6 digital interpolator. Each delay stage is composed oftwo inverters. The timing diagram is illustrated in Fig. 4.Con controls the CCDCO to operate in a re-cycle loop or anormal loop. Once the clock propagates through the re-cycleloop, Trig will trigger the control circuit to countdownward. The count value is detennined by the DLF. Thestate of the re-cycle loop will be held until the count valueof the control circuit reaches O. The DCO will bere-configured and work in a nonnal loop. The coarse tuningis detennined by the delay of the re-cycle loop. The finetuning is achieved by digital interpolation with high speeddithering. No analog tuning technique is used. The periodof the CCDCO is digitally controlled and can be expressedas:

T--Pfoposed=Cycle[8:0}N-Td+I[4:0]-Td+SDM(F[4:0]}(Td/8) (2)where SDMO represents the high speed L6 ditheringfunction and N=8. Compared to eq. (I), the proposedCCDCO can operate over a wide frequency range whilemaintaining highest frequency resolution.

10

LF[16:0]

IF(16:0) Cyde_d(8:0] Cydel(8:0) 11(4:0) Cycle2t8:0) 12(4:0) Cyde{8:0] 114:01Initial 22 1 14step 1 23 1 2 7 1 15 1 15step 2 24 1 3 0 2 6 2 6'1eP3 25 2 3 1 2 9 2 9step 4 26 2 3 2 2 10 2 10

T[5:0]

Fig.9 Die photograph

D.DLFTo stabilize the loop, all poles of the close-loop transfer

function must be within the unit circle [4]. The latency ofindividual blocks should be also taken into account. The gainof the DLF can be dynamically controlled to reduce the locktime. In this design, the Z-domain representation of the DLFcan be expressed asDLF(Z)=G(l-O.8Z-4f(1-Z-4r1 (5)

1[4:0),F[4:0)

Fig.6 Implementation of the proposed algorithmT=1/Frequency I

III

LockedpOin~~ C,,',[8,0]~~tepl

Sequential search algorithm II

Cycle1[8:0] 11[4:0]

o

Cycle[8:0]

Fig.7 Example of the locking process

edge, the sequential frequency search algorithm may causethe sub-band to switch back and forth, leading to higher jitteror even PLL instability. With the proposed algorithm, thedecoder will update Cycle[8:0J and 1[4:0J between two setsof control code in each decision. Only a small discontinuityin DCO frequency occurs when the sub-bands switch. Itguarantees the PLL lock and avoids locking near the bandedges to reduce jitter. The ADPLL will automatically lockover a wide range operation regardless of the initialcondition without any auxiliary circuit. For differentproducts, the overhead ofthe ADPL can be minimized.

e. PFD+TDCThe PFD and counting-based TDC [5] provide frequency

and phase locking function and are shown in Fig. 8. UP andDN pulses generated by the tri-state PFD are digitized by theTDe. Unavoidable static phase error caused byautomatically synthesis can be digitally calibrated by theoffset compensation circuit. To reduce hardware complexity,a NAND gate is used as a unit cell in the TDC so that thedecoder can be replaced by a simple summer.

IV. Measurement resultsThe ADPLL is fabricated as an IP in a IP6M high-Vt

O.13um CMOS process as shown in Fig.9. Themeasurements presented are after packaging in QFN44. Theactive area of the proposed ADPLL is 220x220 um2including 3-wire control. The DCO output clock has a lowduty cycle and is not suitable for driving test pads andinstruments. Instead, the divided-by-2 clock of the DCO ismeasured. In high and low operating frequency bands, themeasured maximum timing steps are 31 and 35 ps,respectively. The dividing ratio is 8 and supply voltage is1.2V. Fig. 10 and Fig 11 show the measured jitter when theADPLL operates at 880MHz and 1.6MHz, respectively.When input frequency is 110MHz, the measuredpeak-to-peak of the cycle-to-cycle jitter is 114 ps. Theproposed CCDCO operates over a wide frequency rangewhile maintaining high frequency resolution. Fig. 12 showsthe jitter performance over different operating frequency.Since the number of cycle time of the CCDCO isproportional to the period of the input clock, the clockpropagation path will be longer in the low-frequencyoperation. For this reason, the absolute jitters in low

11

T blIP rfia e e ormance summa yII 21 31 41 51 tI'his work

Process ~.5um ~.65um O.6um ~.35um 90nm ~.13umk::MOS CMOS CMOS CMOS ('MOS ~MOSOperation frequency 150-550MHz 150K-60MHz 10-SOMHz I52-366MHz 3.6GHz 1.6-SS0MHzITiming/freQuency resolution 125ps 170ps 1.5ns ISOps 12000/256 Hz !