memory -...
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1 Memory Hierarchy Lecture notes from MKP, H. H. Lee and S. Yalamanchili (2) Reading • Sections 5.1, 5.2, 5.3, 5.4, 5.8 (some elements), 5.9
Transcript of memory -...
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Memory Hierarchy
Lecture notes from MKP, H. H. Lee and S. Yalamanchili
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Reading
• Sections 5.1, 5.2, 5.3, 5.4, 5.8 (some elements), 5.9
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• SRAM:v Value is stored on a pair of inverting gatesv Very fast but takes up more space than DRAM (4 to 6
transistors)
• DRAM:v Value is stored as a charge on capacitor (must be
refreshed)v Very small but slower than SRAM (factor of 5 to 10)
Memories: Two Basic Types
Word line
Pass transistor
Bit lineBit line bar
Word line
Pass transistor
Capacitor
Bit line
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Memory Technology
• Registersv Integrated with the CPU: fastest and most expensive
• Static RAM (SRAM)v 0.5ns – 2.5ns, $2000 – $5000 per GB
• Dynamic RAM (DRAM)v 50ns – 70ns, $20 – $75 per GB
• Magnetic diskv 5ms – 20ms, $0.05 – $0.50 per GB
• Ideal memoryv Access time of registerv Capacity and cost/GB of disk
These numbers keep changing
fast!
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The Memory Hierarchy
registers
ALU Cache
Memory
Memory
Memory
Memory Managed by the compiler
Managed by the hardware Managed by the operating system
Managed by the operating system
Cheaper
Faster
Where do Solid State Disks (SSDs) fit?
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Memory Hierarchy
From http://benchmarkreviews.com
From http://brightsideofnews.com
Intel Sandy Bridge
AMD Bulldozer
From http://hexus.net
• Going off-chip is expensive in time and energy
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Principle of Locality
• Programs access a small proportion of their address space at any time
• Temporal localityv Items accessed recently are likely to be accessed
again soonv e.g., instructions in a loop, induction variables
• Spatial localityv Items near those accessed recently are likely to be
accessed soonv E.g., sequential instruction access, array data
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Locality: Example
Not shown - the stack!
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Taking Advantage of Locality
• Memory hierarchy
• Store everything on disk
• Copy recently accessed (and nearby) items from disk to smaller DRAM memoryv Main memory and virtual memory concept
• Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memoryv Cache memory attached to CPU
• Copy most recently accessed items from cache to registers
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Cache Basic Concepts
• Block (aka line): unit of copyingv May be multiple words
• If accessed data is present in upper levelv Hit: access satisfied by upper
levelo Hit ratio: hits/accesses
• If accessed data is absentv Miss: block copied from lower
levelo Time taken: miss penaltyo Miss ratio: misses/accesses
= 1 – hit ratio
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Cache Memory
• Cache memoryv The level of the memory hierarchy closest to the CPU
• Given accesses X1, …, Xn–1, Xn
n How do we know if the data is present?
n Where do we look?
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Basic Principle: Address Breakdown
Same address can be interpreted in more than one
way
0x80080000
0x80080004
32-bit word
16 byte line
4KB page
2228
1220
Page #/Page address Byte within a page
Byte in a lineWord in a lineLine #/address
0x80081000
Examples:
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Direct Mapped Cache
• Location determined by address
• Direct mapped: only one choicev (Block address) modulo (#Blocks in cache)
n #Blocks is a power of 2
n Use low-order address bits
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Tags and Valid Bits• How do we know which particular block is
stored in a cache location?v Store block address as well as the datav Actually, only need the high-order bitsv Called the tag
• What if there is no data in a location?v Valid bit: 1 = present, 0 = not presentv Initially 0
Difference?
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Cache Example
• 8-blocks, 1 word/block, direct mapped
• Initial state
Index V Tag Data000 N001 N010 N011 N100 N101 N110 N111 N
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Cache Example
Index V Tag Data000 N001 N010 N011 N100 N101 N110 Y 10 Mem[10110]111 N
Word addr Binary addr Hit/miss Cache block22 10 110 Miss 110
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Cache Example
Index V Tag Data000 N001 N010 Y 11 Mem[11010]011 N100 N101 N110 Y 10 Mem[10110]111 N
Word addr Binary addr Hit/miss Cache block26 11 010 Miss 010
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Cache Example
Index V Tag Data000 N001 N010 Y 11 Mem[11010]011 N100 N101 N110 Y 10 Mem[10110]111 N
Word addr Binary addr Hit/miss Cache block22 10 110 Hit 11026 11 010 Hit 010
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Cache Example
Index V Tag Data000 Y 10 Mem[10000]001 N010 Y 11 Mem[11010]011 Y 00 Mem[00011]100 N101 N110 Y 10 Mem[10110]111 N
Word addr Binary addr Hit/miss Cache block16 10 000 Miss 0003 00 011 Miss 01116 10 000 Hit 000
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Cache Example
Index V Tag Data000 Y 10 Mem[10000]001 N010 Y 10 Mem[10010]011 Y 00 Mem[00011]100 N101 N110 Y 10 Mem[10110]111 N
Word addr Binary addr Hit/miss Cache block18 10 010 Miss 010
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Address Subdivision
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Block Size Considerations
• Larger blocks should reduce miss ratev Due to spatial locality
• But in a fixed-sized cachev Larger blocks Þ fewer of them
o More competition Þ increased miss ratev Larger blocks Þ pollution
• Larger miss penaltyv Can override benefit of reduced miss ratev Early restart and critical-word-first can help
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• Increasing the block size tends to decrease miss rate:
Performance
ProgramBlock size in
wordsInstruction miss rate
Data miss rate
Effective combined miss rate
gcc 1 6.1% 2.1% 5.4%4 2.0% 1.7% 1.9%
spice 1 1.2% 1.3% 1.2%4 0.3% 0.6% 0.4%
256
40%
35%
30%
25%
20%
15%
10%
5%
0%
Missr ate
64164
Block size (bytes)
1 KB
8 KB
16 KB
64 KB
256 KB
Trading off temporal vs. spatial locality
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Cache Misses
• On cache hit, CPU proceeds normally
• On cache missv Stall the CPU pipelinev Fetch block from next level of hierarchyv Instruction cache miss
o Restart instruction fetchv Data cache miss
o Complete data access
IF ID MEM WBEX
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Write-Through
• On data-write hit, could just update the block in cachev But then cache and memory would be inconsistent
• Write-through: also update memory
• But makes writes take longerv e.g., if base CPI = 1, 10% of instructions are stores,
write to memory takes 100 cycleso Effective CPI = 1 + 0.1�100 = 11
• Solution: write bufferv Holds data waiting to be written to memoryv CPU continues immediately
o Only stalls on write if write buffer is already full
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Write Through (cont.)
• Write buffers are used hide the latency of memory writes by overlapping writes with useful work
• Ensures consistency between cache contents and main memory contents at all times
• Write traffic can dominate performance
Cache
Main Memory
Write bufferCheck
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Write-Back
• Alternative: On data-write hit, just update the block in cachev Keep track of whether each block is dirty
• When a dirty block is replacedv Write it back to memoryv Can use a write buffer to allow replacing block to be
read first
• Still use the write buffer to hide the latency of write operations
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Write Back (cont.)
• Locality of writes impacts memory traffic
• Writes occur at the speed of a cache• Complexity of cache management is increased
• Cache may be inconsistent with main memory
: : : : :
:31 0
Mux
State Bits Tag Data
: :
Valid or invalid
dirty
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Write Allocation
• What should happen on a write miss?
• Alternatives for write-throughv Allocate on miss: fetch the blockv Write around: don’t fetch the block
o Since programs often write a whole block before reading it (e.g., initialization)
• For write-backv Usually fetch the block
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• Read hitsv This is what we want!
• Read missesv Stall the CPU, fetch block from memory, deliver to
cache, restart
• Write hits:v Can replace data in cache and memory (write-
through)v Write the data only into the cache (write-back the
cache later)
• Write misses:v Read the entire block into the cache, then write the
word… ?
Summary: Hits vs. Misses
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Interface Signals
CacheCPU Memory
Read/WriteValid
Address
Write Data
Read Data
Ready
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32
32
Read/WriteValid
Address
Write Data
Read Data
Ready
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128
128
Multiple cycles per access
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Cache Controller FSM
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Main Memory Supporting Caches• Use DRAMs for main memory
v Fixed width (e.g., 1 word)v Connected by fixed-width clocked bus
o Bus clock is typically slower than CPU clock
• Example cache block readv Send address(es) to memoryv Time to read a cache linev Time to transfer data to the cache
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DRAM Organization
• Consider all of the steps a lw instruction must go through!
• We will use a simple model
CoreTransaction request sent to MC
Convert to DRAM commands
Commands sent to DRAM
MemoryController
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Basic DRAM Organization
From https://www.sei.cmu.edu/cyber-physical/research/timing-verification/Multicore-scheduling-cont.cfm
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DRAM Ranks
Single Rank
8b 8b 8b 8b 8b 8b 8b 8b
64b
Single Rank
4b 4b 4b 4b 4b 4b 4b 4b
64b
4b 4b 4b 4b 4b 4b 4b 4b
Dual-Rank
8b 8b 8b 8b 8b 8b 8b 8b
64b
64b
8b 8b 8b 8b 8b 8b 8b 8b
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Increasing Memory Bandwidth
• Example cache block read for organization a.v 1 bus cycle for address transferv 15 bus cycles per DRAM accessv 1 bus cycle per data transfer
• For 4-word block, 1-word-wide DRAMv Miss penalty = 1 + 4�15 + 4�1 = 65 bus cyclesv Bandwidth = 16 bytes / 65 cycles = 0.25 B/cycle
How about bandwidth for these organizations?
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Measuring Cache Performance• Components of CPU time
v Program execution cycleso Includes cache hit time
v Memory stall cycleso Mainly from cache misses
• Computer memory stall cycles
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Measuring Performance
• These expressions themselves are an approximation
• Note the equivalence between the use of misses/instruction and misses/memory reference
• Some Example Problems
Memory Stall Cycles
Read Stalls Write Stalls
IC * Reads/Instruction * read miss rate * miss penalty IC * writes/Instruction * write miss rate * miss penalty
IC * memory references/Instruction * miss rate * miss penalty
Instructions * references/instruction Data references + Instruction references
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Cache Performance Example
• Givenv I-cache miss rate = 2%v D-cache miss rate = 4%v Miss penalty = 100 cyclesv Base CPI (ideal cache) = 2v Load & stores are 36% of instructions
• Miss cycles per instructionv I-cache: 0.02 � 100 = 2v D-cache: 0.36 � 0.04 � 100 = 1.44
• Actual CPI = 2 + 2 + 1.44 = 5.44v Ideal CPU is 5.44/2 =2.72 times faster!
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Average Access Time
• Hit time is also important for performance
• Average memory access time (AMAT)v AMAT = Hit time + Miss rate � Miss penalty
• Examplev CPU with 1ns clock, hit time = 1 cycle, miss penalty
= 20 cycles, I-cache miss rate = 5%v AMAT = 1 + 0.05 � 20 = 2ns
o 2 cycles per instruction
Increase in CPI = Base CPI +Prob(event) * Penalty(event)
• Examples
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Performance Summary
• When CPU performance increasedv Miss penalty becomes more significant
• Decreasing base CPIv Greater proportion of time spent on memory stalls
• Increasing clock ratev Memory stalls account for more CPU cycles
• Can’t neglect cache behavior when evaluating system performance
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Associative Caches
• Fully associativev Allow a given block to go in any cache entryv Requires all entries to be searched at oncev Comparator per entry (expensive)
• n-way set associativev Each set contains n entriesv Block number determines which set
o (Block number) modulo (#Sets in cache)v Search all entries in a given set at oncev n comparators (less expensive)
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Example: Fully Associative Cache
: : : : :
:Byte 31 Byte 0
Mux
Tag Byte
State Bits Associative Tag Store Data
: :
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Spectrum of Associativity
• For a cache with 8 entries
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Associativity Example
• Compare 4-block cachesv Direct mapped, 2-way set associative,
fully associativev Block access sequence: 0, 8, 0, 6, 8
• Direct mapped
Block address
Cache index
Hit/miss Cache content after access0 1 2 3
0 0 miss Mem[0]8 0 miss Mem[8]0 0 miss Mem[0]6 2 miss Mem[0] Mem[6]8 0 miss Mem[8] Mem[6]
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Associativity Example
• 2-way set associative
Block address
Cache index
Hit/miss Cache content after accessSet 0 Set 1
0 0 miss Mem[0]8 0 miss Mem[0] Mem[8]0 0 hit Mem[0] Mem[8]6 0 miss Mem[0] Mem[6]8 0 miss Mem[8] Mem[6]
n Fully associativeBlock
addressHit/miss Cache content after access
0 miss Mem[0]8 miss Mem[0] Mem[8]0 hit Mem[0] Mem[8]6 miss Mem[0] Mem[8] Mem[6]8 hit Mem[0] Mem[8] Mem[6]
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How Much Associativity
• Increased associativity decreases miss ratev But with diminishing returns
• Simulation of a system with 64KBD-cache, 16-word blocks, SPEC2000v 1-way: 10.3%v 2-way: 8.6%v 4-way: 8.3%v 8-way: 8.1%
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Set Associative Cache Organization
search
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Summary: Placement Policy
• Direct Mappedv No choice
• Set Associativev Any location in the set of linesv Replacement policy
• Fully Associativev Any line in the cachev Dictated by the replacement policy
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Summary: Replacement Policy
• Direct mapped: no choice
• Set associativev Prefer non-valid entry, if there is onev Otherwise, choose among entries in the set
• Least-recently used (LRU)v Choose the one unused for the longest time
o Simple for 2-way, manageable for 4-way, too hard beyond that
• Randomv Gives approximately the same performance as LRU
for high associativity
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Multilevel Caches
• Primary cache attached to CPUv Small, but fast
• Level-2 cache services misses from primary cachev Larger, slower, but still faster than main memory
• Main memory services L-2 cache misses
• Some high-end systems include L-3 cache
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Multilevel Caches (cont.)
• Goal: balance (fast) hits vs. (slow) missesv Techniques for the former are distinct from those for
the latter
• Goal: keep up with the processor vs. keep up with memory
Level 1 Cache
Main memory
Level 2 Cache
Example: Addressing
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Multilevel Cache Example
• Givenv CPU base CPI = 1, clock rate = 4GHzv Miss rate/instruction = 2%v Main memory access time = 100ns
• With just primary cachev Miss penalty = 100ns/0.25ns = 400 cyclesv Effective CPI = 1 + 0.02 � 400 = 9
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Example (cont.)
• Now add L-2 cachev Access time = 5nsv Global miss rate to main memory = 0.5%
• Primary miss with L-2 hitv Penalty = 5ns/0.25ns = 20 cycles
• Primary miss with L-2 missv Extra penalty = 500 cycles
• CPI = 1 + 0.02 � 20 + 0.005 � 400 = 3.4
• Performance ratio = 9/3.4 = 2.6
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Multilevel Cache Considerations
• Primary cachev Focus on minimal hit time
• L-2 cachev Focus on low miss rate to avoid main memory accessv Hit time has less overall impact
• Resultsv L-1 cache usually smaller than a single cachev L-1 block size smaller than L-2 block size
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Sources of Misses
• Compulsory misses (aka cold start misses)v First access to a block
• Capacity missesv Due to finite cache sizev A replaced block is later accessed again
• Conflict misses (aka collision misses)v In a non-fully associative cachev Due to competition for entries in a setv Would not occur in a fully associative cache of the
same total size
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Cache Design Trade-offs
Design change Effect on miss rate Negative performance effect
Increase cache size Decrease capacity misses
May increase access time
Increase associativity Decrease conflict misses
May increase access time
Increase block size Decrease compulsory misses
Increases miss penalty. For very large block size, may increase miss rate due to pollution.
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Miss Penalty Reduction
• Return requested word firstv Then back-fill rest of block
• Non-blocking miss processingv Hit under miss: allow hits to proceedv Mis under miss: allow multiple outstanding misses
• Hardware prefetch: instructions and data
• Opteron X4: bank interleaved L1 D-cachev Two concurrent accesses per cycle
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Example: Intel Sandy Bridge
• Sandy Bridge i5-2400v L1 I & D cache: 32K, 8-way, 64 byte linev L2 unified cache: 256K, 8 way, 64 byte linev L3 Shared: 6MB, 12-way 64 byte line
Source: Sandy Bridge-E layout, Intel
• Sandy Bridge i7-970
• Sandy Bridge-E can have up to 20MB L3!
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Example: Intel Nehalem
Per core: 32KB L1 I-cache, 32KB L1 D-cache, 512KB L2 cache
Intel Nehalem 4-core processor
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3-Level Cache Organization
Intel Nehalem AMD Opteron X4L1 caches(per core)
L1 I-cache: 32KB, 64-byte blocks, 4-way, approx LRU replacement, hit time n/aL1 D-cache: 32KB, 64-byte blocks, 8-way, approx LRU replacement, write-back/allocate, hit time n/a
L1 I-cache: 32KB, 64-byte blocks, 2-way, LRU replacement, hit time 3 cyclesL1 D-cache: 32KB, 64-byte blocks, 2-way, LRU replacement, write-back/allocate, hit time 9 cycles
L2 unified cache(per core)
256KB, 64-byte blocks, 8-way, approx LRU replacement, write-back/allocate, hit time n/a
512KB, 64-byte blocks, 16-way, approx LRU replacement, write-back/allocate, hit time n/a
L3 unified cache (shared)
8MB, 64-byte blocks, 16-way, replacement n/a, write-back/allocate, hit time n/a
2MB, 64-byte blocks, 32-way, replace block shared by fewest cores, write-back/allocate, hit time 32 cycles
n/a: data not available
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Concluding Remarks
• Fast memories are small, large memories are slowv We really want fast, large memories Lv Caching gives this illusion J
• Principle of localityv Programs use a small part of their memory space
frequently
• Memory hierarchyv L1 cache « L2 cache « … « DRAM memory
• Memory system design is critical for multiprocessors
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Study Guide• Given a memory system description, e.g.,
cache and DRAM parameters, what is the breakdown of the addresses?
• Given the state of the memory hierarchy be able to determine the changes required on a new access. See sample problems.
• Given a main memory and cache architecture, be able to compute the impact on CPI. See sample problems
• Given the state of a cache system in a coherent shared memory architecture be able to determine the state changes when a new access is provided
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Glossary• Associativity• Cache coherence
• Cache line or block• Cache hit
• Cache miss• Direct mapped cache • Fully associative
cache• Memory hierarchy
• Multilevel cache
• Miss penalty• Replacement policy
• Set associative cache
• Spatial locality• Snooping protocol• Temporal locality
• Tag• Write through
• Write back
