SMYOOO2 . ,MOSMemory DataBook 1984 III III \' h' \/CommercialandMilitary , :\Specifications' 1'/ ! .Jf .TEXAS INSTRUMENTS AlphanumericIndex,TableofContents,SelectionGuide InterchangeabilityGuide_ Glossary/TimingConventions/DataSheetStructure DynamicRAMandMemory SupportDevices DynamicRAMModules EPROMDevices ROMDevices StaticRAMandMemory SupportDevices ApplicationsInformation LogicSymbols MechanicalData MOSMemory DataBook SMYD002 o184-464PP-142M 1984 Cotntnercial andMilitary Specifications TEXAS INSTRUMENTS PrintedinU.S.A. IMPORTANT NOTICE TexasInstrumentsreservestheright to makechangesat-any timein order toimprovedesignandtosupply thebestproduct possible. Texas Instruments assumes no responsibility for infringement of patents or rights of others based on TexasInstruments applications assistance or product specifications, since TI does not possess full access to data concerningtheuseorapplicationsofcustomer'sproducts.TIalso assumesnoresponsibilityfor customerproduct designs. Copyright1984 by Texas InstrumentsIncorporated AlphanumericIndex,Tableof Contents,Selection ,Guide InterchangeabilityGuide.. Glossary/TimingConventions/DataSheet Structure Dynamic RAMandMemory Support Devices DynamicRAMModules EPROMDevices ROM Devices StaticRAMand Memory Support Devices ApplicationsInformation LogicSymbols MechanicalData -6' :s-O) :::I C 3 (1) ... r;' S-c. (1) !< -I 0) C" CD o .... ALPHANUMERICINDEXTODATASHEETS SMJ2516 SMJ2532 SMJ2564 SMJ2708 SMJ27L08 SMJ4164 Page 6-1 6-11 6-21 6-31 6-31 4-39 SMJ4416....................4-85 SMJ5517....................8-25 TM4164EC4..................5-1 TM4164EL9..................5-5 TM4164FL8..................5-9 TMS2114....................8-1 TMS2114L...................8-1 TMS2150....................8-7 TMS2516....................6-1 TMS2532....................6-11 TMS2564....................6-21 TMS2708....................6-31 TMS27L08...................6-31 TMS2732A...................6-47 TMS2764 TMS4016 TMS4044 TMS40L44 TMS4116 TMS4161 TMS4164 TMS4256 TMS4257.................. . TMS4416.................. . TMS4464.................. . TMS4500A................. . TMS4664.................. . TMS4732.................. . TMS4764.................. . TMS4964.................. . TMS27128................. . TMS47128................ .. TMS47256................. . Page 6-53 8-13 Q) 8-19 "C '5 8-19e,:, 4-1t: 4-15 0 '';::::; 4-39 CJ Q) 4-63 1) 4-63 C/) 4-85 0 ... 4-107 t: Q) 4-125 ... t: 7-1 0 7-7 (,J .... 7-13 0 7-19 Q) 6-61 :s CO 7-27 I-7-37 >< Q) "C ..5 CJ '': Q) E ::::s t: CO ..c: c... < ~ Q) e-CD o .... TABLEOFCONTENTS(Concluded) TMS2732A5V32,768-bit(4Kx8)....................... TMS27645V65,536-bit(8Kx8)....................... TMS271285V131,072-bit(16K x 8)...................... ROMDEVICES TMS46645V65,536-bit(8Kx8)....................... TMS47325V32,768-bit(4Kx8).................... '... TMS47645V65,536-bit(8Kx8)......~.............. TMS49645V65,536-bit(8Kx8)....................... TMS471285V131,072-bit(16K x8)...................... TMS472565V262,144-bit(32Kx8)...................... STATICRAMandMEMORYSUPPORTDEVICES TMS21144,096-bit(1K x 4).............................. . TMS2114L4,096-bit(1 K x 4).............................. . TMS2150 TMS4016 TMS4044 TMS40L44 SMJ5517 CacheAddressComparator............................ . 16,384-bit(2K x 8).............................. . 4,096-bit(4K x1).............................. . 4,096-bit(4K x1).............................. . 16,384-bit(2K x 8).............................. . APPLICATIONSINFORMATION 64KDynamicRAMRefreshAnalysisSystemDesignConsiderations.......... . 256-CycleRefreshConversion...................................... . TMS4164AandTMS4416InputDiodeProtection....................... . TMS4164andTMS4416Interlock Clock.............................. . Introduction toSurfaceMount Technology............................ . TTLDriversforTMS4416-1 5...................................... . TMS4416/7220Graphics......................................... . TMS4416/TMS4500AEvaluationBoard.............................. . TMS4500AALEandACXTiming................................... . TMS4500ADRAMControllerConfiguredfor theTMS99000Series 16-Bit Microprocessors........................................ . TMS4500A/8088Interface........................................ . TMS4500A/MC68000Interface.................................... . AnIntroductiontoCacheMemory SystemsandtheTMS21 50.............. . HighDensityROMsInConsumerGameSystems........................ . LOGICSYMBOLS Explanationof NewLogicSymbolsforMemories 6-47 6-53 6-61 7-1 7-7 7-13 7-19 7-27 7-37 8-1 8-1 8-7 8-13 8-19 8-19 8-25 9-1 9-3 9-7 9-11 9-15 9-25 9-31 9-39 9-45 9-51 9-63 9-69 9-85 9-93 10-1 MECHANICALDATA.................................................11-1 1-4 MOS LSI WORDS BITSPERWORD 14 (4K) SRAMs 1K TMS2114 TMS2114L 2K (4K) SRAMs 4KTMS4044 TMS40L44 8K (16K)(64K) 16K DRAMsDRAMs TMS4116TMS4416 SMJ4416 32K (64K)(256K) DRAMsDRAMs 64KTMS4161TMS4464 TMS4164 SMJ4164 (256K) 256K DRAMs TMS4256 TMS4257 (Numbersinparenthesisindicateoverallcomplexity.) TEXAS INSTRUMENTS RAMs,ROMs,EPROMs SELECTIONGUIDE 8 (8K) EPROMs TMS2708 TMS27L08 SMJ2708 SMJ27L08 (16K) SRAMsEPROMs TMS4016TMS2516 SMJ5517SMJ2516 TMS2716 (32K) ROMsEPROMs TMS4732TMS2532 SMJ2532 TMS2732A (64K) ROMsEPROMs TMS4664TMS2564 TMS4764SMJ2564 TMS4964TMS2764 (128K) ROMsEPROMs TMS47128TMS27128 (256K) ROMs TMS47256 POSTOFFICEBOX225012DALLAS. TEXAS75265 Q) "'C 'S (!J c o '';:; (.) Q) Q) en u) ... C Q) ... C o U .... o Q) :c CO ... >< Q) "'C C (.) '':: Q) E ::l C CO .r:. c. :;a: 1-5 -6' :s-O) :::s c 3 CD ... n' :::s c. CD ?< -t 0) e-m-e ..... (") e :::s ... CD :::s ... !!' CA CD m-(") ... c' :::s G') c c: ~ 1-6 AlphanumericIndex,Tableof Contents,Selection Guide Interchangeability Guide Glossary/TimingConventions/DataSheet Structure Dynamic RAMandMemory Support Devices DynamicRAMModules EPROMDevices ROMDevices Static RAMandMemory Support. Devices ApplicationsInformation LogicSymbols MechanicalData S" ... (1) .. (") :::r Q) ~ cc (1) Q) g ;::;" < G') r::: c: (1) INTERCHANGEABILITYGUIDE PART1- ALTERNATEVENDORPARTNUMBERING(EXAMPLES) TEXASINSTRUMENTS(TI) EXAMPLE: TMS TMSCommercialMaS SMJMilitaryMaS 2114L-45 Max Access - 445ns-20200 ns - 555ns-25250 ns - 770ns-30300 ns -10 100 ns-35350 ns -12 120 ns .-45450 ns -15 150 ns tInclusionof an"L" intheproductidentification indicatesthedeviceoperatesatlowpower. ADVANCEDMICRODEVICES(AMD) Am91 90DRAM 91SRAM 92ROM 17/27EPROM L AMERICANMICROSYSTEMS,INC.(AMI) S2364A Max Access A350ns B250ns TEXAS INSTRUMENTS N (J.g, ) FPPlasticChipCarrier JCerpak/Cerdip JD SideBraze MCChip-on-Board NPlasticDIP 28 POSTOFFICEBOX225012DALLAS. TEXAS75265 E L M S L -40C toaoc ooCto70C -55C to125C - 55C to100C -15 Max Access -7070ns -10100 ns -15150 ns -20200ns CI) "C S ~ >-~ :c CO CI) en t: CO ..r::: CJ .... CI) .... ..5 2-1 :r .... (1) .. () :r II) ::s CO (1) II) g; ;:;: -< C) r:: c: (1) 2-2 INTERCHANGEABILITYGUIDE ELECTRONICARRAYS,INC.(EA) EA ~ 27XX EPROM OtherROM EMM/SEMI 4014A ( t SpeedRange) MaxAccess ASlow 8Fast FAIRCHILD F3528 tMay beomitted. *Inclusionof an"L" indicates low power version. A -A (s ...I. ...) Max Access - 1(orAlSlowest -2 (orBI -3 -4 -5Fastest TEXAS INSlRUMENTS POSTOFFICEBOX225012DALLAS. TEXAS 75265 FUJITSU MB8264 MBFujitsu MBMIndustryStandard. Prefix HITACHI ~~ HMRAM HNROM INMOS IMS2600 A ..::.3.. Max Access -1Fastest -2 -3 -4Slowest -15 Max Access -4545ns -5555ns -10100 ns -12120 ns -15150 ns TEXAS INSTRUMENTS INTERCHANGEABILITYGUIDE -10 . (s....tn .. ) Max Access -10100 ns -12120 ns -15150 ns POSTOFFICEBOX225012DALLAS, TEXAS75265 Q) "'C S C!J > ~ :c CO Q) C) c CO .s::. (,) .. Q) ... .5 2-3 :::l ... CD ... C') ::r Dl :::l CC CD Dl g ;:;' -< INTERCHANGEABILITYGUIDE INTEL G)INTERSIL/AMS c c: CD 2-4 IM7 MOSTEK MK t550nsfor SRAMsandROMs tDRAMs 4564-15 (Spa",L.,) MaxAccess -5555ns4250 ns -7070ns-5300 ns -9090 ns- 6350 ns 1120ns-15150 ns:l: 2150 ns-20 200 ns:l: 3200nst -25250 ns :l: TEXAS., INSTRUMENTS MaxAccess -1Fastest -2 -3 -4 -5 -6Slowest MaxAccess - 1(- 111Fastest -2 (-121 -3 -4Slowest POSTOFFICEBOX225012DALLAS. TEXAS75265 MOTOROLA MCM -t (ICMemoryPrefix) tInclusionof an"L" indicateslow power version. NATIONALSEMICONDUCTOR 4164 OKISEMICONDUCTOR(OKI) MSM3764 -15 Max Access -12120 ns -15150 ns. -20200 ns -20 Max Access -12120 ns -15150 ns -20200 ns TEXAS INSTRUMENTS INTERCHANGEABILITYGUIDE -15 Max Access -10100 ns -12120 ns -15150 ns .-20200 ns -25250 ns -30300 ns -45450 ns POSTOFFICEBOX 225012DALLAS. TEXAS 75265 Q) "C S ~ > :!: :c ctI Q) C) c: ctI .c 2-5 (,) ... Q) ~ .5 5" ..... C ., (') :r m ~ CO C m g; ;:;" -< G') c c: C 2-6 INTERCHANGEABILITYGUIDE NIPPONELECTRICCORPORATION(NEC) JLPD SIGNETICS 23128 SYNERTEK Sy 4164 -25 MaxAccess -20200ns -25250ns -30300 ns -45450 ns 2150 "Inclusion of analphacharacterindicatesa devicemodification. A -4 MaxAccess -2200ns -3300 ns -445ns -555ns TEXAS. INSTRUMENTS -2 MaxAccess -0200 ns -1250 ns -2100 ns -3150 ns POSTOFFICEBOX225012DALLAS, TEXAS 75265 TOSHIBA TMM4164 VLSITECHNOLOGY VT4500A -3 (5."'1.. .. ,) Max Access -1Fastest -2 -3 -4 -5Slowest -15 (Sf.JR .. ' ) MaxAccess -15150 ns -20200 ns -25250 ns TEXAS INSTRUMENTS POSTOFFICEBOX225012DALLAS, TEXAS 75265 INTERCHANGEABILITYGUIDE CD "C 'S C!) > :l: :s ca CD C) C ca .c (,) ... CD .... ..5 2-7 5' .... CD ... (') :::r Q) .:::J CC CD Q) g ==t' -< C) r::: is: CD 2-8 INTERCHANGEABILITYGUIDE PARTII- SECONDSOURCES* "Basedonavailablepublisheddata.(Officialsecondsourcingagreementsnot necessarilyimplied.) Alldeviceslistedoperateover theOOCto 70Ctemperaturerange. DYNAMICRAMS ORGANIZATIONMAX ACCESS VENDOR TISECONDSOURCES 16Kx 1MaxAccess=250 nsTI (3Supply)AMD Fairchild Fujitsu Hitachi Intersil ITT Mitsubishi Mostek Motorola National NEC Toshiba 64Kx 1MaxAccess=200 nsTI (5V)Fairchild Fujitsu Hitachi INMOS Intel MicronTech. Mitsubishi Mostek Motorola National NEC OKI Toshiba 16Kx4MaxAccess=200nsTI (5V)Fujitsu Hitachi INMOS 256K x 1MaxAccess=200nsTI (5V)Fujitsu Hitachi Mitsubishi Motorola NEC OKI Toshiba WesternElectric tThesedeviceshavea256 cycle.4msrefreshscheme.Allothersrefreshin2ms. TEXAS INSTRUMENTS POSTOFFICEBOX225012DALLAS. TEXAS 75265 PARTNUMBER TMS4116 Am9016 F4116 MB8116 HM4716A IM4116 ITT4116 M5K4116 MK4116 MCM4116B MM5290 /LPD416 TMM416 TMS41641 F4164 MB8264A HM4864 IMS2600t 2164 MT4264 t M5K4164 MK4564 MCM6665 NMC4164t /LPD4164 MSM3764 TMM4164 TMS4416 MB81416 HM48416AP IMS2620 TMS4256/TMS4257 MB81257/MB81256 HM50257 MSM4256 MCM6256 MSM37256 TMM41256 WCM41256 STATICRAMS ORGANIZATION 4Kx1 (5V) 1Kx4 (5V) 2Kx8 (5V) INTERCHANGEABILITYGUIDE MAX ACCESS VENDOR TISECONDSOURCES Max Access=450 nsTI AMD Intersil Intel NationalSC Mitsubishi Mostek NEC Synertek Max Access=450 nsTI AMD EA EMM/SEMI Fairchild Hitachi Intel Mitsubishi Motorola NationalSC NEC OKI Synertek Max Access=250 nsTI Fairchild Fujitsu Mitsubishi Mostek OKI Toshiba TEXAS INSTRUMENTS POSTOFFICEBOX225012DALLAS, TEXAS 75265 PARTNUMBER TMS4044/TMS40L44 Am4044 IM7141/IM7141L 2141/2141L MM2141 M5T4044 MK4104 I'PD4104 SY2141/SY2141 L TMS2114/TMS2114L Am9114E/91L14E EA2114L 2114 2114 HM472114A 2114A/2114AL M5L2114L MCM2114/MCM21L14 MM2114/MM21 L 14 I'PD2114/I'PD2114L MSM2114/MSM2114L SY2114/SY2114A TMS4016 F3528 MB8128 M58725 MK4802 MSM2128 TMM2016 2-9 INTERCHANGEABILITYGUIDE EPROMS ORGANIZATION 1Kx8 (3Supply) 2KxS (3Supply) 2Kx8 (5V) 4KxS (5V) 4KxS (5V) SKxS (5V) SKxS (5V) 16Kx8 (5V) 2-10 MAX ACCESS VENDOR TISECONDSOURCES MaxAccess=450 nsTI AMD Fairchild Fujitsu Intel Motorola NationalSC OKI MaxAccess=450 nsTI Motorola MaxAccess=450 nsTI AMD Fujitsu Hitachi Intel Mitsubishi Mostek Motorola National NEC OKI Toshiba Max Access=450 nsTI Hitachi Motorola National Max Access= 450 nsTI AMD Fairchild Fujitsu Hitachi Intel Mitsubishi NEC OKI Toshiba MaxAccess=450 nsTI Motorola. Max Access=450 nsTI AMD Fairchild Fujitsu Hitachi Intel Mitsubishi OKI MaxAccess=250 nsTI Fujitsu Intel TEXAS INSlRUMENTS POSTOFFICE BOX225012DALLAS. TEXAS75265 / PARTNUMBER TMS270S/TMS27LOS 270S F270S MBS518 2708/270SL MCM270S MM270S MSM270S TMS2716 TMS2716/TMS27 A 16 TMS2516 2716 MBM2716 HN462716 2716 M5L2716 MK2716 MCM2716/MCM27L 16 MM2716 /LPD2716 MSM2716 TMM323 TMS2532 HN62532 MCM2532/MCM25L32 MM2532 TMS2732A Am2732 F2732 MBM2732A HN462732 2732A M5L2732 /LPD2732 MSM2732 TMM2732 TMS2564 MCM68764 TMS2764 Am2764 2764 MBM2764 HN4S2764 2764 M5L2764 MSM2764A TMS2712S MBM27128 27128 AlphanumericIndex,Tableof Contents,Selection Guide InterchangeabilityGuide Glossary/TimingConventions/DataSheetStructure Dynamic .RAMandMemory Support Devices DynamicRAMModules EPROMDevices .. ROMDevices Static RAMandMemorySupport Devices Application$Information .. Logic Symbols MechanicalData G) 5" en en D) ~ -< --t 3 :r CQ o o :s < CD :s .. o :s en -o CII .. CII en =-CD CD .. en .. ~ c (') r+ C ... CD GLOSSARY fTIMINGCONVENTIONS/DATASHEETSTRUCTURE PART1- GENERALCONCEPTSAND TYPESOFMEMORIES Address- Any givenmemorylocationinwhichdatacanbestored or fromwhichit canberetrieved. Automatic Chip-Select/Power Down- (seeChipEnableInput) Bit - Contraction of Binary digiT, i.e., a1 or a 0; in electrical terms the value of a bit may be represented by the presence or absenceof charge,voltage,or current. Byte- Aword of8bits(seeword) Chip Enable Input - A control input to an integrated circuit that when active permits operation of the integrated circuit for in-put, internal transfer, manipulation, refreshing, andlor output of data and when inactive causes the integrated .circuit to beina reducedpower standbymode. Chip Select Input - Chip select inputs aregating inputs that control the input to and output from the memory. They may be of two kinds: 1.Synchronous - Clockedllatched with the memory clock. Affects the inputs and outputs for the duration of that memory cycle. 2.Asynchronous - Hasdirectasynchronouscontrolofinputsandoutputs.Inthereadmode,anasyn-chronous chipselect functionslikeanoutput enable. Column Address Strobe (CAS)- Aclock used in dynamic RAMs to control the input of column addresses.It canbeactive high(CAS)oractivelow(CAS). Data- Any informationstored or retrievedfroma memory device. Dynamic (Read/Write)Memory (DRAM)- Areadlwrite memory inwhich the cells require the repetitive application of con-trol signalsin order to retainthestored data. NOTES:1 .Thewords"read/write"maybeomitted fromthetermwhenno misunderstandingwillresult. 2.Suchrepetitiveapplicationof thecontrolsignalsis normally calledarefreshoperation. 3.Adynamic memorymayusestatic addressingorsensingcircuits. 4.This definition applies whether the control Signals are generated inside or outside the integrated cir-cuit. Electrically Alterable Read-Only Memory (EAROM)- Anonvolatile memory that canbefield-programmedlikea PROMor EPROM,but that canbeelectricallyerasedbyacombinationof electricalsignalsat its inputs. Erasableand ProgrammableRead-OnlyMemory(EPROM)/ReprogrammableRead-OnlyMemory- Afield-programmable read-onlymemory that canhave thedatacontent of eachmemorycellalteredmorethanonce. Erase- TypicallyassociatedwithEPROMsandEAROMs.Theprocedurewherebyprogrammeddataisremovedandthe. devicereturns to its unprogrammedstate. Field-Programmable Read-Only Memory - Aread-only memory that after being manufactured, can have the data content of eachmemorycellaltered. Fixed Memory - Acommon term for ROMs,EPROMs,EAROMs, etc., containing data that is not normally changed.A more precisetermfor EPROMsandEAROMsisnonvolatile sincetheir datamaybeeasilychanged. FullyStatic RAM- Ina fullystaticRAM,the peripheryaswellasthememoryarrayisfullystatic.Theperipheryisthus always active andreadyto respondto input changes without the needfor clocks.There is no prechargerequiredfor staticperiphery. K- Whenusedinthecontextofspecifyingagivennumberofbitsofinformation,1 K=210 =1024bits.Thus, 64K=64X1024=65,536 bits. Large-Scale Integration (LSI)- The description of any ICtechnology that enables condensing more than100 gates onto a singlechip. TEXASINSTRUMENTS INCORPORATED POSTOFFICEBOX225012DALLAS. TEXAS75265 Q) ... ::::J ... CJ ::::J ... ... en ... Q) Q) .c en CO ... CO c en c o '';::; c Q) > C o U t:n c 'E i= -> ... CO (/) (/) o a 3-1 G) 5" en en Q) -< --I 3' 5' CO n o :::s < Q) :::s ... 0' :::s en -C Q) ... Q) tJ) :r Q) Q) ... tJ) ... c n ... c Q) 3-2 GLOSSARY/TIMINGCONVENTIONS/DATASHEETSTRUCTURE Mask-Programmed Read-Only Memory- Aread-onlymemory inwhich the datacontent of eachcellis determined during manufacturebythe useof a mask.thedatacontent thereafter beingunalterable. Memory- Amedium capableof storageof information fromwhich theinformation canberetrieved. Memory Cell - The smallest subdivisionof a memory into which a unit of data has been or can beentered. in which it is or canbestored.andfromwhichit canberetrieved. Metal-Oxide Semiconductor (MOS)- The technology involving photolithographic layering of metal andoxide to produce a semiconductor device. NMOS- AtypeofMOStechnologyinwhichthebasicconductionmechanismisgovernedbyelectrons.(Shortfor N-channel MOS) Nonvolatile Memory- Amemory inwhich the data content ismaintainedwhether the power supply isconnectedor not. Output Enable- Acontrol input that. when true.permits data to appear at the memory output. and when false.causes the output to assumea high-impedancestate.(Seealsochipselect) PMOS- Atype of MOS technology inwhich the basic conduction mechanism isgoverned by holes.(Short for P-channel MOS) Parallel Access - Afeature of a memory by which all the bits of a byte or word are entered simultaneously at several inputs or retrievedsimultaneouslyfromseveraloutputs. Power Down- Amode of a memory device during which the device is operating in a low-power or standby mode. Normally reador write operationsof thememory arenot possibleunder this condition. Program- Typically associatedwith EPROMmemories.theprocedure whereby logical O's(or"s) arestoredinto various desiredlocationsina previouslyeraseddevice. ProgramEnable- Aninputsignalthat whentrue.puts a programmablememory deviceinto theprogrammode . Programmable Read-Only Memory (PROM)- Amemory that permits access to any of its address locations in any desired se-quencewith similar accesstimeto eachlocation. NOTE:The term ascommonlyuseddenotes a read/write memory. Read- Amemoryoperationwhereby dataisoutput froma desiredaddresslocation. Read-On/y Memory (ROM)- Amemoryinwhich the contents arenot intendedto bealteredduringnormaloperation. NOTE:Unlessotherwisequalified.the termmemory"impliesthatthecontent isdeterminedby its structure andisunalterable . ReadIWrite Memory - Amemory in which each cellmay be selected by applying appropriate electrical input signals and the storeddata may beeither (a)sensedat appropriate output terminals.or (b)changedinresponse to other similar elec-trical input signals. Row Address Strobe (RAS)- Aclock used in dynamic RAMs to control the input of the row addressed.It can be active high (RAS)or activelow (RAS). Scaled-MOS (SMOS)- MOS technology under which the device is scaled down in size in three dimensions and in operating voltagesallowingimprovedperformance. Semi-Static(Quasi-Static,Pseudo-Static)RAM- Inasemi-staticRAM.theperipheryisclock-activated(i.e .dynamic). Thus the periphery isinactive until clocked. and only one memory cycle is permitted per clock.The peripheral circuitry must beallowed to resetafter eachactive memory cyclefor a minimumprecharge time.Norefreshisrequired. Serial Access - A feature of a memory by which all the bits are entered sequentially at a single input or retrieved sequentially forma singleoutput. Static RAM (SRAM)- Aread/write random-access device within which information is stored as latched voltage levels. The memory cellisa static latch that retains data aslong aspower is applied to the memory array.Norefreshisrequired. The typeof peripherycircuitry sub-categorizesstaticRAMs. TEXASINSTRUMENTS INCORPORATED POSTOFFICE BOX225012DALLAS, TEXAS75265 GLOSSARY/TIMINGCONVENTIONS/DATASHEETSTRUCTURE Very-Large-Scale Integration(VLS!)- The description of any ICtechnology that ismuch more complex than large-scale in-tegration (LSI),andinvolves a much higher equivalent gate count. At this time an exact definition including a minimum gatecount hasnot beenstandardizedby JEDECor theIEEE. VolatileMemory- Amemory inwhich the datacontent islost whenpower suppliedisdisconnected. Word- Aseriesof oneor morebits that occupya given addresslocation andthat canbestoredandretrievedinparallel. Write- Amemory operationwherebydataiswritten into a desiredaddresslocation. WriteEnable- Acontrol signal that when true causes the memory to assume the write mode,andwhen false causes it to assume thereadmode. PART 11- OPERATINGCONDITIONSAND CHARACTERISTICS(INCLUDINGLETTERSYMBOLS) Capacitance Theinherent capacitanceoneverypin,which canvarywith variousinputs andoutputs. Examplesymbology: CiInput capacitance CoOutput capacitance Ci(D)Input capacitance,data input Current High-level input current,IIH Thecurrentintoaninput whenahigh-levelvoltageisapplied-tothatinput. High-level output current,10H The current into *anoutput with input conditions applied that according to the product specification willestablisha hig!;llevelat theoutput. Low-level input current,IlL Thecurrent into aninput when alow-levelvoltage isappliedto that input. Low-level output current,10L Thecurrent into *anoutput with input conditionsapplied that according to the product specificationwillestablish a lowlevelat theoutput. Off-state Ihigh-impedance-state)output currentlof a three-stateoutput),10Z Thecurrent into *anoutput having three-state capability with input conditions appliedthat according tothe product specificationwill establishthehigh-impedance stateat theoutput. Short-circuit output current,lOS The current into *an output when the output is short-circuited to ground lor other specified potential) with input condi-tions appliedto establishtheoutput logiclevel farthest fromgroundpotential(orother specifiedpotential). Supply current IBB'ICC,100, Ipp Thecurrent into, respectively,theVBB,VCC,VDD,Vpp supply terminals. OperatingFree-Air Temperature The temperature(T A)rangeoverwhich thedevicewilloperateandmeet the specifiedelectricalcharacteristics. OperatingCaseTemperature The case temperature ITC)range over which the device will operate and meet the specified electrical characteristics. "Current out of aterminalisgivenas anegative value. TEXASINSTRUMENTS INCORPORATED POSTOFFICEBOX225012DALLAS,TEXAS75265 Q) .. ::s ... (.) ::s .. ... CJ) ... Q) Q) ..c: CJ) CO ... CO Q -en c o "+: c Q) > C o (.) C) C "s i= -~ CO en en o (5 3-3 C') 5" C/) C/) Q) .. '< --I 3' 5' eQ o o ::J < CD ::J r+ cr ::J (I) C I r+ I en :r-CD CD r+ en r+ ., C (') r+ C ., R 3-4 GLOSSARY /TIMINGCONVENTIONS/DATASHEETSTRUCTURE Voltage High-level input voltage,VIH Aninputvoltagewithinthemorepositive(lessnegative)of thetworangesofvaluesusedtorepresentthebinary variables. NOTE:Aminimum is specified that is the least positive value of high-level input voltage for which operation of the logic elementwithinspecificationlimitsisguaranteed. High-leveloutput voltage,VOH Thevoltageatanoutputterminalwithinputconditionsappliedthataccordingtotheproductspecificationwill establisha highlevelat the output. Low-level input voltage,VIL An input voltage level within the less positive (more negative) of the two ranges of values used to represent the binary variables. NOTE:Amaximum is specified that is the most positive value of low-level input voltage for which operation of the logic elementwithinspecificationlimitsisguaranteed . Low-leveloutput voltage,VOL Thevoltageatanoutputterminalwithinputconditionsappliedthataccordingtotheproductspecificationwill establisha low levelat the output. Supply Voltages,VBB,Vee, Vee, Vpp The voltages supplied to the corresponding voltage pins that are required for the device to function. From one to four of thesesuppliesmay benecessary,alongwith ground,VSS. Time Intervals New or reviseddata sheets in this book useletter symbols in accordance with standards recently adopted by JEOEC, the IEEE,and the IEC. Two basic forms are used. The first form is usually used in this book when intervals can easily be classified asaccess,cycle, disable,enable,hold,refresh,setup, transition, or valid times andfor pulse durations. The secondformcanbeusedgenerally but in this book isusedprimarily for time intervals not easily classifiable. These-cond(unclassified) form will bedescribed first.Since some manufacturers use this form for all time intervals, symbols inthe unclassifiedformaregivenwith the examples for most of the classified time intervals. Unclassifiedtime intervals Generalizedletter symbolscanbeusedto identify almost any timeintervalwithout classifying it using traditionalor contrived definitions.Symbols for unclassified time intervals identify two signal events listed infrom-to sequence us-ingtheformat: t A B - C ~ Subscripts Aand C indicate the names of the signalsfor which changes of state or levelor establishment of state or level constitute signal events assumed to occur first and last, respectively, that is, at the beginning and end of the time interval. Every effort is made to keep the A and C subscript length down to one letter, if possible (e.g., R for RAS and C for CASof TMS 4116). Subscripts Band 0indicate the direction of the transitions and/or the final states or levels of the signals represented by AandC,respectively.Oneor two of thefollowingisused: H =highor transitionto high L=low or transition to low V=a validsteady-state level X=unknown,changing,or"don't care"level Z=high-impedance(off)state TEXASINSTRUMENTS INCORPORATED POSTOFFICEBOX225012DALLAS,TEXAS75265 GLOSSARY!TIMINGCONVENTIONS/DATASHEETSTRUCTURE Thehyphen betweentheBand C subscripts isomittedwhen no confusionislikelytooccur. Forexamples of symbolsof thistype,seeTMS4116 (e.g.,tpLCU. Classified time Intervals (generalcomments,specific times follow) Because of the information containedin the definitions,frequently the identification of oneor both of the two signal events that begin andend the intervals canbesignificantly shortenedcompared to theunclassifiedforms.For exam-ple,it is not necessary to indicate inthe symbol that anaccess time endswith validdataat theoutput.However,if both signals arenamed(e.g.,ina holdtime),thefrom-tosequenceismaintained. Access time Thetimeinterval between the applicationof a specificinput pulseandtheavailabilityof validsignalsat anoutput. Examplesymbology: Classified talA) tatS),ta(CS) Cycle time Unclassified tAVOV tSLOV Description Access timefromaddress Accesstimefromchipselect(low) Thetime intervalbetween thestart andendof a cycle. NOTE:The cycle time is the actualtime intervalbetween two signaleventsandisdeterminedby thesystem in which the digital circuit operates.Aminimum valueisspecifiedthat istheshortest interval that must be allowedfor thedigital circuit to performa specifiedfunction(e.g.,read,write,etc.)correctly. Examplesymbology: Classified tc(RI,tc(rd) tc(WI Unclassified tAVAV(R) tAVAV(W) Description Readcycle time Write cycle time NOTE:R is usually used as the abbreviation for "read"; however, in the case of dynamic memories,"rd" isused to permitR to standfor RAS. Disable time (of a three-stateoutput) Thetime interval between the specifiedreference points onthe input andoutput voltage waveforms,withthe three-state output changingfromeither of thedefinedactive levels(highor lowlto a high-impedance(offlstate. Examplesymbology: Classified tdis(S) tdis(W) Unclassified tSHOZ tWLOZ Description Output disable time after chipselect (high) Output disable timeafterwriteenable(low) Thesesymbolssupersedetheolder forms tpvz or tpXZ. Enabletime(of a three-stateoutputl The time interval between the specifiedreference points onthe input andoutput voltage waveforms,with the three-stateoutput changingfroma high-impedance(off)state to eitherof thedefinedactivelevels(highorlow). NOTE:For memories theseintervals areoften classifiedasaccess times. Examplesymbology: Classified ten(SL) Unclassified tSLOV Description Output enabletime after chipselectlow Thesesymbolssupercede the older formtpZV. TEXASINSTRUMENTS INCORPORATED POSTOFFICE BOX225012DALLAS. TEXAS75265 ... (1) (1) .c en ~ ... ~ C -t/) C o '';::; c (1) > C o U C) c 's i= -> ... ~ t/) t/) o (5 3-5 C) 5" (I) (I) Q) .. < ~ 3' :i' cc n o ::J c::: CD ::J ... 0' ::J (I) C D) ... D) en :::r CD CD ... en ... .. c: (') ... c: .. CD 3-6 GLOSSARY/TIMINGCONVENTIONS/DATASHEETSTRUCTURE Holdtime Thetimeintervalduringwhichasignalisretainedataspecifiedinputterminalafteranactivetransitionoccursat another specifiedinput terminal. NOTES:1.The hold time is the actual time interval between two signalevents and isdetermined by the system inwhichthedigitalcircuitoperates.Aminimumvalueisspecifiedthat istheshortestintervalfor whichcorrectoperationof thedigitalcircuit isguaranteed. 2.The hold time may have a negative value in which case the minimum limit defines the longest interval (between the releaseof the signal and the active transition)for which correct operation of the digital circuit isguaranteed. Examplesymbology: Classified th(D) th(RHrd) th(CHrd) th(CLCA) th(RLCA) th(RA) Unclassified tWHDX tRHWH tCHWH t C L ~ C A X tRL-CAX tRL-RAX Description Dataholdtime(afterwritehigh) Read(write enablehigh)holdtimeafterRAShigh) Read(writeenablehigh)holdtimeafter CAShigh) Columnaddressholdtimeafter CASlow Columnaddressholdtimeafter RASlew Rowaddressholdtime(afterRASlow) Theselast threesymbolssupersedetheolder forms: NEWFORM th(CLCA) th(RLCA) th(RA) OLDFORM th(ACl) th(ARL) th(AR) NOTE:The fromto sequenceinthe order of subscriptsin theunclassified formismaintainedinthe classifiedform. In the caseofhold times, this causesthe order to seemreversedfrom what wouldbesuggestedby the terms. Pulseduration(width) The timeintervalbetweenspecifiedreferencepointsonthe leadingandtrailingedgesof thepulsewaveform. Examplesymnbology: ClassifiedUnclassified tw(W)tWLWH twIRL)tRLRH Refreshtime interval Description Writepulseduration Pulseduration,RASlow Thetimeintervalbetweenthebeginningsofsuccessivesignalsthatareintendedtorestorethelevelinadynamic memorycellto its originallevel. NOTE:The refreshtime intervalistheactualtimeintervalbetween two refreshoperations andisdetermined by thesysteminwhich thedigital circuit operates.Amaximum valueisspecified that isthelongest interval forwhichcorrect operationof thedigitalcircuitisguaranteed. Examplesymbology: ClassifiedUnclassifiedDescription trf Refreshtimeinterval TEXASINSTRUMENTS INCOR PORATEO POSTOFFICEBOX225012DALLAS, TEXAS75265 GLOSSARY/TIMINGCONVENTIONS/DATASHEETSTRUCTURE Setup time The time interval between the application of a signal at a specified input terminal and a subsequent active transition at anotherspecifiedinput terminal.. NOTES:1.The setup time is the actual time interval between two signal events and is determined by the system inwhichthedigitalcircuitoperates.Aminimumvalueisspecifiedthat istheshortestintervalfor which correctoperationof the digitalcircuit isguaranteed. 2.The setup time may have a negative value in which case the minimum limit defines the longest inter-val (between the active transition andthe application of the other signal)for which correct operation of the digitalcircuitisguaranteed. Examplesymbology: Classified tsu(D) tsu(CA) tsu(RA) Unclassified tDVWH tCAV-CL tRAV-RL Description Datasetup time(beforewritehigh) Columnaddresssetuptime(beforeCASlow) Rowaddresssetup time(beforeRASlow) Transition times(also calledriseandfall times) Thetime intervalbetween two referencepoints(10%and90%unlessotherwise specified)on thesamewaveform that ischangingfromthedefinedlowlevelto thedefinedhighlevel(risetime)orfromthedefinedhighleveltothe definedlow level(falltime). Examplesymbology: Classified tt tt(CH) tr(C) tf(C) Validtime (a)General Unclassified tCHCH tCHCH tCLCL Description Transitiontime (general) Low-to-high transitiontimeof CAS CASrisetime CASfalltime The timeinterval duringwhich a signalis(orshouldbe)valid. (b)Output data-validtime Thetimeintervalinwhichoutputdatacontinestobevalidfollowingachangeofinputconditionsthatcould cause the output data to changeat theendof theinterval. Examplesymbology: ClassifiedUnclassifiedDescription tv(A)tAXQX O u ~ p u tdatavalidtimeafter changeof address. Thissupersedesthe older formtpVX. TEXASINSTRUMENTS INCORPORATED POSTOFFICEBOX225012DALLAS. TEXAS75265 Q) ... ::l ... (,) ::l ... ... en ... Q) Q) ..c: en CO ... CO C -en c o '';:::; c Q) > C o U C) c 'E ~ -> ... CO en en o (9 3-7 C') 5" (I) (I) Q) ... -< '::i 3' 5' co n o :::J c:: CD :::J r+ 0' :::J (I) C Q) r+ Q) en :r CD CD r+ en r+ ... E: (') r+ E: ... CD 3-8 GLOSSARY/TIMINGCONVENTIONS/DATASHEETSTRUCTURE PART111- TIMINGDIAGRAMSCONVENTIONS MEANING TIMINGDIAGRAM SYMBOL INPUT FORCINGFUNCTIONS Must besteadyhighorlow High-to-Iowchanges permitted Low-to-highchanges permitted Don't Care (Doesnot apply) PARTIV-BASIC DATA SHEETSTRUCTURE OUTPUT RESPONSEFUNCTIONS. Willbesteadyhighorlow Willbechangingfromhigh tolow sometimeduring designatedinterval Willbechangingfromlow tohighsometime during designatedinterval State unknown or changing Centerline representshigh-impedance(off)state . The front page of the data sheet begins with a list of key features such as organization, interface, compatibility, opera-tion (static or dynamic), access and cycle times, technology (Nor P channel,silicon or metal oxide gate), and power. In addition,thetopviewofthedeviceisshownwiththepinoutprovided.Nextageneraldescriptionofthedevice, system interface considerations,andelaboration onother device chracteristicsarepresented.Thenext sectionisan explanation of the device's operation which includes the function of each pin (Le., the relationship between each input (output)anda given type of memory).The functionsbasically involve starting,achieving,andending a given type of memory cycle(e.g.,programming or erasingEPROMs,or readinga memory location). Augmenting the descriptive text thereappears a logic symbol preparedinaccordance with forthcoming IEEEandIEC standardsandexplainedinthesectionof thisbookfollowingthisone.Followingthesymbolisusuallyafunctional block diagram,a flow chart of the basic internal structure of the device showing thesignalpaths for data,addresses, andcontrolsignals,aswellastheinternalarchitecture.Usuallythenextfewpagescontaintheabsolutemaximum ratings(e.g.,voltagesupplies,inputvoltage,andtemperature)applicableovertheoperatingfree-airtemperature range.If the device is used outside of these values, it may be permanently destroyed or at least it would not function as intended.Next,typically,aretherecommendedoperatingconditions(e.g.,supplyvoltages,inputvoltages,and operating temperature). The memory device is guaranteed to work reliably and to meet all data sheet parameters when operatedinaccordwiththerecommendedoperatingconditionsandwithinthespecifiedtiming.Ifthedeviceis operated outside of these limits (minimum/maximum), the device's operation is no longer guaranteed to meet the data sheetparameters.Operationbeyondtheabsolutemaximumratingsasjustdescribedcanresultincatastrophic failures. Thenextsectionprovidesatableof electrical characteristics over full rangesof recommended operating conditions (e.g.,inputandoutputcurrents,outputvoltages,etc.).Thesearepresentedasminimum,typical,andmaximum values.Typical values are representative of operation at an ambient temperature of T A=25C with all power supply voltages at nominal value.Next, input and output capacitances are presented.Eachpin has a capacitance (whether an input, an output, or control pin).Minimum capacitances are not given, as the typical and maximum values are the most crucial. Thenext few tablesinvolve thedevice timing characteristics.Theparametersarepresentedasminimum, typical(or nominal),andmaximum.Thetimingrequirementsover recommendedsupplyvoltagerangeand operatingfree-air temperatureindicatethedevicecontrolrequirements 'suchasholdtimes,setup times,andtransitiontimes.These valuesarereferencedtotherelativepositioningofsignalsonthetimingdiagrams,whichfollow.Theswitching characteristicsover recommended supplyvoltagerangearedeviceperformancecharacteristicsinherenttodevice TEXASINSTRUMENTS INCORPORATED POSTOFFICEBOX225012DALLAS, TEXAS75265 GLOSSARY/TIMINGCONVENTIONS/DATASHEETSTRUCTURE operation once the inputs are applied. These parameters are guaranteed for the test conditions given. The interrelation-shipofthetimingrequirementstotheswitchingcharacteristicsisillustratedintimingdiagramsforeachtypeof memorycycle(e.g."read,write,program). At the endof a data sheet additional applications information may be provided such ashow to use the device,graphs of electricalcharacteristics,or otherdataonelectrical characteristics. TEXASINSTRUMENTS INCORPORATED POSTOFFICEBOX225012PALLAS, TEXAS 75265 Q) .. :::l .... CJ :::l .. .... en .... Q) Q) .c en C'O .... C'O C -(I) c o '+:; c Q) > C o U C) c 'E i= -> .. C'O (I) (I) o c:5 3-9 C) 0" (I) (I) C) .. '< --of 3' 5' (Q o o ::s < CD ::s .... 0' ::s C/I -o DI .... DI en ::r CD CD .... en .... ... c ~ ... c ... R 3-10 Alphanumeric Index,Tableof Contents,SelectionGuide InterchangeabilityGuide Glossary/TimingConventions/DataSheet Structure DynamicRAMandMemorySupport Devices DynamicRAMModules EPROMDevices ROMDevices Static RAMandMemory Support Devices ApplicationsInformation LogicSvmbols MechanicalData C '< ~ 01 3 c;" :D ):-3: 01 ~ Co 3: CD 3 o -< en c "C "C o ~ C CD < cr CD til ATTENTION These devices contain circuits to protect the inputs and outputs against damage duetohighstaticvoltagesorelectrostatic fields;however,it isadvisedthat precautions be taken to avoid application of any voltage higher than maximum-ratedvoltagestothesehigh-impedancecircuits. Unused inputs must always beconnected to anappropriate logic voltage level, preferablyeithersupplyvoltageor ground. AdditionalinformationconcerningthehandlingofESDsensitivedevicesis availablefromTexasInstrumentsinadocumententitled"Guidelinesfor Handling Electrostatic-Discharge-Sensitive(ESDS)Devicesand Assemblies. " Pleasecontact to obtainthisbrochure. TexasInstruments P.O.Box401560 Dallas,Texas75240 MOS LSI TMS4116 16,384-811DYNAMICRANDOM-ACCESSMEMORY 016,384 X1Organization 10%ToleranceonAllSupplies AllInputsIncludingClocksTTL-Compatible 0UnlatchedThree-StateFullyTTL-Compatible Output 3PerformanceRanges: ACCESSACCESSREAD TIMETIMEOR ROWCOLUMNWRITE ADDRESSADDRESSCYCLE (MAX)(MAX)(MIN) TMS4116-15150 ns100 ns375ns TMS4116-20200ns135 ns375ns TMS4116-25250ns165 ns410 ns 0Page-ModeOperationforFasterAccess Time CommonI/OCapabilitywith"EarlyWrite" Feature 0Low-PowerDissipation - Operating462 mW(Max) - Standby20mW(Max) 01-TCellDesign,N-ChannelSilicon-Gate Technology 16-Pin300-Mil(7.62mm)Package Configuration description READ, MODIFY-WRITEt CYCLE (MIN) 375ns 375ns 515ns OCTOBER1977- REVISEDMAY1982 TMS4116. NLPACKAGE (TOPVIEW) VBBVSS DCAS iNQ RASA6 AOA3 A2A4 AlA5 VDD......... __--'"-VCC PINNOMENCLATURE AO-A6 CAS Addresses ColumnAddressStrobe D Q RAS VBB VCC VDD VSS IN ,DataInput DataOutput RowAddressStrobe -5-V PowerSupply + 5-VPowerSupply + 12-V PowerSupply Ground WriteEnable The TMS4116 series iscomposedof monolithic high-speed dynamic16,384-bit MOS random-access memories organiz-edas16,384one-bitwords,andemployssingle-transistorstoragecellsandN-channelsilicon-gatetechnology. Allinputsandoutputs arecompatiblewith Series74 TTL circuits includingclocks:RowAddressStrobeRAS(or R) and Column Address Strobe CAS (or C).All address lines (AO through A6) and data in (D)are latched onchip to simplify systemdesign.Dataout(Q)isunlatchedtoallowgreatersystemflexibility. Typical power dissipation isless than 350 milliwatts active and6 milliwatts during standby (VCC isnot requireddur-ingstandby operation).Toretaindata,only10 milliwatts averagepower isrequiredwhichincludes the power con-sumedtorefreshthecontentsof thememory. TheTMS4116seriesisofferedina16-pindual-in-lineplastic(NLsuffix)packageandisguaranteedforoperation fromoocto70oe.Packageisdesignedfor insertioninmounting-holerowson300-mil(7.62mm)centers. tTheterm"read-writecycle"issometimesuS,edasanalternativetitleto"read-modify-writecycle". TEXAS INSTRUMENTS Copyright1982 by TexasInstrumentsIncorporated POSTOFFICEBOX225012DALLAS, TEXAS75265 CI) Q) CJ "S; Q) C ... ... o Q. Q. :::l Ul >-... o E Q) ~ "t:J c:: CO ~ ... o E Q) ~ 'C C ca ~ c:t: a: (,) 'E ca c > C 4-3 c < ::l Q) 3 c:;" ::IJ s: Q) ::l Co s: CD 3 o ... < en r:::: 'C 'C o ... r+ c CD < (;' CD (I) 4-4 TMS4116 16,384-8ITDYNAMICRANDOM-ACCESSMEMORY absolutemaximumratingsoveroperatingfree-air temperaturerange(unlessnoted) t Voltageonanypin(seeNote1).............................................-0.5 Vto20 V VoltageonVee,Voo supplieswithrespecttoVss................................-1Vto15V Shortcircuitoutput current........................................................50 mA Power dissipation.................................................................1W Operatingfree-airtemperaturerange............................................ooe to700e Storagetemperaturerange................................................- 65 e to1500e tStresses beyond thoselisted under"Absolute Maximum Ratings"may cause permanent damage to the device.Thisis a stress rating only andfunctional operation of the device at these or any other conditions beyond thoseindicated in the "Recommended Operating Conditions"section of this specification isnot implied.Exposureto absolute-maximum-ratedconditionsforextendedperiodsmayaffact devicereliability. NOTE1:Under absolute maximum ratings,voltage values arewith respect to the most-negative supply voltage,Vee (substrate),unless otherwise noted. Throughouttheremainderof thisdatasheet,voltagevaluesarewith respectto VSS' recommendedoperatingconditions PARAMETERMINNOMMAXUNIT Supplyvoltage,VSS4.5-5-5.5V Supplyvoltage,VCC4.555.5V Supplyvoltage,VOO10.81213.2V Supplyvoltage,VSS0V I AllinputsexceptRAS,CAS,WRITE2.47 High-levelinput voltage,VIH I V RAS,CAS,WRITE2.77 Low-levelinput voltage,VIL(seeNote2)-10O.BV Operatingfree-airtemperature,T A070C NOTE2;The algebraic convention,where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic voltage levels only_ electricalcharacteristicsover fullrangesof recommendedoperatingconditions(unlessotherwisenoted) PARAMETERTESTCONDITIONS VOH High-)eveloutput voltage 10H=-5 mA VOL Low-leveloutputvoltage10L=4.2mA II Input current(leakage) VI=0Vto7V, Allotherpins=0VexceptVBB= 10Output current(leakage) Vo=0to5.5V, CAShigh ISS1 Averageoperatingcurrent ICC1:f:Minimumcycletime 1001 duringreadorwritecycle ISS2 After1memory cycle ICC2 Standbycurrent RASandCAShigh 1002 ISS3 Minimumcycletime ICC3 AveragerefreshcurrentRAScycling, 1003 CAshigh ISS4 Minimumcycletime ICC4:f:Averagepage-modecurrentRASlow, 1004 CAScycling tAlltypicalvaluesareat T A=25Candnominalsupplyvoltages. *VCCisappliedonlyto theoutputbuffer,soICCdependsonoutputloading. Outputloadingtwo standardTTLloads. TEXAS INSTRUMENTS -5 V POSTOFFICE BOX225012DALLAS. TEXAS75265 MIN Typt MAXUNIT 2.4V 0.4V 10pA 10p.A 50200pA 49 mA 2735mA 10100pA 10p.A 0.51.5mA 50200p.A 10p.A 2027mA 50200uA 4 mA 2027mA 1MS4116 16,384-811DYNAMICRANDOM-ACCESSMEMORY capacitanceoverrecommendedsupplyvoltagerangeandoperatingfree-airtemperaturerange,f1MHz PARAMETERTypt MAXUNIT Cj(A)Input capacitance,addressinputs45pF Cj(O)Input capacitance,datainput45pF CHRC) Input capacitance,strobeinputs810pF CHW) Inputcapacitance,writeenableinput810pF CoOutputcapacitance57pF switchingcharacteristicsover recommendedsupplyvoltagerangeandoperatingfree-airtemperaturerange ALT.TMS4116-15 PARAMETERTESTCONDITIONS SYMBOLMINMAX CL= 100 pF, ta(C) AccesstimefromCASLoad= 2Series, tCAC 100 74 TTL gates tRLCL= MAX, ta(R) AccesstimefromRAS CL= 100 pF, Load= 2Series, tRAG 150 74 TTLgates Output disable time CL= 100 pF, tdis(GH) after GAShigh Load= 2Series tOFF a40 74 TTLgates tAlltypicalvaluesareatT A=25Candnominalsupplyvoltages. .. ,'TEXAS INSTRUMENTS POSTOFFICE BOX225012DALLAS. TEXAS75265 TMS4116-20TMS4116-25 UNIT MINMAXMINMAX 135165ns 200250ns a50a60ns CI) Q) (.) ':; Q) C .... ... o c. C. ::J tJ) >-... o E Q) ~ "'0 C CO ~ ~ a: (.) 'E CO c >-C 4-5 o -< :;, C 3 c:;. :ll > 3: C ::l 0-3: CD 3 o ... -< t/) C "C "C o ~ o CD < c:;. CD en 4-6 TMS4116 16,384BITDYNAMICRANDOMACCESSMEMORY timingrequirementsoverrecommendedsupplyvoltagerangeandoperatingfree-airtemperaturerange ALT.TMS4116-15TMS4116-20TMS4116-25 PARAMETER SYMBOLMINMAXMIN UNIT MAXMINMAX tC(PI Page-modecycletimetpc170225275ns tc(rd) Readcycletime tRC 375375410ns tc(WI Writecycletime twc 375375410ns tc(rdW) Read,modify-writecycletime tRWC 375375515ns tw{CHl Pulsewidth,CAShigh(prechargetime)tcp6080100ns tw(CL) Pulsewidth,CASlow tCAS 10010,00013510,00016510,000ns tw(RHI PulsewidthRAShigh(prechargetime)tRP100120150ns twIRL) Pulsewidth,~low tRAS 15010,00020010,00025010,000ns tw(W) Writepulsewidthtwp455575ns Transitiontimes(riseandfall)for 335350350tt RASandCAS tTns tsu(CA) Columnaddresssetuptime tASC -10-10-10ns tsu(RA) Rowaddresssetup time tASR 000ns tsu(D) Datasetuptime tDS 000ns tsu(rd) Readcommandsetuptime tRCS 000ns tsu(WCH) Writecommandsetuptime tCWL 6080100 beforeCAShigh ns tsu(WRH) Writecommandsetuptime tRWL 6080100ns beforeRAShigh Columnaddressholdtime th(CLCA) afterCASlow tCAH 455575ns th(RA) Rowaddressholdtime tRAH 202535ns Columnaddressholdtime th(RLCA) after ~low tAR 95120160ns th(CLD) DataholdtimeafterCASlow tDH 455575ns th(RLD) DataholdtimeafterRASlow tDHR 95120160ns th(WLD) Dataholdtimeafter Wlow tDH 455575ns thIrd) Readcommandholdtime tRCH 000ns Writecommandholdtime th(CLW) after CASlow tWCH 455575ns Writecommandholdtime th(RLW) afterRASlow tWCR 95120160ns tRLCH Delaytime,RASlow toCAShigh tCSH 150200250ns tCHRL Delaytime,CAShightoRASlow tCRP -20-20-20ns tCLRH Delaytime,CASlow toRAShigh tRSH 100135165ns tCLWL Delaytime,CASlowtoWlow tCWD 7095125 (read,modify-write-cycleonly) ns Delaytime,mlow toCASlow tRLCL (maximumvaluespecifiedonly tRCD 205025653585ns to guaranteeaccesstime) tRLWL Delaytime,RASlow to W low tRWD 120160200 (read,modify-write-cycleonly) ns tWLCL Delaytime,Wlow to CASlow twcs -20-20-20 (earlywritecycle) ns trf Refreshtimeinterval tREF 222ms .TEXAS" INSTRUMENTS POSTOFFICE BOX225012DALLAS, TEXAS 75265 readcycletiming ADDRESSES DO TMS4116 16.38481TDYNAMICRANDOMACCESSMEMORY rtc(rd) ::: -it'wIRLI${\-__ _ II I j4-tRLCL TtW(CL)---ir-tCHRL----i IfiRLC"lL VIL---1I4t tsu(RA)! Ij..---tW(CHI---.j II th(RAI --tJ4-r- III II--tj4f-tsU(CA)I _____ IIII VOL II \.--.I- th(CLCA) II ..TEXAS INSTRUMENTS I-ro0O(o{T$A:O I . tdis(CH)VALIDPOSTOFFICE BOX225012DALLAS. TEXAS75265 U) Q) CJ 'S: Q) c t: o c. C. ::J en > ... o E Q) "C C ca a: CJ 'E ca c > C 4-7 c < ::l D) 3 Ci' :xl l> s: Q) ::l c.. s: a> 3 o ... < en I: "C "C o ... ... C a> < Ci' a> fI) 4-8 1MS4116 16,384811DYNAMICRANDOMACCESSMEMORY earlywritecycletiming ADDRESSES 01 DO VOH VOL ----------HI-Z-----------TEXAS INSTRUMENTS POSTOFFICEBOX225012DALLAS, TEXAS75265 writecycletiming ADDRESSES DI DO TMS4116 16,384811DYNAMICRANDOMACCESSMEMORY tThe enable time (ten)for a write cycle is equal in duration to the access time from CAS (ta(C)) in a read cycle;but the active levels at the output are invalid. TEXAS INSTRUMENTS POSTOFFICEaox 225012DALLAS. TEXAS75265 en Q) (J 'S; Q) C .... ... o Q. Q. ~ rJ) > ... o E Q) ~ "C C a:1 ~ 0: (J 'E a:1 c > C 4-9 c < :::l Q) 3 cr jJ s: Q) :::l Co s: CD 3 o ... < en c "C "C o ... r+ c CD < 0' CD en TMS4116 16,3848ITDYNAMICRANDOMACCESSMEMORY readwrite/read-modify-writecycletiming

:: jtt----,----tW(RLl-------... 'I...j4----tCLRH\.twIRHIJ \4--tRLCL--..+....----twICLI--------:..1 '*-tCHRL--.fI . Ir"}t- tRLeH;J 5th(RLCAIII Cth(RAII Hth(CLCAIIII --.I II ADDRESSES 01 II VOH II -.....:.i----H1-Z : __DO VOL

......... .'.. 4-10 ".TEXAs INSTRUMENTS POSTOFFICE BOX225012DALLAS, TEXAS 75265 RAS CAS z Ii ADDRESSES w DO ! ..... 'C III CO(I) :3 o Co V'H 'wlRL>,*"*. i VIL- 5J=( L_i"-r tRLCH--II;. Irtc(P).14-tCLRH ---.I I I.-'RLCL 1-1t-----I 'w'CHIIr-'CHRL --Ioil V'HIII r-tr-'WICL>-: f-f V"IIjjl- .fjItfl th(RA) I-- I th(CLCA)1I th(CLCA)II Mth(CLCA)I I rIIII I -+j!J-tSU(CAlI II VI. .............................. IIIII IIIII I.I I II 1""""11+- 'h",,-JI--II'h",,-Jt-- --I jI+-'h'," vN3IW 7;1' II I I i I htdis(CHlItdis(CH)I!.-.f tdis(CH) 8>---DynamicRAMandMemorySupportDevices .... :n co .;:. m =i c < :2 :z:a 3: n = :z:a :2 c o 3: :i:-n n m en en 3: .... m3: 3: en o=: =- o TMS4116 16,38481TDYNAMICRANDOMACCESSMEMORY CYCLERATE(&TIME)VSTEMPERATURE Q. E GI I-70 60 GI at I 50

o tc(rd)- CycleTime- ns 375 1000500400,300 TA (MAX) 23 103/tc(rd)- CycleRate- MHz 250 4 CYCLERATE(&TIME)VSMAX SUPPLY CURRENT.1003 tc(rd)- CycleTIme- ns SOmA 1000500400300250 c:t E 40mA ::s 30mA () > C. Q. ::s (/j I 20mA X c:t ::E ",""

I" M10mA C .9 o o 234 103/tc(rdl- CycleRate- MHz c:t E f :; () > C. Q. ::s (/j I X c:t 0 .9 c:t E !! :; () > C. Q. ::s (/j X c:t ::E Of C .9 CYCLERATE(&TIME)VSMAX SUPPLY CURRENT.1001 50mA 40mA 30mA 20mA 10mA o o tc(rd)- CycleTime- ns 375 10005 00400300

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--C This document contalnalnfonnation on a product unde, development. Texallnstrumentl reserve. the right to changeordiscontinuethisproductwithoutnotice. TEXAS INSTRUMENTS 4-15 POSTOFFICEBOX225012DALLAS, TEXAS75265 TMS4161 65.53681TMULTIPORTMEMORY two, three,or four 64-bit shift registers can besequentially readout depending on a two-bit code applied to the two most significant column address inputs. The TMS4161employs state-of-the-art SMOS (Scaled-MOS) N-channel dou-blelevelpolysilicongatetechnologyforveryhighperformancecombinedwithlow cost andimprovedreliability. The TMS4161features full asynchronous dual access capability except when transferring data between the shift register andthememoryarray. Refresh period is extended to 4milliseconds, andduring this period each of the 256 rows must bestrobed with RAS inorder to retaindata.CAScanremainhighduring the refreshseql!ence to conservepower.Note that the transfer of a rowof datafromthememoryarraytotheshift registeralsorefreshesthatrow. Allinputs andoutputs,including clocks,are compatible with Series74 TTL.All address lines anddata-in arelatched onchiptosimplifysystemdesign.Data-outisunlatchedtoallowgreatersystemflexibility. The TMS4161isoffered ina 20-pin dual-in-line-plastic packageandis guaranteedfor operationfromOOCto 70C. Packagesaredesignedforinsertioninmounting-holerowson300-mil(7,62mm)centers. randomaccessaddressspacetosequentialaddressspacemapping The TMS4161is designed with each row divided into four, 64-column sections. The first column section to be shifted out is selectedby the two most significant column address bits.If the two bits represent binary 00, then one to four Cregisters can be shifted out in order.If the two bits represent binary 01, then only 1 to 3 (the most significant) registers ~canbeshiftedoutinorder.If thetwo bitsrepresent10,thenonetotwoof themost significantregisters 'canbe mshifted out inorder.Finally, if the two bits represent 11only the most significant register can beshifted out. All registers 3areshifted out with the least significant bit (bit 0)first andthemost significant bit (bit 63)last.Note that if the two n'column addressbits equal00 during the last register transfer cycle(TRInE equalto 0)a total of 256 bits canbese-::aquentiallyreadout. l> ~ Q) :s Q. ~ CI) 3 o .. -< tn c: "0 "0 o .. ... 4-16 TEXAS INSTRUMENTS POSTOFFICEBOX225012DALLAS, TeXAS75265 functionalblock diagram D I I COL 0 ,-- - -ROW 0 256 OWS 1_ ROW 255 - - -COL SCLK SIN A6 A7 SOE randomaccessoperation TR/QE 0 I REG I 00 I t 256COLUMNS (4GROUPSOF64 COLUMNS) 1 -f DQ MEMORYARRAY f 256COLUMNS - SHIFTREGISTERS--REG I REG 0110 I COL ~ COL !64128 I I I COL 192 TMS4161 65,536-811MULTIPORTMEMORY I Q ~ ~ iI 65.535 SIN REG r--11 + COL 255 64 BITS 128 BITS1OF4 K>--REGISTER 192 BITS DECODER 256 BITS SOUT +t TheTA/DEpinhastwo functions.First,it selects eitherregister transfer orrandom-accessoperationasRASfalls, andsecond,if thisisarandom-accessoperation,it functionsasanoutputenableafterCASfalls. To use the TMS4161in the random-access mode, TR/Of must behigh asRASfalls.Holding TR/QE high disconnects the256elementsof theshift registersfromthecorresponding256bitlinesof thememoryarray.If dataistobe shifted, the shift registers must be disconnected from the bit lines. Holding TR/QE low enables the 256 switches that connect the shift registers to the bit lines and indicates that a transfer will occur between the shift registersal\d one of thememoryrows.-OnceCAShasbeenpulledlow,TR/QEcontrolswhen thedatawillappearattheQoutput(ifthisisa readcycle). Whenever TR/QEisheld high, the Q output will bein the high-impedance state. This feature removes the possibility fI) (1) CJ "S; (1) C ... ... 0 0. 0. ::::J en > ... 0 E (1) :; '"C C CO :; ... o E Q) ~ "C c:: CO ~ a: (J 's CO c:: > C TEXAS INSTRUMENTS 4-19 POSTOFFICEBOX225012DALLAS. TeXAS75265 c -< j m 3 o :::c l> s: m j c. s: (t) 3 o .. -< tn c "0 "0 o .. .... c (t) < O (t) rn TMS4161 65,53681TMUL TIPORTMEMORY recommendedoperatingconditions PARAMETERMINNOMMAXUNIT Supplyvoltage,VOO4.555.5V Supplyvoltage,VSS0V High-levelinput voltage,VIH2.4VOO+0.3V Low-levelinput voltage,VIL(seeNote2)-10.8V Operatingfree-airtemperature,T A070C NOTE2:The algebraic convention,where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic voltage levels only. electricalcharacteristicsoverfullrangeof recommendedoperatingconditions(unlessotherwisenoted) TESTTMS4161-15TMS4161-20 PARAMETER TyptTypt UNIT CONDITIONSMINMAXMINMAX VOH High-leveloutput 10H= voltage(Q,SOUT) -5 mA2.42.4V VOL Low-leveloutput 10L=4.2mA voltage(Q,SOUT) 0.40.4V VI=0Vto5.8V, II Input current(leakage)VOO=5V,1010p.A Allotherpins=0V 10 Output current(leakage) Vo=0.4Vto5.5V, 1010p.A VOO=5V tc(rd)=minimumcycletime, 1001 AverageoperatingcurrentTAtGElowafterRASfalls, t 35503045mA duringreadorwritecycleSCLKandSINlow, SOEhigh After1- RAScycle, RASandCAShigh, 1002StandbycurrentSCLKlow,81068mA SINlow, SOEhigh tc(rd)=minimumcycletime, CAShigh, 1003 Averagerefreshcurrent SCLKlow, 30 SINlow, 402535mA SOEhigh, TRtQEhigh tc(P)=minimumcycletime, RASlow, 1004 Averagepage-modecurrent CAScycling, 30402032mA TAtGElowafterRASfalls, t SCLKandSINlow, SOEhigh Averageshiftregister RAShigh, 100511CAShigh,16271525mA current(includes1002) tc(SCLK)= 100 ns NOTE:1001thru1005 assumenoloadona andSOUToAdditionalinformationontheseparametersonlastpage. tAlltypicalvaluesareatT A=25Candnominalsupplyvoltages. tSeeappropriatetimingdiagram. VIL>-0.6 V. ISeepower versuscycletimederatingcurveonlastpage. 4-20 TEXAS INSTRUMENlS POSTOFFICEBOX225012DALLAS. TEXAS75265 TMS4161 65,536-0ITMULTIPORTMEMORY capacitanceoverrecommendedsupplyvoltageandoperatingfree-airtemperaturerange,f1 MHz PARAMETER Typt MAXUNIT Ci(A) Input capacitance,addressinputs45pF Ci(D)Inputcapacitance,datainput45pF CURCI Inputcapacitance,strobeinputs810pF Ci(W) Inputcapacitance,writeenableinput810pF Ci(CK) Inputcapacitance,serialclock810pF Ci(SI) Inputcapacitance,serialin45pF Ci(SOE) Inputcapacitance,serialoutput enable45pF Ci(TR) Input capacitance,registertransferinput45pF Co(O) Output capacitance,random-accessdata57pF Co(SOUT) Output capacitance,serialout57pF tAlltypicalvaluesareatT A=25Candnominalsupplyvoltages. switchingcharacteristicsoverrecommendedsupplyvoltagerangeandoperatingfree-airtemperaturerange (seefigure1) PARAMETERTESTCONDITIONS ALT.TMS4161-15TMS4161-20 SYMBOLMINMAXMINMAX UNIT ta(C) AccesstimefromCASCL=100 pF tCAC 100135 Accesstimeofa from ta(GE) TR/DElow CL=100 pF4040 ta(R) AccesstimefromRAS tRLCL= MAX, CL=100 pF tRAC 150200 SOUTaccesstimefrom ta(RSO) RAShigh CL=50pF6060 AccesstimefromSOE ta(SOE; low toSOUT CL=50pF2025ns ta(SOI AccesstimefromSCLKCL=50pF3030 tdis(CH)+ a output disabletime 2025 fromCAShigh tOFF tdis(OE)+ Qoutput disabletime 2025 from 'fA/DEhigh tdis(SOE)+ Serialoutput disabletime 2025 fromSOEhigh tThemaximum values for tdis(CH).tdis(QE).andtdis(SOE)define the timeatwhich theoutput achieves theopencircuitconditionandarenot referenced toVOHorVOL. en Q) CJ 'S: Q) c ... ... o c. c. ::::s tJ) >-... o E Q) ~ 'C c: ca ~ -----I ,-,--talCI talRI-I l'RiilE D o fA Q) Co) S Q) c > ... o E Q) :liE ""C &: CO :liE oCt a: Co) 'E CO &: > C TEXAS INSTRUMENTS 4-27 POSTOFFICEBOX225012DALLAS, TEXAS 75265 +>-N (Xl 0_ :;;z ;;c

x U1 '" enU1sao!l\aa A.lowall\lpueII\I"HO!weuAO _I ItwIRL)1 RAS:,:[\ISJf I ItRLCH.,tw(RH)r--t -.It.- ,.te(P):1r--tCLRHttIItw(CH)I.tCHRL---I Ii.-tRLCL--=-ttt-.lI 1 CAS:,:! iit,wICLJ1ht,wICLJrth(RA).,....,I th(CLCA)I, I'I III III ,..-I th(CLCA),j.....*th(CLCA)II tsu(RA) IrstsU(CA)I-.f r;-tSU(CA)ItSU(CA,)--t r;- III AD.A7ROWDON'T CAREth(TR),-.,1I III ,,"ITA'"1 '7:I II r-'CLOEHtt! Tnla.tI\ \\\\ISIIl !w--\. 'III IIIIIII ,I,!I II,I.....,I,:th(RHrd) ....}th(CHrd).-I14- II--.lr-th(CHrd)IIII th(CHrd) Itsu(rd).f4- -I,=--Itsu(rd)Itsu(rd)I WV'H ;;V :..: 'caEjh=i;t:.J=IIVIL______IIrV'I I1----1I-----tr-ta(OE),II !.-ta(C)....I..... ta(C)-.iIt--ta(C)--t1..f I.ta(R).1,- .1tdis(CH)I-1j.-tdis(CH)IrtdiS(OE) IIIItdis(CH),.. Q:::?VALIDVALID }H. VALID}-NOTE:Timingisfor non-multiplexed0,Q,andAddresslines. 'C en-.of 01!-"'3:CC U'Ien :3 c..,)';;" 0 en_ C-oen 5!-m -.of 013:C-nc: -C 4-31 C '< :J Q) 3 c;" jJ > s: Q) :J Q. s: (I) 3 o .. '< en c "C "C o .. r+ c CD < C;O (I) C/I TMS4161 65,53681TMULTIPORTMEMORY shiftregistertomemorytiming AO-A7 o:,: 0OOOT III VIHII1

VIL .,I--I tCKRL-1j-tWCKHI'I.,__,tWCKL :,:;r\\\\\\\\SS\\\S>\\\\\\if j.talsOI,l-- thIRSOI---ftaIRSOI--tlI..--.., II Q SCLK SOUT vOL ___--'__RE_G_D_A_TA__..,DATANOTVALID NOTES:1.Theshift register to memory cycleisused to transfer datafromtheshiftregister to thememory array.Everyone of the256 locations in the shift register iswritten into the256 columns of the selectedrOw.Notethat thedatathatwasin the shift register may have resulted.either fromaserialshiftinor fromaparallelloadof theshiftregisterfromoneof thememoryarrayrows. 2.SOEassumedlow. 3.SCLKmaybehighorlowduringtwIRL)' 4-32 TEXAS INSTRUMENlS POST OFFICEBOX225012DALLAS, TEXAS75265 TMS4161 65.536-BITMUL TIPORTMEMORY memorytoshiftregistertiming twiRL)i :,:------::lII.it-'RLCL----1}1 IrtRLCH.1 I Ix-'w'cu-}tltm,ll! :! !J-LItSUIRWI-:ItsuIRWI-{L!...LII I tll-thlRWIII-1l-thlRWII/II JOON !I tzX)(ofrfc6 C TEXAS INSTRUMENTS 4-37 POSTOFFICEBOX225012DALLAS. TEXAS 75265 o m < c;' m en 4-38 :4 MOS LSI TMS4164,SMJ4164 65,536-8ITDYNAMICRANDOM-ACCESSMEMORY 65,536X1Organization Single+5-V Supply(10%Tolerance) JEDECStandardizedPin-OutinDual-In-Line Packages Upward PinCompatiblewith TMS4116 (16KDynamic .RAM) FirstMilitaryVersionof64K DRAM AvailableTemperatureRanges: M...- 55C to125C S... - 55C to100C E ... -40C to 85C L... OOCto 70C LongRefreshPeriod...4milliseconds LowRefreshOverheadTime... AsLowAs 1.8%of TotalRefreshPeriod AllInputs,Outputs,ClocksFullyTTL Compatible 3-State UnlatchedOutput CommonI/OCapabilitywith"EarlyWrite" Feature Page-ModeOperationforFaster Access LowPower Dissipation Operating... 125 mW(TVP) Standby... 17.5 mW (TVP) PerformanceRanges(S,E,L Temperature Ranges): ACCESSACCESS TIMETIME ROWCOLUMN ADDRESSADDRESS (MAX)(MAX) '4164-12120 ns70ns '4164-15150 ns85ns '4164-20200 ns135 ns New SMOS(Scaled-MOS)N-Channel Technology description READ OR WRITE CYCLE (MIN) 230ns 260 ns 326ns The'4164isahigh-speed,65,536-bit,dynamic random-access memory, organized as 65,536 words ofonebiteach.Itemploysstate-of-the-artSMOS (scaledMOS)N-channel double-level polysilicon gate technology for very high performance combined with low costandimprovedreliability. ADVANCEINFORMATION MILITARYPRODUCTS(SMJ)ONLY JULY1980- REVISEDOCTOBER1983 TMS4164 . NLPACKAGE SMJ4164 . JD PACKAGE (TOPVIEW) NC[1V16VSS D215CAS W314Q RAS413A6 AO12A3 A211A4 A1 VDD 10A5 9A7 TMS4164 FPLPACKAGE (TOPVIEW) SMJ4164 . FGPACKAGE (TOPVIEW) mlm um u 211817211817 IN3016QIN3A16Q RAS4 NC5 AO6 A27 READ-MODIFY-WRITE CYCLE (MIN) 260ns 285ns 345ns 15A6RAS4 14NCNC5 13A3AO6 12A4A27 891011 A A ~ g < C" ll'l C~ < CI"- ll'l C-0.6 V. TMS4164-12TMS4164-15 TYptTVpt UNIT MINMAXMINMAX 2.42.4V 0.40.4V 1010/LA 1010/LA 40483545mA 3.553.55mA 28402537mA 28402537mA ... .. o ~ ~ ::::J CJ) >-.. o E Q) ~ "'C r::::: CO ~ ~ a: (J -e CO r::::: >-C TEXAS INSTRUMENTS 4-43 POSTOFFICE BOX225012DALLAS. TEXAS 75265 TMS4164 65,536BITDYNAMICRANDOMACCESSMEMORY electricalchara,cteristicsover fullrangesof recommendedoperatingconditions(unlessotherwisenoted) PARAMETER TEST CONDITIONS VOH High-leveloutputvoltage IOH= -5 mA VOLLow-leveloutputvoltageIOL=4.2mA II Input current(leakage) VI= 0Vto5.8V.VOO=5V Allotherpins= 0V Vo= 0.4 to5.5V. 10 Output current(leakage)VOO=5V. CAShigh 1001 ~ Averageoperatingcurrent tc=minimumcycle duringreadorwritecycle 1002Standbycurrent After1memory cycle. RASandCAShigh tc=minimumcycle. 1 0 0 3 ~AveragerefreshcurrentRASlow. CAShigh tc(P)=minimumcycle. 1004 Averagepage-modecurrentRASlow. CAScycling tAlltypicalvaluesareatT A=25C andnominalsupplyvoltages. tAdditionalinformationonlastpage. VIL>,-0.6 V. TMS4164-20 MINTyptMAX 2.4 0.4 10 \ 10 2737 3.55 2032 2032 capacitanceoverrecommendedsupplyvoltagerangeandoperatingfree-air temperaturerange,f D) ::::J a. s: en 3 o .., -< CJ) C CHAt Ci(O) CHRC) CHW) Co PARAMETER Inputcapacitance.addressinputs Inputcapacitance.datainput Inputcapacitancestrobeinputs Inputcapacitance.writeenableinput Outputcapacitance 'CtAlltypicalvaluesareat T A=25Candnominalsupplyvoltages. TMS4164 TypT MAX 47 47 810 810 58 UNIT V V p.A p.A mA mA mA mA 1MHz UNIT pF pF pF pF pF 'C o ~switchingcharacteristicsover recommendedsupplyvoltagerangeandoperatingfree-airtemperaturerange C en < n en (J) 4-44 I ta(C) ta(R) tdis(CH) PARAMETER AccesstimefromCAS AccesstimefromRAS Output disable time afterCAShigh TESTCONDITIONS CL=100 pF. Load=2Series74 TTLgates tRLCL=MAX. Load=2Series74TTLgates CL=100 pF. Load=2Series74 TTLgates TEXAS INSTRUMENTS ALT. SYMBOL tCAC tRAC tOFF POSTOFFICE BOX225012DALLAS, TEXAS75265 TMS4164-12TMS4164-15 UNIT MINMAXMINMAX 7085ns 120150ns 040040ns 1: TMS4164 65,536811DYNAMICRANDOMACCESSMEMORY switchingcharacteristicsover recommendedsupply voltagerangeandoperatingfree-airtemperaturerange PARAMETERTESTCONDITIONS ALT. SYMBOL TMS4164-20 MINMAX UNIT talC) AccesstimefromCAS CL=100 pF Load=2Series74 TTL gates tCAC 135ns ta(R)AccesstimefromRAS tRLCL=MAX. Load=2Series74 TTL gates tRAC 200ns tdis(CH) Outputdisable timeCL=100 pF. afterCAShighLoad=2Series74 TTL gates tOFF 050ns en (1) (J "S (1) c ..... ... o c. C. ::l (I'J > ... o E (1) ~ "'C C CO ~ a: (J "E CO c > C TEXAS INSTRUMENTS 4-45 POSTOFFICEBOX225012DALLAS. TEXAS75265 Q) :::s Co ~ CD 3 o ... -< en c: "C "C o ... r+ c CD c:: (i' CD I/) 1MS4164 65.536811DYNAMICRANDOMACCESSMEMORY timingrequirementsover recommendedsupplyvoltagerangeandoperatingfree-air temperatureranqe ALT.TMS4164-12TMS4164-15 PARAMETERUNIT SYMBOLMINMAXMINMAX tc(P) Pagemodecycle timetpc130160ns tc(rd) Readcycletime t tRC 230260ns tclWi Writecycle time twc 230260ns tc(rdW) Read-write/read-modify-writecycle time tRWC 260285ns tw(CH) Pulsewidth,CAShigh(prechargetime); tcp5050ns tw(Cl) Pulsewidth,CASlow 9 tCAS 7010,0008510,000ns tw(RH)Pulsewidth,RAShigh(prechargetime)tRP80100ns twIRL) Pulsewidth,RASlow' tRAS 12010,00015010,000ns tw.iWl Writepulsewidthtwp4045ns tt Transitiontimes(riseandfall)for RASandCAS tT 350350ns tsu(CA) Columnaddresssetuptime tASC -5-5ns tsu(RA) Rowaddresssetup time tASR 00ns tsu(D) Datasetuptime tDS 00ns tsu(rd)' Readcommandsetuptime tRCS 00ns tsu(WCH) . Writecommandsetup time beforeCAShigh tCWL 5050ns tsu(WRH) Writecommandsetup time beforeRAShigh tRWL 5050ns th(CLCA) Columnaddressholdtimeafter CASlow tCAH 4045ns th(RA)RowaddressholdtimetRAH1520ns th(RLCA) ColumnaddressholdtimeafterRASlow tAR 8595ns th(CLD) Dataholdtimeafter CASlow tDH 4045ns th(RLDI Dataholdtimeafter RASlow tDHR 8595ns th(WLD) Dataholdtimeafter Wlow tDH4045ns th(CHrd) Readcommandholdtimeafter CAShigh tRCH 00ns th(RHrd) ReadcommandholdtimeafterRAShigh tRRH 55ns th(CLW) Writecommandholdtimeafter CASlow tWCH 4045ns th(RLW) WritecommandholdtimeafterRASlow tWCR 8595ns tRLCH Delay time,RASlow toCAShigh tCSH 120150ns tCHRL Delaytime,CAShightoRASlow tCRP 00ns tCLRHDelaytime,CASlowtoRAShightRSH60100ns tCLWL Delaytime,CASlow to Wlow tCWD 4060ns (read-modify-writecycleonly) Delay time,RASlow toCASlow tRLCL (maximumvaluespecifiedonly tRCD 15502065ns toguaranteeaccesstime) tRLWL Delay time,RASlowto Wlow tRWD (read-modify-writecycleonly) 85. 100ns tWLCL Delaytime,Wlow toCAS twcs low(earlywrite cycle) -5-5ns trf Refreshtimeinterval tREF 44ms NOTE:Timingmeasurements aremade at the10% and 90%pointsof input andclock transitions.Inaddition,VILmax and VIHmin must bemet at the 10%and90%points. tAllcycletimes assume tt=5ns. *Pagemodeonly. In a read-modify-write cycle, tCLWL and tsu(WCH)must be observed.Depending onthe user's transition times,this may requireadditional CASlow time (tw(CL))'Thisapplies topagemoderead-modify-writealso._ ,Ina read-modify-write cycle, tRLWL and tsu(WRH)must beobserved.Depending onthe user's transition times,this may requireadditional RASlow time (tw(RL))' 4-46 TEXAS INSTRUMENTS 'POSTOFFICE BOX225012DALLAS. TEXAS 752.65 TMS4164 65,536-811DYNAMICRANDOM-ACCESSMEMORY timingrequirementsover recommendedsupplyvoltagerangeandoperatingfree-airtemperature range ALT.TMS4164-20 PARAMETERUNIT SYMBOLMINMAX tc(P) Pagemodecycletimetpc206ns tc(rd) Readcycletime 1 tRC 326ns tc(W) Writecycletime twc 326ns tc(rdW) Read-write/read-modify-writecycletime tRWC 345ns tw{CH) Pulsewidth,CAShigh(prechargetime)t tcp80ns tw(CLlPulsewidth,CASlow9 tCAS13510,000ns tw(RH) Pulsewidth, RAShigh(prechargetime) tRP 120ns twIRL) Pulsewidth,RASlow' tRAS 20010,000ns tw(W) Writepulsewidthtwp55ns ttTransitiontimes(riseandfall)forRASandCAS tT350ns tsu(CA) ColumnaddresBs;etuptime tASC -5 tsu(RA) Rowaddresssetuptime tASR 0ns tsu(D) Datasetup time tDS ans tsu(rd) Readcommandsetuptime tRCS 0ns tsu(WCH) WritecommandsetuptimebeforeCAShigh tCWL 60ns tsu(WRH) Writecommandsetup timebeforeRAShigh tRWL 60ns th(CLCA)Columnaddressholdtimeafter CASlowtCAH55ns th(RA) Rowaddressholdtime tRAH 25ns th(RLCA) ColumnaddressholdtimeafterRASlow tAR 120ns th(CLD) Dataholdtimeafter CASlow tDH 55ns th(RLD) DataholdtimeafterRASlow tDHR 145ns th(WLD) Dataholdtimeafter Wlow tDH 55ns th(CHrdl ReadcommandholdtimeafterCAShigh tRCH 0ns th(RHrd) ReadcommandholdtimeafterRAShigh tRRH 5ns th(CLW) Writecommandholdtimeafter CASlow tWCH 55ns th(RLWI WritecommandholdtimeafterRASlow tWCR 145ns tRLCH Delaytime,RASlow to CAShigh tCSH 200ns tCHRLDelaytime,CAShigh ,toRASlowtCRP0ns tCLRH Delaytime,CASlow toRAShigh tRSH' 135ns tCLWL Delaytime,CASlow to Wlow tCWD 65ns (read-modify-writecycleonly) Delaytime,RASlow toCASiow tRLCL (maximumvaluespecifiedonly tRCD 2565ns to guaranteeaccesstime) tRLWL Delaytime,RASlow to Wlow tRWD 130 (read-modify-writecycleonly) ns tWLCL Delaytime,Wlow to CAS twcs -5 low (earlywrite cycle) ns trfRefreshtimeintervaltREF4ms NOTE:Timing measurements aremadeat the10% and90%pointsof input andclock transitions.Inaddition,Vil max andVIHminmustbemet at the 10%and90%points. tAllcycletimes assumett=5ns. *Pagemodeonly. In a read-modify-write cycle,tClWl andtsu(WCHImust beobserved.Dependingon the user's transition times.this may requireadditionalCAS low time (tw(Clll.Thisapplies to pagemoderead-modify-writealso. ,In a read-modify-write cycle.tRlWl andtsu(WRHImust beobserved.Depending onthe user's transition times,this may requireadditionalRASlow time (tw(Rlll. ... ... o c. C. :l (J) >-... o E Q) ~ "C t: CO ~ ~ a: CJ -E CO t: >-C TEXAS INSTRUMENTS 4-47 POSTOFFICE BOX225012DALLAS. TEXAS 75265 SMJ4164 65.536811DYNAMICRANDOMACCESSMEMORY recommendedoperatingconditions SMJ4164 PARAMETERMVERSIONS VERSIONEVERSIONUNIT MINNOMMAXMINNOMMAXMINNOMMAX Supply voltage,VOO4.555.54.555.54.555.5V Supplyvoltage,VSS000 High-levelinput voltage,VIH 2.4 VCC+0.32.4VCC+0.32.4VCC+0.3V Low-levelinput voltage,VIL-0.60.8-0.60.8-0.60.8V (seeNotes2and3) Operatingcase -55125-55100-4085 DC temperature,T C NOTES:2.Thealgebraic convention.where the morenegative(less positive I limit is designatedasminimum. isusedinthis datasheetfor logic voltage levelsonly. 3.Duetqinputprotectioncircuitry.theappliedvoltagemaybegintoclampat-0.6 V.Testconditionsshouldcomprehend this occurrence. C '-0.6 V. 4-48 TEXAS INSTRUMENTS SMJ4164-15 MVERSION MIN Typt MAX 2.4 0.4 10 10 48 7 40 40 POSTOFFICEBOX225012DALLAS. TEXAS 75265 SMJ4164-20 MVERSIONUNIT MIN TYpt MAX 2.4V 0.4V 10p.A 10p.A 45rnA 7rnA 37rnA 37rnA SMJ4164 65,536-011DYNAMICRANDOM-ACCESSMEMORY electricalcharacteristicsoverfullrangesof recommendedoperatingconditions(unlessotherwisenoted) TEST PARAMETER CONDITIONS VOH High-leveloutput voltage10H=-5 mA VOL Low-leveloutput voltage10L=4.2 mA II Inputcurrent(leakage) VI=OVto5.8V,VOO=4.5V to5.5V,outputopen Vo=0Vto5.5V, 10Output current(leakage)VOO=5V, CAShigh 1001f Averageoperatingcurrent tc=minimum cycle duringreadorwritecycle 1002Standbycurrent After1memorycycle, RASandCAShigh tc=minimumcycle, 1003f AveragerefreshcurrentRASlow, CAShigh tc(P)=minimumcycle, 1004 Averagepage-modecurrentRASlow, CAScycling tAlltypicalvaluesareat TC=25 DCandnominalsupplyvoltages. tAdditionalinformationonlastpage. VIL>-0.6 V. SMJ4164-12SMJ4164-15 S,EVERSIONSS,EVERSIONSUNIT MIN Typt MAXMINTyptMAX 2.42.4V 0.40.4V 1010p.A 1010p.A 40483545mA 3.553.55mA 28402537mA 28402537mA +" ... o 0. 0. ::l en > ... o E Q) ~ "'C c:: CO ~ C TEXAS INSTRUMENTS 4-49 POSTOFFICE BOX225012DALLAS, TEXAS75265 SMJ4164 65,536-811DYNAMICRANDOM-ACCESSMEMORY electricalcharacteristicsover fullrangesof recommendedoperatingconditions(unlessotherwisenoted) C '< ~ Q) 3 c=i" :D l> ~ Q) ~ c.. PARAMETER TEST CONDITIONS VOH High-leveloutputvoltage 10H= -5 mA VOL Low-leveloutput voltageIOL=4.2 mA IIInputcurrent(leakage) VI=O Vto5.8V,VOO=4.5V to5.5V.output open Vo=0Vto5.5V. 10Output current(leakage)VDO=5V. CAShigh 1 0 0 1 ~ Averageoperatingcurrent tc=minimumcycle duringreador writecycle 1002Standbycurrent After1memorycycle. RASandCAShigh tc=minimumcycle. 1 0 0 3 ~AveragerefreshcurrentRASlow. CAShigh tc(P)=minimumcycle. 1004 Averagepage-modecurrentRASlow. CAScycling tAlltypicalvaluesareatTC= 25Candnominalsupplyvoltages. tAdditional informationonlast page. VIL>-0.6 V. SMJ4164-20 S.EVERSIONS MIN Typt MAX 2.4 0.4 10 10 2737 3.55 2032 2032 ~capacitanceover recommendedsupplyvoltagerangeandoperatingfree-airtemperaturerange,f CD 3 o .., '< en C "C "C o .., r+ CilA) CilD) Ci(RC) Ci(W) Co PARAMETER Input capacitance.addressinputs Input capacitance.datainput Input capacitancestrobeinputs Inputcapacitance.write enableinput Output capacitance ~tAlltypicalvaluesareat TA= 25C andnominalsupplyvoltages. < SMJ4164 Typt MAX 47 47 810 810 58 UNIT V V p.A p.A mA mA mA mA 1MHz UNIT pF pF pF pF pF c=i"switchingcharacteristicsover recommendedsupply voltagerangeandoperatingfree-airtemperaturerange CD C/l PARAMETER --talC) AccesstimefromCAS ta(R)AccesstimefromRAS tdis(CH) Output disable time after CAShigh 4-50 TESTCONDITIONS ALT. SYMBOL CL=80 pF, tCAC seeFigure1 tRLCL=.MAX, tRAC seeFigure1 CL=80 pF, tOFF seeFigure1 TEXAS INSTRUMENTS POSTOFFICEBOX225012DALLAS. TEXAS 75265 SMJ4164-15SMJ4164-20 MVERSIONMVERSIONUNIT MINMAXMINMAX 100135ns 150200ns 050060ns SMJ4164 65,536-81TDYNAMICRANDOM-ACCESSMEMORY switchingcharacteristicsover recommendedsupplyvoltagerangeandoperatingfree-airtemperaturerange SMJ4164-12SMJ4164-15 PARAMETERTESTCONDITIONS ALT. S,EVERSIONS,EVERSIONSUNIT SYMBOL MINMAXMINMAX ta(C) AccesstimefromCAS CL=80pF, seeFigure1 tCAC 7085ns ta(R) AccesstimefromRAS tRLCL=MAX, seeFigure1 tRAC 120150ns tdis(CH) Output disabletimeCL=80 pF, tOFF 040040 afterCAShighseeFigure1 ns switchingcharacteristicsover recommendedsupplyvoltagerangeandoperatingfree-airtemperaturerange SMJ4164-20 ALT. PARAMETERTESTCONDITIONSS,EVERSIONUNIT SYMBOL MINMAX ta(C) AccesstimefromCAS CL=80 pF, seeFigure1 tCAC 135ns ta(R) AccesstimefromRAS tRLCL=MAX, seeFigure1 tRAC 200ns tdis(CH) Output disabletimeCL=80 pF, afterCAShighseeFigure1 tOFF 050ns en Q) (.) -s; Q) c ~ -o 0. 0. ::l (J) >--,0 E Q) ~ , ~ c: CO ~ a: (.) -e CO c: >-C TEXAS INSfRUMENTS 4-51 POSTOFFICEBOX225012DALLAS, TEXAS75265 c < :::J Q) 3 Ci-:0 ~ Q) :::J Co ~ CD 3 o ... < en c 'C 'C o ... r+ c CD < Ci" CD C/I SMJ4164 65,536-811DYNAMICRANDOM-ACCESSMEMORY timingrequirementsoverrecommendedsupply voltage rangeandoperatingfree-airtemperaturerange SMJ4164-15SMJ4164-20 ALT. MVERSIONPARAMETERMVERSIONUNIT SYMBOL MAXMINMAXMIN tc(P) Pagemodecycletimetpc160225ns tc(rd) Readcycletime t tRC 330410ns tc(W) Writecycletime twc 330410ns tc(rdW) Read-write/read-modify-writecycletime tRWC 345425ns tw(CH) Pulsewidth,CAShigh(prechargetime) +tcp5080ns tw(CL)Pulsewidth,CASlow tCAS1001,5001351.500ns tw(RH) Pulsewidth,RAShigh(prechargetime) tRP 160200ns twIRl) Pulsewidth,RASlow' tRAS 1501,5002001,500ns tw(W) Writepulsewidthtwp4555ns tt Transitiontimes(riseandfalllfor RASandCAStT320320ns tsu(CA) Columnaddresssetup time tASC 00ns tsu(RA) Rowaddresssetup time tASR 55ns tsu(D) Datasetuptime tDS 00ns tsu(rd) Readcommandsetup time tRCS 00ns tsu(WCH) Writecommandsetup timebeforeCAShigh tCWL 6080ns tsu(WRH) WritecommandsetuptimebeforeRAShigh tRWL 6080ns th(CLCA)Columnaddressholdtimeafter CASlowtCAH6070ns th(RA) Rowaddressholdtime tRAH 2025ns th(RLCA) Columnaddressholdtimeafter RASlow tAR 95140ns th(CLD) DataholdtimeafterCASlow tDH 7090ns th(RLD) DataholdtimeafterRASlow tDHR 125160ns th(WLD) DataholdtimeafterWlow tDH 5060ns th(CHrd) Readcommandholdtimeafter C-A-Shigh tRCH 00ns th(RHrd) ReadcommandholdtimeafterRAShigh tRRH 55ns th(CLW) Writecommandholdtime after CASlow tWCH 7090ns th(RLW) Writecommandholdtime after RASlow tWCR 125160ns tRLCH Delaytime,RASlow toCAShigh tCSH 150200ns tCHRLDelaytime,CAShightoRASlowtCRP00ns tCLRH Delaytime,CASlow toRAShigh tRSH 100135ns tCLWL Delaytime,CASlow to Wlow tCWD (read-modify-writecycleonly) 6065ns Delaytime,RASlow toCASlow tRLCL (maximumvaluespecifiedonly tRCD 20502565ns to guaranteeaccesstime) tRLWL Delaytime,RASlow toWlow tRWD 110130ns (read-modify-writecycleonly) tWLCL Delaytime,Wlow toCAS twcs 55ns low (earlywrite cycle) trfRefreshtime intervaltREF44ms NOTE:Timingmeasurements aremadeat the10%and90%points of input andclock transitions.Inaddition,VILmax andVIHmin must bemet at the 10%and90%points. tAllcycletimes assume tt=5ns. ;Pagemodeonly. In a read-modify-write cycle,tCLWL and tsu(WCH)must beobserved.Dependingon the user's transition times,this may requireadditional CAs low time (tw(CL)).Thisappliestopagemoderead-modify-writealso._ ,In a read-modify-write cycle,tRLWL and tsu(WRH)must be observed.Depending on the user's transition times, this may requireadditionalRASlow time (tw(RL)) 4-52 TEXAS INSfRUMENlS POSTOFFICE BOX225012DALLAS. TEXAS75265 SMJ4164 65,536-011DYNAMICRANDOM-ACCESSMEMORY timingrequirementsover recommendedsupplyvoltagerangeandoperatingfree-airtemperature range SMJ4164-12SMJ4164-15 ALT. S.EVERSIONSPARAMETERS,EVERSIONSUNIT SYMBOL MINMAXMINMAX tc(P) Pagemodecycletimetpc130160ns tc(rd) Readcycletime t tRC 230260ns tc(Wi Writecycletimetwc230260ns tc(rdW) Read-write/read-modify-writecycletime tRWC 260285ns twlCH) Pulsewidth,CAShigh(prechargetime) *tcp5050ns tw(CLl Pulsewidth,CASlow tCAS 7010,0008510,000ns tw(RH) Pulsewidth,RAShigh(prechargetime) tRP 80100ns twIRL) Pulsewidth,RASlow' tRAS 12010,00015010,000ns tw(Wi Writepulsewidthtwp4045ns tt Transitiontimes(riseandfall)for 'RASandCAS tT350350ns tsu(CA) Columnaddresssetup time tASC -5-5ns tsulRAi Row addresssetup time tASR 00ns tsu(D) Datasetuptime tDS 00ns tsu(rd)Readcommandsetup time tRCS00ns tsu(WCH) WritecommandsetuptimebeforeCAShigh tCWL 5050ns tsu(WRH) Writecommand setup timebefore RAShigh tRWL 5050ns th(CLCA) ColumnaddressholdtimeafterCASlow tCAH 4045ns th(RAJ Row addressholdtime tRAH 1520ns th(RLCA) ColumnaddressholdtimeafterRASlow tAR 8595ns th(CLD) Dataholdtimeafter CASlow tDH 4045 .. ns . th(RLDl DataholdtimeafterRASlow tDHR 8595ns th(WLD) DataholdtimeafterWlow tDH4045ns th(CHrd) Readcommandholdtimeafter CAShigh tRCH 00 -" ns th(RHrdl Readcommandholdtimeafter RAShigh tRRH 55ns th(CLW)WritecommandholdtimeafterCASlowtWCH4045ns tti(RLW) Writecommandholdtime after ~low tWCR 8595ns tRLCH Delaytime,RASlow toCAShigh tCSH 120150ns tCHRL Delay time,CAShightoRASlow tCRP 00ns tCLRH Delay time,CASlow toRAShigh tRSH 60100ns tCLWL Delaytime,CASlow toWlow tCWD (read-modify-writecycleonly) 4060ns Delaytime,RASlow toCASlow tRLCL (maximumvaluespecifiedonly tRCD 15502065ns toguaranteeaccesstime) tRLWL Delay time, RASlow to W low (read-modify-writecycleonly) tRWD85100ns tWLCL Delaytime,Wlow toCAS twcs -5-5 low(earlywritecycle) ns trf Refreshtimeinterval tREF 44ms NOTE:Timing measurementsaremadeatthe10%and90%points of input andclock transitions.Inaddition.VILmax andVIHmin must bemet atthe 10%and90%points. tAllcycletimesassumett= 5ns. tPagemodeonly. In a read-modify-write cycle, tCLWL and tsulWCH) must beobserved.Depending onthe user's transition times, this may require additional CAS low time (tw(CL))'Thisappliesto pagemoderead-modify-writealso.__ ,Ina read-modify-writecycle,tRLWL and tsu(WRH)must beobserved.Depending onthe user's transition times,thismay requireadditional RASlow time (tw(RL))' ~ a.. o 0. 0. ::l en >-a.. o E OJ ~ "0 c:: CO ~ a: (.) 'E CO c:: >-C TEXAS INSTRUMENTS 4-53 POSTOFFICEBOX225012DALLAS. TEXAS75265 c -< :l ~ 3 r;-lJ l> ~ ~ :l Co ~ CD 3 o ... -< en c 'C 'C o ... r+ c CD < r)" CD en SMJ4164 65,536-8ITDYNAMICRANDOM-ACCESSMEMORY timingrequirementsover recommendedsupplyvoltagerangeandoperatingfree-air temperaturerange SMJ4164-20 ALT. PARAMETERS,EVERSIONSUNIT SYMBOL MINMAX tclPI Pagemodecycle timetpc206ns tclrd) Readcycletime t tRC 326ns tc{WI Writecycletime twc 326ns tclrdWI Read-write/read-modify-writecycle time tRWC 345ns tw(CH) Pulsewidth,CAShigh(prechargetime):!:tcp80ns tw(CL)Pulsewidth,CAS low 9tCAS 13510,000ns twlRHI Pulsewidth,RAShigh(prechargetime) tRP 120ns twIRL) Pulsewidth,RASlow'tRAS 20010,000ns twlWI Writepulsewidthtwp55ns tt Transitiontimes(riseandfall)for RASandCAStT 350ns tsu(CA) Columnaddresssetup time tASC -5ns tsu(RA) Rowaddresssetuptime tASR 0ns tsulD) Datasetup time tDS 0ns tsu(rd) Readcommandsetuptime tRCS 0ns tsulWCHI WritecommandsetuptimebeforeCAS high tCWL 60ns tsu(WRH) WritecommandsetuptimebeforeRAShigh tRWL60ns thlCLCA) ColumnaddressholdtimeafterCASlowtCAH55ns th(RAl Rowaddressholdtime tRAH 25ns th(RLCA) ColumnaddressholdtimeafterRASlow tAR 120ns th(CLD) Dataholdtimeafter CASlow tDH 55ns thIRLD) Dataholdtimeafter RASlow tDHR 145ns th(WLD) Dataholdtimeafter W low tDH 55ns th(CHrdl Readcommandholdtimeafter 'CAShigh tRCH 0ns thlRHrd) ReadcommandholdtimeafterRAShigh tRRH 5ns th(CLW) Writecommandholdtimeafter CASlow tWCH 55ns th(RLW) Writecommandholdtimeafter RAS low tWCR 145ns tRLCH Delaytime,RASlow toCAShigh tCSH 200ns tCHRL Delaytime,CAShigh toRASlowtCRP 0ns tCLRH Delay time, CASlow to 'RAS high tRSH 135ns tCLWL Delay time, 'C:AS low to W low tCWD 65ns (read-modify-writecycleonly) Delaytime,RASlow toCASlow tRLCL (maximumvaluespecifiedonly tRCD 2565ns to guaranteeaccesstime) tRLWL Delaytime,RASlow to Wlow tRWD 130ns (read-modify-writecycleonly) tWLCL Delaytime,Wlow toCAS twcs -5ns low(earlywritecycle) trfRefreshtimeintervaltREF4ms NOTE:TImingmeasurementsare made at the10% and 90%points of input andclock transitions.Inaddition,VIL max andVIHminmust bemet at the 10% and90%points. tAllcycletimesassume tt= 5ns. :I:Pagemodeonly. In a read-modify-write cycle, tCLWL and tsu(WCH)must beobserved.Depending onthe user's transition times,this may requireadditional CAS low time (tw(CL))'Thisapplies to page moderead-modify-writealso._ ,Ina read-modify-write cycle,tRLWL and tsu(WRH)must be observed.Dependingon the user's transition times,this may requireadditional RASlow time (tw(RL))' 4-54 TEXAS INSTRUMENTS POSTOFFICEBOX 225012DALLAS. TEXAS75265 readcycletiming RAS CAS AO-A7 w Q TMS4164,SMJ4164 65,53681TDYNAMICRANDOMACCESSMEMORY PARAMETERMEASUREMENTINFORMATION OUTPUT UNDER TEST 1.31V -IRL Iel FIGURE1- LOADCIRCUIT en Q) (J .S; Q) C ... ... o c. C. :::::I CI) >-... o E Q) ~ ~ c: m ~ a::: (J 'E m c: >-C TEXAS INSTRUMENTS 4-55 POSTOFFICE BOX225012DALLAS. TEXAS75265 c -< :::l Q) 3 C:;" ~ ~ ~ Q) :::l c.. ~ CD 3 o ... -< rn c: '0 '0 o ... ... c CD < c:;" CD (I) TMS4164.SMJ4164 65.536"8ITDYNAMICRANDOM"ACCESSMEMORY earlywritecycletiming RAS CAS AO-A7 w o Q VOH VOL -----------HI-Z------------4-56 TEXAS INsrRuMENTS POSTOFFICEBOX 225012DALLAS. TEXAS75265 writecycletiming VIH RAS VIL VIH CAS VIL VIH AO-A7 V,L VIH Vi VIL V,H D V,L Q VOH VOL TMS4164,SMJ4164 65,5368ITDYNAMICRANDOMACCESSMEMORY I-tc(W) -, 1 , , I- tw(RL) II U -t I-tCLRH "I ,j.-tRLCL J.- tCHRL ---I , I..ItRLCH_I" 1 L

'--1l4jtSU(CA)I'" I ---I Jl-tt 1III _ROW1Itsu(WCH) --.f !I 1 th(RLW)-1I II

1IIr- tw(W)---..I 111 r-- th(WLD) 1 1 ---.tI. ,..th(RLD)..I, II, ---t j4-tsu(D)1 II t--- ten t ---.j j.-.f- tdis(CH) HI-Z NOTVALID CI) CD CJ .:; CD C .... .. 0 C. c. ::l tn > .. 0 E CD "C C ctS < CJ 'e ctS C > C tThe enable time (ten)for a write cycle is equal in duration to the access time from CAS (ta(C))ina read cycle;but the active levels at the output areinvalid. TEXAS INSTRUMENTS POSTOFFICEBOX225012DALLAS. TEXAS75265 4-57 C < ::l Q) 3 C:;' :xl l> s: Q) ::l C. s: (1) 3 0 ... < en c: "C "C 0 ... .... C (1) C' C:;' (1) en TMS4164,SMJ4164 65,536BITDYNAMICRANDOMACCESSMEMORY read-write/read-modify-writecycletiming RAS CAS AO-A7 W D Q I- tc(rdWI.\ ::: it'wIRL)Iti\. ---..!I--tt,- tCLRH.1j..-tW(RHI-.i \r--- tRLCL --,.....-tw(CLI-IH---,I tCHRL --.t II ;- =tIltRLCH ,J.;:::It-IIIlj."i\. t---- th(RLCA)II.1CtW(CHI--.-.t I,.. -Ith(RAII:\1 V'H.;fl-;',"IRAIU III VILROWCOLUMN III.-tsu(WCHI--t1\ I'I 1I1, I1r--tCLWL ---..tII I ..,I t- l'th(RLD):I..tI "- th(CLD)-oJI !I...-.c";-tsu(D)II' VIHVIL III.JI 1Ii--th(WLD)tdis(CHI II1:{ ------ HI-ZVALIDDATA>-----1!I I14--- VOL /- ta(R)./ 4-58 TEXAS INSTRUMENTS POSTOFFICE BOX225012DALLAS, TEXAS75265 z

z .J:>.c1J ....I Q. Q. ::I II) Q 9 VIH

::: VOH VOL---------------HI-Z----------------100 80 70 60 50 40 30 20 10 .100 IDD1vs.CYCLETIME

'(), ifi. 1-C This document contains information on a product under development.TexasInstruments reservesthe right to changeordiscontinuethisproductwithoutnotice. TEXAS INSTRUMENTS 4-63 POSTOFFICEBOX225012DALLAS, TEXAS75265 c -< j Q) 3 o :0 l> s: Q) j Co s: CD 3 o ~ -< (I'J c::: "C "C o ~ r+ c CD C o CD I/) TMS4256,TMS4257 262,14481TDYNAMICRANDOMACCESSMEMORIES requirements,andeasingboardlayout.IDD peaks are150 mA typical,anda-1-V input voltageundershoot canbe tolerated,minimizingsystemnoiseconsiderations. All inputs and outputs,including clocks,arecompatible with Series 74 TTL.All addressanddata-in lines arelatched onchiptosimplifysystemdesign.Data-outisunlatchedtoallowgreatersystemflexibility. The' 4256 and' 4257 are offered ina 16-pin dual-in-line ceramic or plastic package andare guaranteed for operation from 0 DCto 70 DC.These packages aredesigned for insertion in mounting-hole rows on300 mil (7,62 mm) centers. operation address(AOthroughAS) Eighteenaddressbitsarerequiredtodecode1of 262,144 storagecelllocations.Ninerow-addressbitsaresetup onpinsAOthroughA8andlatchedonto thechipby therow-addressstrobe(RAS).Then the ninecolumn-address bits areset up onPinsAOthrough A8 andlatchedonto the chipby the column-addressstrobe(CAS).Alladdresses mustbestableonorbeforethefallingedgesof RASandCAS.RASissimilartoachipenableinthatit activates the sense amplifiers aswell as the row decoder.CAS is usedasa chip select activating the column decoder and the input andoutputbuffers. writeenable(W) Thereador writemode isselectedthrough the-write enable(W)input.Alogic high onthe Winput selects the read modeandalogiclowselectsthewritemode.ThewriteenableterminalcanbedrivenfromstandardTTLcircuits without a pull-up resistor. The data input is disabled when the readmode is selected. When Wgoes low prior to CAS, data-outwillremaininthehigh-impedancestatefor theentirecyclepermittingcommonI/Ooperation. data-in(D) Dataiswrittenduringawrite orread-modifywritecycle.Dependingonthemodeof operation,thefallingedgeof CASor Wstrobesdataintotheon-chipdatalatch.ThislatchcanbedrivenfromstandardTTL circuitswithouta pull-up resistor.Inanearly-write cycle,Wisbro,ught low prior to CAS andthe dataisstrobed inby CASwith setup andhold times referenced to this signal.Ina delayed write or read-modify write cycle,CASwill already below, thus thedatawillbestrobedinby IN withsetupandholdtimesreferencedtothissignal. data-out(Q) Thethree-stateoutputbuffer providesdirect TTLcompatibility(nopull-upresistorrequired)witha fan-outof two Series74 TTLloads.Data-out isthesamepolarityasdata-in.Theoutput isinthehigh-impedance(floating)state until CAS is brought low. Ina readcycle the output goesactive after the access time interval talC)that begins with the negative transition of CAS aslong as.!illB.lis satisfied. The output becomes valid after the access time has elaps-edandremainsvalidwhileCASislow;CASgoinghighreturnsit toahigh-impedancestate.Inadelayed-writeor read-modify-writecycle,theoutputwillfollowthesequencefor thereadcycle. refresh Arefresh operationmust beperformed at least onceevery four milliseconds to retain data.Thiscanbeachievedby strobing each of the 256 rows (AO-A7).Anormal reador write cycle will refresh allbits in eachrow that isselected. ARAS-only operation canbeusedby holding CAS at thehigh(inactive)level,thus conserving power asthe output buffer remains in the high-impedance state. Hidden refresh may beperformed while maintaining valid data at the out-put pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified pre-charge period,similartoa"RAS-only"refreshcycle. CAS-before-RASrefresh(optional) The optional CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tCLRLland holding it low after RASfalls(seeparameter tRLCHR).Forsuccessive CAS-before-RASrefreshcycles,CAS canremainlow while cycling RAS.The external addressisignoredand the refreshaddressisgenerated internally.Fordevices with thisoption,theexternaladdressisalsoignoredduringthehiddenrefreshcycles. 4-64 TEXAS INSTRUMENTS POSTOFFICEBOX225012DALLAS, TEXAS75265 page-mode(TMS4256) TMS4256,TMS4257 262,1448ITDYNAMICRANDOMACCESSMEMORIES Page-mode operation allows effectively faster memory access by keeping the same row address and strobing random column addresses onto the chip.Thus, the time required to setup andstrobe sequentialrow addressesfor the same pageiseliminated.Themaximum number of columns that can be addressedisdetermined by tw(RL), the maximum RASlow pulsewidth.Forexample,with a minimumcycle time(tc(P)=100 ns)appr'oximately100 of the512 col-umns specified by column AO to column AScan be accessed.Row AS provided in the first page cycle,specifies which groupof512columns,outofthe1024 internalcolumnsistobepaged. nibble-mode(TMS4257) Nibble-mode operationallowshigh-speedserialread,write,or read-modify-writeaccessof1to 4bitsof data.The firstbit isaccessedinthenormaldatacomingout at talC)time.Thenext sequentialnibblebits canbereadorwrittenbycyclingCASwhileRASremainslow.Thefirstbitisdeterminedby therowandcolumn addresses,which need to besupplied only for the first access.Row ASandcolumnASprovide the twobinary bits for initialselection,with row ASbeing the least significant address.Thereafter,the fallingedgeof CASwillaccess thenextbitof thecircular4-bitnibbleinthefollowingsequence: C--(O,O).. (0,1) --------.,.... ( 1,0) -------1... (l,l):=-J Innibble-mode,allnormalmemory operations(read,write,or ready-modify-write)may beperformedinany desired combination. power-up To achieveproper device operation.aninitialpauseof 200 p'Sisrequiredafter power up followedby a minimum of eightinitializationcycles. logicsymbol t AO A1 A2 A3 A4 A5 A6 A7 AS RAS CAS W 0 RAM256KX1 (5) ....;..;..:...----12009/2100 (7) (6) (12) (11) (10) (13) (9) (1) (4) (15) (3) (2) A,220 A_O_ 262143 23C22 A\l (14) Q tThissymbolisinaccordancewithIEEEStd91/ANSIY32.14andrecentdecisionsbyIEEEandlEe.Seeexplanationonpage101. en Cl) .(.) 'S Cl) c ... ... o c. C. ::::J tJ) > ... o E Cl) "C t: CO a: (.) 'E CO t: > C TEXAS INSTRUMENTS 4-65 POSTOFFICEBOX225012DALLAS. TEXAS 75265 c < Q) 3 n' ::IJ l> 3: Q) c. 3: CD 3 o ... < CJ) C "C "C o ... r+ c CD < n' CD til TMS4256,TMS4257 262,14481TDYNAMICRANDOMACCESSMEMORIES functionalblockdiagram AD A1 A2 A3 A4 AS A6 A7 AB 1 ROW ADDRESS BUFFERS r--+-(8) rr; 1 CDLUMN ADDRESS BUFFERS (B) 1. ROW L r--f--- ---{ I---RASCASW ++ i I TIMINGANDCONTROL I

32KARRAY ROW 32KARRAY DECODE 256SENSEAMPS256SENSEAMPS 32KARRAY ROW 32KARRAY DECODE COLUMNDECODE ROW 32KARRAY32KARRAY DECODE 256SENSEAMPS256SENSEAMPS 32KARRAY RDW 32KARRAY DECODE !oorill--IN I/O REG BUFFERS 1 of4 SELEC-t--W-liON DUT REG .. absolutemaximumratingsover operatingfree-airtemperaturerange(ur:tlessotherwisenoted) t VoltageonanypinincludingVOOsupply(seeNote1)_..............................- 1Vto7V Shortcircuitoutputcurrent........................................................50mA Powerdissipation.................................................................1W Operatingfree-airtemperaturerange............................................OOCto700C Storagetemperaturerange................................................- 65 C to1500C tStressesbeyond those listed under "Absolute Maximum Ratings"may cause permanentdamage to the device.Thi.sisa stress only andfunctional operation of the device at these or any other conditions beyond thoseindicated inthe "Recommended OperatingConditions"section of this specification isnot implied.Exposureto absolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. NOTE1:Allvoltagevaluesinthis datasheetarewith respectto VSS. recommendedoperatingconditions PARAMETERMINNOMMAXUNIT Supplyvoltage,VOO4.555.5V Supplyvoltage,VSS0V High-levelinput voltage,VIH2.4VOO+0.3V Low-levelinput voltage,VIL (seeNote2)-10.8V Operatingfree-airtempera