Module 25 Storage: Retaining Information. Sensory Memory Short Term Memory Long Term Memory.
Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information...
-
Upload
lesley-dorsey -
Category
Documents
-
view
223 -
download
0
Transcript of Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information...
![Page 1: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/1.jpg)
Memory and Programmable Logic
Chapter 7
![Page 2: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/2.jpg)
2Digital Circuits
7-1 Introduction
Memory information storage a collection of cells store binary information
RAM – Random-Access Memory read operation write operation
ROM – Read-Only Memory read operation only a programmable logic device
![Page 3: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/3.jpg)
3Digital Circuits
Programmable Logic Device (PLD) ROM PLA – programmable logic array PAL – programmable array logic FPGA – field-programmable gate array
programmable logic blocks programmable interconnects
Fig. 7.1Conventional and array logic diagrams for OR gates
![Page 4: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/4.jpg)
4Digital Circuits
7-2 Random-Access Memory
A memory unit stores binary information in groups of bits (words) 8 bits (a byte), 2 bytes, 4 bytes
Block diagram
Fig. 7.2Block diagrams of a memory unit
![Page 5: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/5.jpg)
5Digital Circuits
A 1024 16 Memory
Fig. 7.3Contents of a 1024 16 memory
![Page 6: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/6.jpg)
6Digital Circuits
Write and Read Operations Write operation
• Apply the binary address to the address lines• Apply the data bits to the data input lines• Activate the write input
Read operation• Apply the binary address to the address lines• Activate the read input
![Page 7: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/7.jpg)
7Digital Circuits
Memory Description in HDL
Examples
![Page 8: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/8.jpg)
8Digital Circuits
HDL Example 7.1
![Page 9: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/9.jpg)
9Digital Circuits
Timing Waveforms
The operation of the memory unit is controlled by an external device
The access time the time required to select a word and read it
The cycle time the time required to complete a write operation
Read and write operations must synchronized with an external clock
![Page 10: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/10.jpg)
10Digital Circuits
CPU clock – 50 MHz The access/cycle time < 50 ns A write cycle
Fig. 7.4Memory cycle timing waveforms
![Page 11: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/11.jpg)
11Digital Circuits
A read cycle
Fig. 7.4Memory cycle timing waveforms (cont.)
![Page 12: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/12.jpg)
12Digital Circuits
Types of Memories
Static Information are stored in latches remains valid as long as power is applied short read/write cycle
Dynamic Information are stored in the form of charges on
capacitors the stored charge tends to discharge with time need to be refreshed (read and write back) reduced power consumption Larger memory capacity
![Page 13: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/13.jpg)
13Digital Circuits
Volatile lose stored information when power is turned off SRAM, DRAM
Non-volatile Retains its stored information after the removal of
power ROM EPROM, EEPROM Flash memory
![Page 14: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/14.jpg)
14Digital Circuits
7-3 Memory Decoding A memory unit
the storage components the decoding circuits to select the memory word
A memory cell
Fig. 7.5Memory cell
![Page 15: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/15.jpg)
15Digital Circuits
Internal Construction
A RAM of m words and n bits per word m*n binary storage cells Decoding circuits to select individual words
k-to-2k decoder
![Page 16: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/16.jpg)
16Digital Circuits
A 4 4 RAM
Fig. 7.6Diagram of a 4 4 RAM
![Page 17: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/17.jpg)
17Digital Circuits
Coincident Decoding A two-dimensional selection scheme
reduce the complexity of the decoding circuits
Fig. 7.7Two-dimensional decoding structure for a 1K-word memory
![Page 18: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/18.jpg)
18Digital Circuits
A 10-to-1024 decoder 1024 AND gates with 10 inputs per gates
Two 5-to-32 decoders 2 * (32 AND gates with 5 inputs per gates)
Reduce the circuit complexity and the cycle time
![Page 19: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/19.jpg)
19Digital Circuits
Address Multiplexing
The reduce the number of pins in the IC package consider a 64M1 DRAM
26-bit address lines Multiplex the address lines in one set of address
input pins
![Page 20: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/20.jpg)
20Digital Circuits
An examples RAS – row address strobe CAS – column address strobe
Fig. 7.8Address multiplexing for a 64K DRAM
![Page 21: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/21.jpg)
21Digital Circuits
Random Access MemoryRAS, CAS Addressing
Even to read 1 bit, an entire 64-bit row is read!
Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits!
Address RAS CAS Dout Valid
Col AddressRow Address
Read Cycle
Read RowRow Address Latched
Read Bit Within RowColumn Address Latched
Tri-stateOutputs
第三版內容,參考用 !
![Page 22: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/22.jpg)
22Digital Circuits
Random Access Memory
Address RAS CAS WE Din Valid
Col AddressRow Address
(1) Latch Row Address Read Row
(2) WE low
(3) CAS low: replace data bit
(4) RAS high: write back the modified row
(5) CAS high to complete the memory cycle
Write Cycle Timing
第三版內容,參考用 !
![Page 23: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/23.jpg)
23Digital Circuits
7-4 Error Detection And Correction
Improve the reliability of a memory unit A simple error detection scheme
a parity bit (Sec. 3-9) a single bit error can be detected, but cannot be
corrected An error-correction code
generates multiple parity check bits the check bits generate a unique pattern, called a
syndrome the specific bit in error can be identified
![Page 24: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/24.jpg)
24Digital Circuits
Hamming Code
k parity bits are added to an n-bit data word (2k –1 n + k) The bit positions are numbered in sequence from
1 to n + k Those positions numbered as a power of 2 are
reserved for the parity bits The remaining bits are the data bits
![Page 25: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/25.jpg)
25Digital Circuits
Example: 8-bit data word 11000100 Include 4 parity bits and the 8-bit word 12 bits
2k –1 n + k, n = 8 k = 4Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0 Calculate the parity bits: even parity assumption
P1 = XOR of bits (3, 5, 7, 9, 11) = 1 1 0 0 0 = 0
P2 = XOR of bits (3, 6, 7, 10, 11) = 1 0 0 1 0 = 0
P4 = XOR of bits (5, 6, 7, 12) = 1 0 0 0 = 1
P8 = XOR of bits (9, 10, 11, 12) = 0 1 0 0 = 1 Store the 12-bit composite word in memory.
Bit position: 1 2 3 4 5 6 7 8 9 10 11 120 0 1 1 1 0 0 1 0 1 0 0
![Page 26: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/26.jpg)
26Digital Circuits
When the 12 bits are read from the memory Check bits are calculated
C1 = XOR of bits (1, 3, 5, 7, 9, 11)
C2 = XOR of bits (2, 3, 6, 7, 10, 11)
C4 = XOR of bits (4, 5, 6, 7, 12)
C8 = XOR of bits (8, 9, 10, 11, 12)
If no error has occurredBit position: 1 2 3 4 5 6 7 8 9 10 1112
0 0 1 1 1 0 0 1 0 1 0 0
C = C8C4C2C1 = 0000
![Page 27: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/27.jpg)
27Digital Circuits
One-bit error error in bit 1
C1 = XOR of bits (1, 3, 5, 7, 9, 11) = 1
C2 = XOR of bits (2, 3, 6, 7, 10, 11) = 0
C4 = XOR of bits (4, 5, 6, 7, 12) = 0
C8 = XOR of bits (8, 9, 10, 11, 12) = 0
C8C4C2C1 = 0001
error in bit 5 C8C4C2C1 = 0101
Two-bit error errors in bits 1 and 5
C8C4C2C1 = 0100
![Page 28: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/28.jpg)
28Digital Circuits
The Hamming code can be used for data of nay length k check bits 2k –1 n + k
![Page 29: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/29.jpg)
29Digital Circuits
Single-Error Correction, Double-Error Detection Hamming code
Can detect and correct only a single error Multiple errors may not be detected.
Hamming code + a parity bit Can detect double errors and correct a single
error. The additional parity bit is the XOR of all the other
bits. E.g.: the previous 12-bit coded word
0 0 1 1 1 0 0 1 0 1 0 0 P13 0 0 1 1 1 0 0 1 0 1 0 0 1 (even parity).
![Page 30: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/30.jpg)
30Digital Circuits
When the word is read from memory If P = 0, the parity is correct; P = 1, incorrect Four cases
1. If C = 0, P = 0, no error
2. If C 0, P = 1, a single error that can be corrected
3. If C 0, P = 0, a double error that is detected but cannot be corrected
4. If C = 0, P = 1, an error occurred in the P13 bit
![Page 31: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/31.jpg)
31Digital Circuits
7-5 Read-Only Memory
Store permanent binary information 2k x n ROM
k address input lines enable input(s) three-state outputs
Fig. 7.9ROM block diagram
![Page 32: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/32.jpg)
32Digital Circuits
32 x 8 ROM 5-to-32 decoder 8 OR gates
each has 32 inputs 32x8 internal programmable connections
Fig. 7.10Internal logic of a 32 8 ROM
![Page 33: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/33.jpg)
33Digital Circuits
programmable interconnections close (two lines are connected) or open A fuse that can be blown by applying a high voltage pulse
Fig. 7.11Programming the ROM according to Table 7.3
![Page 34: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/34.jpg)
34Digital Circuits
ROM truth table (partial) an example
![Page 35: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/35.jpg)
35Digital Circuits
Combinational Circuit Implementation
ROM: a decoder + OR gates sum of minterms a Boolean function = sum of minterms For an n-input, m-output combinational ckt
2n m ROM Design procedure:
1. Determine the size of ROM
2. Obtain the programming truth table of the ROM
3. The truth table = the fuse pattern
![Page 36: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/36.jpg)
36Digital Circuits
Example 7-1
3 inputs, 6 outputs B1=0
B0=A0
8x4 ROM
![Page 37: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/37.jpg)
37Digital Circuits
ROM implementation Truth table
Fig. 7.12ROM implementation of Example 7.1
![Page 38: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/38.jpg)
38Digital Circuits
Types of ROM
Types of ROM mask programming ROM
IC manufacturers is economical only if large quantities
PROM: Programmable ROM fuses universal programmer
EPROM: erasable PROM floating gate ultraviolet light erasable
EEPROM: electrically erasable PROM longer time is needed to write flash ROM limited times of write operations
![Page 39: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/39.jpg)
39Digital Circuits
Combinational PLDs Programmable two-level logic
an AND array and an OR array
Fig. 7.13Basic configuration of three PLDs
![Page 40: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/40.jpg)
40Digital Circuits
7.6 Programmable Logic Array
PLA an array of programmable AND gates
can generate any product terms of the inputs an array of programmable OR gates
can generate the sums of the products more flexible than ROM use less circuits than ROM
only the needed product terms are generated
![Page 41: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/41.jpg)
41Digital Circuits
An exampleF1 = AB + AC + ABCF2 = (AC + BC)XOR gatescan invert the outputs
Fig. 7.14PLA with three inputs, four product terms, and two outputs
![Page 42: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/42.jpg)
42Digital Circuits
PLA programming table specify the fuse map
![Page 43: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/43.jpg)
43Digital Circuits
The size of a PLA The number of inputs The number of product terms (AND gates) The number of outputs (OR gates)
When implementing with a PLA reduce the number of distinct product terms the number of terms in a product is not important
![Page 44: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/44.jpg)
44Digital Circuits
Examples 7-2 F1(A, B, C) = (0, 1, 2, 4); F2(A, B, C) = (0, 5, 6, 7) both the true value and the complement of the function
should be simplified to check
Fig. 7.15Solution to Example 7.2
![Page 45: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/45.jpg)
45Digital Circuits
F1 = (AB + AC + BC) F2 = AB + AC + ABC
Fig. 7.14PLA with three inputs, four product terms, and two outputs
![Page 46: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/46.jpg)
46Digital Circuits
7-7 Programmable Array Logic
a programmable AND array and a fixed OR array The PAL is easier to program, but is not as flexible
as the PLA
第三版圖片,參考用 !
![Page 47: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/47.jpg)
47Digital Circuits
An example PAL product terms
cannot be shared
Fig. 7.16PAL with four inputs, four outputs, and a three-wide AND-OR structure
![Page 48: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/48.jpg)
48Digital Circuits
An example implementation
w(A,B,C,D) = (2,12,13)
x(A,B,C,D) = (7,8,9,10,11,12,13,14)
y(A,B,C,D) = (0,2,3,4,5,6,7,8,10,11,15)
z(A,B,C,D) = (1,2,8,12,13) Simplify the functions
w = ABC + ABCDx = A + BCD
y = AB + CD + BDz = ABC + ABCD + ACD + ABCD = w + ACD + ABCD
![Page 49: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/49.jpg)
49Digital Circuits
PAL programming table
![Page 50: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/50.jpg)
50Digital Circuits
w = ABC + ABCDx = A + BCD
y = AB + CD + BDz = w + ACD + ABCD
Fig. 7.17Fuse map for PAL as specified in Table 7.6
![Page 51: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/51.jpg)
51Digital Circuits
7-8 Sequential Programmable Devices
Sequential programmable logic device SPLD PLD + filp-flops
Fig. 7.18Sequential programmable logic device
![Page 52: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/52.jpg)
52Digital Circuits
Macrocell
A typical SPLD contains 8-10 macrocells
Fig. 7.19Basic macrocell logic
![Page 53: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/53.jpg)
53Digital Circuits
Programming features: AND array use or bypass the flip-flop select clock edge polarity preset or clear for the register complement an output programmable input/output pins
![Page 54: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/54.jpg)
54Digital Circuits
Altera macrocell
Clk MUX
Output MUXQ
F/B MUX
Invert Control
AND ARRAY
CLK
pad
8 Product TermAND-OR Array
+Programmable
MUX's
Programmable polarity
I/O Pin
Seq. LogicBlock
Programmable feedback
第三版內容,參考用 !
![Page 55: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/55.jpg)
55Digital Circuits
Complex PLD Put a lot of PLDS on a chip Add wires between them whose connections can
be programmed Use fuse/EEPROM technology
Fig. 7.20General CPLD configuration
![Page 56: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/56.jpg)
56Digital Circuits
Field-Programmable Gate Array Emulate gate array technology Hence Field Programmable Gate Array You need:
A way to implement logic gates A way to connect them together
PALs, PLAs = 10 - 100 Gate Equivalents Field Programmable Gate Arrays = FPGAs
100 - 1000(s) of Gate Equivalents
![Page 57: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/57.jpg)
57Digital Circuits
Logic blocks To implement combinational
and sequential logic Interconnect
Wires to connect inputs andoutputs to logic blocks
I/O blocks Special logic blocks at
periphery of device forexternal connections
Key questions: How to make logic blocks programmable? How to connect the wires? After the chip has been fabbed
Field-Programmable Gate Arrays
第三版內容,參考用 !
![Page 58: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/58.jpg)
58Digital Circuits
Basic Xilinx Architecture
Fig. 7.21Basic architecture of Xilinx Spartan and predecessor devices
![Page 59: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/59.jpg)
59Digital Circuits
Configurable Logic Block (CLB)
Fig. 7.22CLB architecture
![Page 60: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/60.jpg)
60Digital Circuits
Interconnect Resources
Fig. 7.23RAM cell controlling a PIP transition gate
![Page 61: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/61.jpg)
61Digital Circuits
Programmable Interconnect Point (PIP)
Fig. 7.24Circuit for a programmable PIP
![Page 62: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/62.jpg)
62Digital Circuits
I/O Block (IOB)
Fig. 7.25XC4000 series IOB
![Page 63: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/63.jpg)
63Digital Circuits
Enhancements
Fig. 7.26Distributed RAM cell formed from a lookup table
![Page 64: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/64.jpg)
64Digital Circuits
Xilinx Spartan XL FPGAs
Fig. 7.27Spartan dual-port RAM
![Page 65: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/65.jpg)
65Digital Circuits
Xilinx Spartan XL FPGAs
![Page 66: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/66.jpg)
66Digital Circuits
Xilinx Spartan II FPGAs
![Page 67: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/67.jpg)
67Digital Circuits
Xilinx Spartan II FPGAs
![Page 68: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/68.jpg)
68Digital Circuits
Xilinx Spartan II FPGAs
Fig. 7.28Spartan II architecture
![Page 69: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/69.jpg)
69Digital Circuits
Xilinx Spartan II FPGAs
Fig. 7.29Spartan II CLB slice
![Page 70: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/70.jpg)
70Digital Circuits
Xilinx Spartan II FPGAs
Fig. 7.30Spartan II IOB
![Page 71: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/71.jpg)
71Digital Circuits
Xilinx Virtex FPGAs
Fig. 7.31Virtex II overall architecture
![Page 72: Memory and Programmable Logic Chapter 7. Digital Circuits 2 7-1 Introduction Memory information storage a collection of cells store binary information.](https://reader034.fdocuments.in/reader034/viewer/2022051621/5697bf8d1a28abf838c8c88d/html5/thumbnails/72.jpg)
72Digital Circuits
Xilinx Virtex FPGAs
Fig. 7.32Virtex IOB block