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Lecture 7 - 1Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Lecture 7
Memory and Array Circuits
Konstantinos Masselos
Department of Electrical & Electronic Engineering
Imperial College London
URL: http://cas.ee.ic.ac.uk/~kostas
E-mail: [email protected]
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Lecture 7 - 2Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Based on slides/material by
J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html
Digital Integrated Circuits: A Design Perspective, Prentice Hall
D. Harris http://www.cmosvlsi.com/coursematerials.html
Weste and Harris, CMOS VLSI Design: A Circuits and Systems
Perspective, Addison Wesley
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Lecture 7 - 3Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Recommended Reading
J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective:
Chapter 12
Weste and Harris, CMOS VLSI Design: A Circuits and SystemsPerspective: Chapter 11
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Outline
Memory classification
Basic building blocks
ROM
Non Volatile Read Write Memories
Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit Content Addressable Memory (CAM)
Serial access memories
Programmable Logic Array Reliability and Yield
Memory trends
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Semiconductor Memory Classification
RWM NVRWM ROM
EPROM
E2
PROM
FLASH
Random
Access
Non-Random
Access
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO
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Lecture 7 - 6Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Memory Arrays
Memory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory
(CAM)
Read/Write Memory
(RAM)
(Volatile)
Read Only Memory
(ROM)
(Nonvolatile)
Static RAM
(SRAM)
Dynamic RAM
(DRAM)
Shift Registers Queues
First In
First Out
(FIFO)
Last In
First Out
(LIFO)
Serial In
Parallel Out
(SIPO)
Parallel In
Serial Out
(PISO)
Mask ROM Programmable
ROM
(PROM)
Erasable
Programmable
ROM
(EPROM)
Electrically
Erasable
Programmable
ROM
(EEPROM)
Flash ROM
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Lecture 7 - 7Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Outline
Memory classification
Basic building blocks
ROM
Non Volatile Read Write Memories
Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit Content Addressable Memory (CAM)
Serial access memories
Programmable Logic Array Reliability and Yield
Memory trends
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Lecture 7 - 8Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Memory Architecture: Decoders
Word 0
Word 1
Word 2
Word N-1
Word N-2
Input-Output
S0
S1
S2
SN-2
SN_ 1
(M bits)
StorageCell
M bits
NWords
Word 0
Word 1
Word 2
Word N-1
Word N-2
Input-Output(M bits)
StorageCell
M bits
De
coder
A0
A1
AK -1
S0
N words => N select signals
Too many select signals
Decoder reduces # of select signals
K = log2N
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Lecture 7 - 9Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Array-Structured Memory Architecture
Input-Output(M bits)
RowDecoderAK
AK+1
AL-1
2L- K
Column Decoder
Bit Line
Word Line
A0
AK -1
Storage Cell
Sense Amplifiers / Drivers
M.2K
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing torail-to-rail amplitude
Selects appropriateword
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Lecture 7 - 10Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Hierarchical Memory Architecture
Global Data Bus
RowAddress
ColumnAddress
BlockAddress
Block Selector GlobalAmplifier/Driver
I/O
Control
Circuitry
Advantages:1. Shorter wires within blocks2. Block address activates only 1 block => power savings
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Lecture 7 - 12Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Memory Timing: Approaches
AddressBus
RAS
CAS
RAS-CAS timing
Address
BusAddress
Address transitioninitiates memory operation
DRAM Timing SRAM Timing
Row Address Column Address
MSB LSB
Multiplexed Adressing Self-timed
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Lecture 7 - 13Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Outline
Memory classification
Basic building blocks
ROM
Non Volatile Read Write Memories
Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit Content Addressable Memory (CAM)
Serial access memories
Programmable Logic Array Reliability and Yield
Memory trends
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Lecture 7 - 14Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Read-Only Memories
Read-Only Memories are nonvolatile
Retain their contents when power is removed
Mask-programmed ROMs use one transistor per bit
Presence or absence determines 1 or 0
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Lecture 7 - 15Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
ROM Example
4-word x 6-bit ROM
Represented with dot diagram
Dots indicate 1s in ROM
Wor d 0: 010101
Wor d 1: 011001
Wor d 2: 100101
Wor d 3: 101010
ROM Array
2:4
DEC
A0A1
Y0Y1Y2Y3Y4Y5
weak
pseudo-nMOS
pullups
Looks like 6 4-input pseudo-nMOS NORs
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Lecture 7 - 16Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
MOS NOR ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
GND
GND
VDD
Pull-up devices
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Lecture 7 - 17Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
MOS NOR ROM Layout
Metal1 on top of diffusion
Basic cell10x 7
2
W L[0]
W L[1]
W L[2]
W L[3]
G ND(diffusion)
Metal1
Polysilicon
Only 1 layer (contact mask) is used to program memory arrayProgramming of the memory can be delayed to one of
last process steps
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Lecture 7 - 18Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
MOS NOR ROM Layout
Basic Cell
8.5x 7
WL[0]
WL[1]
WL[2]
WL[3]
Metal1 over diffusion
Threshold raising
implant
BL[0] BL[1] BL[2] BL[3]
Polysilicon
GND (diffusion)
Threshold raising implants disable transistors
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Lecture 7 - 19Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
MOS NAND ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL [1] BL[2] BL[3]
VDD
Pull-up devices
All word lines high by default with exception of selected row
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Lecture 7 - 20Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
MOS NAND ROM Layout
Basic cell
5 x 6
Threshold
implant
Polysilicon
Diffusion
lowering
No contact to VDD or GND necessary;
Loss in performance compared to NOR ROM
drastically reduced cell size
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Lecture 7 - 21Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Precharged MOS NOR ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
GND
GND
VD D
Precharge devicesp re
PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.
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Lecture 7 - 22Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Building Logic with ROMs
Use ROM as lookup table containing truth table
n inputs, k outputs requires 2n words x k bits
Changing function is easy reprogram ROM
Finite State Machine n inputs, k outputs, s bits of state
Build with 2n+s x (k+s) bit ROM and (k+s) bit reg
n
inputs
2nw
ordlines
ROM Array
k outputs
DEC ROM
inputs outputs
state
n ks
k
s
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Lecture 7 - 23Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Outline
Memory classification
Basic building blocks
ROM
Non Volatile Read Write Memories
Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit Content Addressable Memory (CAM)
Serial access memories
Programmable Logic Array
Reliability and Yield
Memory trends
N l til R d W it M i (NVRW)
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Lecture 7 - 24Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Nonvolatile Read-Write Memories (NVRW)
Architecture virtually identical to the ROM structure
the memory core consists of an array of transistors placed on a word-line/bit-
line grid
The memory is programmed by selectively disabling or enabling some ofthose devices
in a ROM this is accomplished by mask level alterations
in a NVRW memory a modified transistor that permits its threshold to be
altered electrically is used instead the modified threshold is retainedindefinitely (or long) even when the supply voltage is turned off
To reprogram the memory the programmed values must be erased after
which a new programming round can be started
The method of erasing is the main differentiating factor between the variousclasses of reprogrammable non volatile memories
The programming of the memory is typically an order of magnitude slower
than the reading operation
PROM d EPROM
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Lecture 7 - 25Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
PROMs and EPROMs
Programmable ROMs
Build array with transistors at every site
Burn out fuses to disable unwanted transistors
Electrically Programmable ROMs Use floating gate to turn off unwanted transistors
EPROM, EEPROM, Flash
n+
p
GateSource Drain
bulk Si
Thin Gate Oxide
(SiO2)
n+
Polysilicon
Floating Gate
Fl ti t t i t (FAMOS)
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Lecture 7 - 26Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Floating-gate transistor (FAMOS)
Source Drain
GateFloating gate
tox
tox
Substrate
n+n+ p
(a) Device cross-section
S
D
G
(b) Schematic symbol
Fl ti G t T i t P i
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Lecture 7 - 27Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Floating-Gate Transistor Programming
DS
20 V
20 V
DS
0 V
0 V10 V 5 V 5 V
DS
5 V
5 V2.5 V
Avalanche injection. Removing programming voltageleaves charge trapped.
Programm ing results inhigher VT.
Characteristics of Non Volatile Memories
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Lecture 7 - 28Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Characteristics of Non Volatile Memories
Outline
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Lecture 7 - 29Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Outline
Memory classification
Basic building blocks
ROM
Non Volatile Read Write Memories
Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit Content Addressable Memory (CAM)
Serial access memories
Programmable Logic Array
Reliability and Yield
Memory trends
Read Write Memories (RAM)
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Lecture 7 - 30Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Read-Write Memories (RAM)
STATIC (SRAM)
DYNAMIC (DRAM)
Data s tored as long as supply is app lied
Large (6 trans istors/cel l)Fast
Differential
Period ic refresh req uired
Small (1-3 t ransis tors /cell)
Slower
Sing le Ended
6 transistor CMOS SRAM Cell
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Lecture 7 - 31Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
6-transistor CMOS SRAM Cell
VDD
Q
Q
M1 M3
M4M2
M5
BL
WL
BL
M6
SRAM Read/Write
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Lecture 7 - 32Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
SRAM Read/Write
CMOS SRAM Analysis (Read)
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Lecture 7 - 33Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
CMOS SRAM Analysis (Read)
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
0.0
0.5
1.0
1.5
0 100 200 300 400 500 600
time (ps)
word bit
A
A_b bit_b
Precharge both bitlines high
Then turn on wordline
One of the two bitlines will be pulled down by the cell
Ex: A = 0, A_b = 1 bit discharges, bit_b stays high
But A bumps up slightly
Read stability
A must not flip
N1 >> N2
CMOS SRAM Analysis (Write)
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Lecture 7 - 34Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
CMOS SRAM Analysis (Write)
Drive one bitline high, the other low
Then turn on wordline
Bitlines overpower cell with new value
Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high
Writability
Must overpower feedback inverter
N2 >> P1
time (ps)
word
A
A_b
bit_b
0.0
0.5
1.0
1.5
0 100 200 300 400 500 600 700
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
SRAM Sizing
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Lecture 7 - 35Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
SRAM Sizing
High bitlines must not overpower inverters during reads
But low bitlines must write new value into cell
bit bit_b
med
A
weak
strong
med
A_b
word
6T-SRAM Layout
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Lecture 7 - 36Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
6T SRAM Layout
VDD
GND
QQ
WL
BLBL
M1 M3
M4M2
M5 M6
Resistance-load SRAM Cell
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Lecture 7 - 37Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Resistance load SRAM Cell
VD D
QQ
M1 M2
M3
BL
WL
BL
M4
RL RL
Static power dissipation -- Want RLlargeBit lines precharged to VDDto address tpproblem
Multiple Ports
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Lecture 7 - 38Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Multiple Ports
We have considered single-ported SRAM
One read or one write on each cycle
Multiported SRAM are needed for register files
Examples: Multicycle MIPS must read two sources or write a result on some cycles
Pipelined MIPS must read two sources and write a third result each cycle
Superscalar MIPS must read and write many sources and results each cycle
Dual-Ported SRAM
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Lecture 7 - 39Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Simple dual-ported SRAM
Two independent single-ended reads
Or one differential write
Do two reads and one write by time multiplexing
Read during ph1, write during ph2
bit bit_b
wordBwordA
True dual port SRAM
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Lecture 7 - 40Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
p
Multi-Ported SRAM
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Lecture 7 - 41Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Adding more access transistors hurts read stability
Multiported SRAM isolates reads from state node
Single-ended design minimizes number of bitlines
bA
wordBwordA
wordDwordC
wordFwordE
wordG
bB bC
write
circuits
read
circuits
bD bE bF bG
Outline
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Lecture 7 - 42Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Memory classification
Basic building blocks
ROM
Non Volatile Read Write Memories Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit Content Addressable Memory (CAM)
Serial access memories
Programmable Logic Array
Reliability and Yield
Memory trends
3-Transistor DRAM Cell
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Lecture 7 - 43Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
M2M1
BL1
WWL
BL2
M3
RWL
CS
X
WWL
RWL
X
BL1
BL2
VDD -VT
V
VDD
VDD -VT
No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a 1 = VW W L-VT n
3T-DRAM Layout
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Lecture 7 - 44Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
1-Transistor DRAM Cell
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Lecture 7 - 45Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
CSM1
BL
WL
CBL
WL
X
BL
VDD VT
VD D
/2
VD D
GN D
Write "1" Read "1"
sensing
VDD
/2
V VB L V PR E V B IT V PR E( )CS
CS CB L+------------------------= =
Write: CSis charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
DRAM Cell Observations
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Lecture 7 - 46Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
1T DRAM requires a sense amplifier for each bit line, due to
charge redistribution read-out.
DRAM memory cells are single ended in contrast to SRAM cells.The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
Unlike 3T cell, 1T cell requires presence of an extra capacitancethat must be explicitly included in the design.
When writing a 1 into a DRAM cell, a threshold voltage is lost.
This charge loss can be circumvented by bootstrapping theword lines to a higher value than VD D .
1-T DRAM Cell
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Lecture 7 - 47Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
(a) Cross-section
(b) Layout
Diffusedbit line
Polysilicon
plate
M1 word
line
Capacitor
Polysilicon
gate
Metal word line
SiO2
n+Field Oxide
Inversion layerinduced by
plate bias
n+
poly
poly
Used Polysilicon-Diffusion Capacitance
Expensive in Area
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Outline
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Lecture 7 - 49Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Memory classification
Basic building blocks
ROM
Non Volatile Read Write Memories Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit Content Addressable Memory (CAM)
Serial access memories
Programmable Logic Array
Reliability and Yield
Memory trends
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Row Decoders
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Lecture 7 - 51Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
A NAND Decoder using 2-input Pre-Decoders
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Lecture 7 - 52Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
A0A1 A0A1 A0A1 A0A 1 A 2A3 A2A3 A2A3 A2A3
A1 A 0 A0 A1 A3 A2 A2 A3
WL0
WL1
Splitting decoder into two or more logic layersproduces a faster and cheaper implementation
Dynamic Decoders
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Lecture 7 - 53Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
WL 3
GND GNDPrecharge devices
WL 2
WL 1
WL 0
VD D A0 A0 A1 A1 A0 A0 A1 A1
VDD
VDD
VDD
VDD
WL 3
WL 2
WL 1
WL 0
Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder
Propagation delay is primary concern
4 input Pass-Transistor based Column Decoder
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Lecture 7 - 54Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
BL 0 BL 1 BL 2 BL 3
D
A0
A1
S0
S1
S2
S32inputNOR
deco
der
Advantage: speed (t pd does not add to overall memory access time)
Disadvantage: large transistor count
only 1 extra transistor in signal path
4-to-1 Tree based Column Decoder
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Lecture 7 - 55Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
BL0 BL1 BL2 BL3
D
A0
A0
A1
A1
Number of devices drastically reducedDelay increases quadratically with # of sections; prohibitive for large decoders
buffers
progressive sizing
combination of tree and pass transistor approaches
Solutions:
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Sense Amplifiers
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Lecture 7 - 57Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
tp
C V
Iav
----------------=
make V as small
as possible
smalllarge
Idea: Use Sense Amplifer
outputinput
s.a.smalltransition
Differential Sensing - SRAM
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Lecture 7 - 58Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Diff.Sense
Amp
BLBL
SRAM cell i
x x
y y
D D
VDDVDD
WLi
PC
EQ
VDD
x x
y
SE
VDD
xx
y
SE
VDD
x x
y
SE
(b) Doubled-ended Current Mirror Amplifier
y
(a) SRAM sensing scheme.(c) Cross-Coupled Amplifier
M1 M2
M4M3
M5
Latch-Based Sense Amplifier
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Lecture 7 - 59Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
VD D
BL
SE
SE
BLEQ
Initialized in its meta-stable point with EQOnce adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
Single-to-Differential Conversion
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Lecture 7 - 60Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Diff.
S.A.cell
BL
Vref+_
WL
x x
y y
How to make good Vref?
Open Bitline Architecture
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Lecture 7 - 61Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
VDD
SE
SE
CS CS CS
L
...CSCS
...CS
R
BLL BLR
L0L1 R0 R1
dummy
cell
dummy
cell
EQ
DRAM Read Process with Dummy Cell
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Lecture 7 - 62Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
0 1 2 3 4 5t (nsec )
0.0
2.0
4.0
6.0
V
(Volt)
0 1 2 3 4 5t (nsec)
0.0
2.0
4.0
6.0
V
(Volt)
0 1 2 3 4 50.0
1.0
2.0
3.0
4.0
5.0
V
(Volt)
EQ
WL
SE
BL
BL
BL
BL
(a) readin g a zero
(b ) read ing a one
(c) control s ignals
Single-Ended Cascode Amplifier
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Lecture 7 - 63Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
VDD
WL
WL C
Vca sc
DRAM Timing
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Lecture 7 - 64Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Address Transition Detection
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Lecture 7 - 65Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
DELAYtdA0
DELAY
td
DELAY
td
ATD
.. .
A1
AN-1
VDD
ATD
Outline
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Lecture 7 - 66Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Memory classification Basic building blocks
ROM
Non Volatile Read Write Memories Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit
Content Addressable Memory (CAM)
Serial access memories
Programmable Logic Array
Reliability and Yield
Memory trends
Content Addressable Memories (CAMs)
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Lecture 7 - 67Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Extension of ordinary memory (e.g. SRAM) Read and write memory as usual
Also match to see which words contain a key
CAM
adr data/key
match
read
write
CAM Cell Operation
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Lecture 7 - 68Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Read and write like ordinary SRAM For matching:
Leave wordline low
Precharge matchlines
Place key on bitlines
Matchlines evaluate
Miss line
Pseudo-nMOS NOR of match lines Goes high if no words match
row
deco
der
weak
missmatch0
match1
match2
match3
clk
column circuitry
CAM cell
address
data
read/write
10T CAM Cell
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Lecture 7 - 69Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Add four match transistors to 6T SRAM
bit bit_bword
match
cell
cell_b
Outline
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Lecture 7 - 70Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Memory classification Basic building blocks
ROM
Non Volatile Read Write Memories Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit
Content Addressable Memory (CAM)
Serial access memories
Programmable Logic Array
Reliability and Yield
Memory trends
Serial Access Memories
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Lecture 7 - 71Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Serial access memories do not use an address Shift Registers
Tapped Delay Lines
Serial In Parallel Out (SIPO)
Parallel In Serial Out (PISO)
Queues (FIFO, LIFO)
Shift Register
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Lecture 7 - 72Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Shift registers store and delay data Simple design: cascade of registers
Watch your hold times!
clk
Din Dout8
Denser Shift Registers
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Lecture 7 - 73Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Flip-flops arent very area-efficient For large shift registers, keep data in SRAM instead
Move read/write pointers to RAM rather than data
Initialize read address to first entry, write to last Increment address on each cycle
Din
Dout
clk
counter c
ounter
reset
00...00
11...11
readaddr
writeaddr
dual-ported
SRAM
Tapped Delay Line
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Lecture 7 - 74Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
A tapped delay line is a shift register with a programmable number ofstages
Set number of stages with delay controls to mux
Ex: 0 63 stages of delay
SR32
clk
Din
delay5
SR16
delay4
SR8
delay3
SR4
delay2
SR2
delay1
SR1
delay0
Dout
Serial In Parallel Out
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Lecture 7 - 75Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
1-bit shift register reads in serial data After N steps, presents N-bit parallel output
clk
P0 P1 P2 P3
Sin
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Queues
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Lecture 7 - 77Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Queues allow data to be read and written at different rates. Read and write each use their own clock, data
Queue indicates whether it is full or empty
Build with SRAM and read/write counters (pointers)
Queue
WriteClk
WriteData
FULL
ReadClk
ReadData
EMPTY
FIFO, LIFO Queues
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Lecture 7 - 78Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
First In First Out (FIFO) Initialize read and write pointers to first element
Queue is EMPTY
On write, increment write pointer
If write almost catches read, Queue is FULL
On read, increment read pointer
Last In First Out (LIFO)
Also called a stack Use a single stack pointerfor read and write
Outline
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Lecture 7 - 79Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Memory classification Basic building blocks
ROM
Non Volatile Read Write Memories Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit
Content Addressable Memory (CAM)
Serial access memories
Programmable Logic Arrays
Reliability and Yield
Memory trends
Programmable Logic Array
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Lecture 7 - 80Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
x0 x1 x2
f0 f1
A NDPLANE
ORPLANE
x0x1
x2
Product Terms
PLAs
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Lecture 7 - 81Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
A Programmable Logic Array performs any function in sum-of-productsform.
Literals: inputs & complements
Products / Minterms: AND of literals
Outputs: OR of Minterms
Example: Full Adder
out
s abc abc abc abc
c ab bc ac
= + + +
= + +
AND Plane OR Plane
abc
abc
abc
abc
ab
bc
ac
sa b coutc
Minterms
Inputs Outputs
NOR-NOR PLAs
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Lecture 7 - 82Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
ANDs and ORs are not very efficient in CMOS Dynamic or Pseudo-nMOS NORs are very efficient
Use DeMorgans Law to convert to all NORs
AND Plane OR Plane
abc
abc
abc
abc
ab
bc
ac
s
a b c
outc
AND Plane OR Plane
abc
abc
abc
abc
ab
bc
ac
s
a b c
outc
Pseudo-Static PLA
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Lecture 7 - 83Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
f0 f1
GND
GND
VD D
GND
x0 x0 x1 x1 x2 x2
GND GND GND GND
VDD
AND-PLANE OR-PLANE
PLA Schematic & Layout
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Lecture 7 - 84Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
AND Plane OR Plane
abc
abc
abc
abc
ab
bc
ac
s
a b c
outc
Dynamic PLA
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Lecture 7 - 85Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
f0 f1 GND
VDD
OR
x0 x0 x1 x1 x2 x2
GND
VDD
AND-PLANE OR-PLANE
ANDO R
A ND
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PLA Layout
A d Pl O Pl
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Lecture 7 - 87Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
VDD GNDAnd-Plane Or-Plane
f0 f1x0 x0 x1 x1 x2 x2
Pull-up devices Pull-up devices
PLA versus ROM
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Lecture 7 - 88Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Programmable Logic Arraystructured approach to random logictwo level logic implementation
NOR-NOR (product of sums)
NAND-NAND (sum of products)
IDENTICAL TO ROM!
Main difference
ROM: fully populatedPLA: one element per minterm
Note: Importance of PLAs has drastically reduced
1. slow2. better software techniques (mutli-level logicsynthesis)
Outline
M l ifi ti
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Lecture 7 - 89Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Memory classification Basic building blocks
ROM
Non Volatile Read Write Memories
Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit
Serial access memories
Content Addressable Memory (CAM)
Programmable Logic Array
Reliability and Yield Memory trends
Reliability and Yield
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Lecture 7 - 90Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Open Bit-line Architecture Cross Coupling
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Lecture 7 - 91Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Sense
AmplifierC C CCCC
WL1 WL0 WLD WLD WL0 WL1
EQ
CWBLCWBL
CBL
BL
CBL
BL
Folded-Bitline Architecture
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Lecture 7 - 92Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
BL
...
WLDWLD
BL
y
yx
x
WL0
CCCCCC EQ
Sense
Amplifier
WL0WL1WL1
CBL
CBL
CWBL
CWBL
Transposed-Bitline Architecture
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Lecture 7 - 93Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
BL
BL
BL
BL"
SA
Ccross
SABL
BL
BL
BL"
Ccross
(a) Straightforward bitline routing.
(b) Transposed bitline architecture.
Yield
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Lecture 7 - 94Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Yield curves at different stages of process maturity
(from [Veendrick92])
Redundancy
Row
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Lecture 7 - 95Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
MemoryArray
Redundant
columns
Redundant
rows
Column Decoder
RowDecoder
Row
Address
Column
Address
FuseBank
:
Redundancy and Error Correction
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Lecture 7 - 96Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Outline
Memory classification
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Lecture 7 - 97Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Memory classification Basic building blocks
ROM
Non Volatile Read Write Memories
Static RAM (SRAM)
Dynamic RAM (DRAM)
Memory peripheral circuit
Serial access memories
Content Addressable Memory (CAM)
Programmable Logic Array
Reliability and Yield Memory trends
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Semiconductor Memory Trends
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Lecture 7 - 99Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Increasing die size
factor 1.5 per generation
Combined with reducing cell size
factor 2.6 per generation
Semiconductor Memory Trends
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Lecture 7 - 100Introduction to Digital Integrated Circuit DesignMemory and Array Circuits
Technology feature size for different SRAM generations