Memorias-I-OK.pdf

7/24/2019 Memorias-I-OK.pdf

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Digital System Design

ourse


2/101

Digital system design for Dummies

Do not read this.!!!


3/101

Digital system design for Wise Guys

Wise Guys

Students of

Electronics Engineering


4/101

Clever/Agile

Students


12

3


5/101


1

2+

2

1

Laboratory 1 EEPROM


6/101



7/101

Semiconductor Memories


8/101

Memory Arrays

Memor Arra s


9/101

Static

RAM

Dynamic

RAM

Flash

EEPROM


10/101

Latches

Flip-flops

RegistersRegister bank

Memory Arrays

Very small

capacity

Memory Arrays

RAM SRAM

DRAMROM

EPROM EEPROM flash

Very high

capacity


11/101

DRAM EEPROMFlash


12/101

1.Memory Devices for Computers

CACHE Main

Secondary

Processor

Fast

static

Dynamic

RAM Disk

1 2 3

CACHE

SRAM DRAM


13/101

1. Anatomy of a Computer

Block diagram view: memory system

address

read/write

data

Processor Memory

System

2

MMU

CacheMain

MemD or I

VA PAPA

D or I

Processor


14/101

1. Anatomy of a Computer

Block diagram view: memory system

address

read/write

data

Processor Memory

System

2

Processor MMU

Cache

secundaria

Main

MemD or I

VA PAPA

D or ICacheprimaria


15/101

1. Memory Hierarchy

ProcessorRegisters

On ChipCache

Local

Higher

Cost

10 ns

10 ns

20 ns

1

1

2

Various memory

devices are used in a

computer system

They have differentspeeds and costs

SecondaryCache

Global

Memory

MassStorage

Slower

Access

Higher

Density

60 ns

100 ns

12 ms

3

10

1,200

DRAM

HDD


16/101

1. Memory Hierarchy

Want inexpensive, fast memory

Main memory Large, inexpensive, slow

memory stores entire program

and data

Cache Small, expensive, fast memory

Processor

Registers

parts of larger memory Can be multiple levels of cache Main memory

Disk

Tape


17/101

Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory (CAM)

Read/Write Memory(RAM)

(Volatile)

Read Only Memory(ROM)

(Nonvolatile)

Shift Registers Queues

1. Memory Arrays

Static RAM(SRAM)

Dynamic RAM(DRAM)

First InFirst Out(FIFO)

Last InFirst Out(LIFO)

Serial InParallel Out

(SIPO)

Parallel InSerial Out

(PISO)

Mask ROM ProgrammableROM

(PROM)

ErasableProgrammable

ROM(EPROM)

ElectricallyErasable

ProgrammableROM

(EEPROM)

FlashEEPROM


18/101

1.Memory types

Memory Types Features

FLASH Low-cost, high-density, high-speedarchitecture; low power; high reliability

ROMRead-Only Memory

Mature, high-density, reliable, low cost;

time-consuming mask required, suitable for

high production with stable code

SRAM Highest speed, high-power, low-density

-

EPROM

Electrically Programmable Read-

Only Memory

High-density memory; must be exposed to

ultraviolet light for erasure

EEPROM or E

2

Electrically Erasable Programmable

Read-Only Memory

Electrically byte-erasable; lower reliability,

higher cost, lowest density

DRAM

Dynamic Random Access Memory

High-density, low-cost, high-speed, high-

power


19/101

FLASH Full-Featured Memory Solution

EPROM

EEPROM

NonvolatileUpdatable

ROMDRAM

FLASH

High

Density


20/101

1. Memory: basic concepts

Stores large number of bits

m x n: m words of n bits each

k= Log2(m) address input signals

or m = 2k words

e.g., 4,096 x 8 memory:

32,768 bits

12 address input signals 8 input/output data signals

Memory access

r/w: selects read or write

enable: read or write only when asserted

multiport: multiple accesses to different locations simultaneously


21/101


A0 12 A10 112K A20 212M

A1

24 A11

124K A21

224M

A2 38 A12 138K A22 238M

A3 416 A13 1416K A23 2416M

kaddress signals 2k words

4 14 24

A5 664 A15 1664K A25 2664M

A6 7128 A16 17128K A26 27128M

A7 8256 A17 18256K A27 28256M

A8 9512 A18 19512K A28 29512MA9 101024 = 1K A19 201024K = 1M A29 301024M = 1G


22/101


24

= 165

2 = 326

112 = 204812

2 = 409613

2 = 819214

2 = 1638415

2 = 3276816

2 1 = 2

22

= 4

23

= 8

2 = 64

82 = 256

72 = 128

9

2 = 51210

2 = 1024

2 = 6553617

2 = 13107218

2 = 262144

302 = 1 X109

402 = 1 X1015

20

2 = 1 X106


23/101

m n memory

rds

enable2k n

r/w

memory external view


n bits per word

mw

rea an wr e

memory

A0

D0Dn-1

Ak-1


24/101

1. Memory Architecture

row

dec

bit-line conditioning

memory cells:

2 n-k rows x

bit-lines

word-lines

d

er

columndecoder

n

n-kk

2 m bits

column

circuitry

2 m+k columns


25/101

1. Array Architecture

2n words of 2m bits each

If n >> m, fold by 2k into fewer rows of more columns

Good regularity easy to design Very high density if good cells are used


26/101

ROM used for storing programs and constant tables

Conflicting requirements

non-volatility

(re)-programability

2. ROM: Read-Only Memory


27/101

2. ROM Types

EEPROM: E2PROM and FLASH E2PROM

charge on a floating gate

erased by electrical signal

(UV) EPROM

charge on a floating gate

OTP PROM

fusible nichrome/polysilicon links

programmed by blowing fuses

ROM

mask-programmed

Emulated ROM NVRAM RAM-with-a-battery


28/101

2.1 ROM: Read-Only Memory

Ninput bits (3) 2N words (8) by M bits (5)

Marbitrary functions (5) ofN variables (3): 8 words by 5 bits

A0

ROM

D4

8 words x 5 bitsA2

A1

D3 D0D1D2

Address

Data

Horizontal lines = words

Vertical lines = data


29/101


Ninput bits (3) 2N words (8) by M bits (5)

Marbitrary functions (5) ofN variables (3): 8 words by 5 bits

A

ROM3 Inputs

5 Outputs

F4

8 words x 5 bitsC

B

F 3 F0F1F2

Horizontal lines = words

Vertical lines = data


30/101


Three inputs:

address bits: 16

chip select

output enable

One output:

ROM

A0 A15

16

8

tristate data output

Access time (time from

stable address to stable

data) 450 ns - 70 ns

x ts

CS

OE

D7 D0


31/101

Memoria de slo lectura: ROM

La ROM es un conversor de cdigo

No es necesario almacenar los bits en flip-flops Se puede implementar a partir de circuitos combinatorios:

decodi icadores/codi icadores



32/101

D0A0

2.1 Memoria ROM: Read Only Memory

Diagrama a nivel de bloque: ROM

Dn-1An-1

CS OE


33/101

POSICIN DE DIRECCIN PALABRA DE DATOS

MEMORIA A2 A1 A0 D3 D2 D1 D0M0 0 0 0 0 1 0 0

M1 0 0 1 0 1 1 1


Tabla de verdad: ROM

M2 0 1 0 1 0 1 0M3 0 1 1 1 1 0 1

M4 1 0 0 0 0 1 0

M5 1 0 1 1 0 1 1M6 1 1 0 0 1 1 1

M7 1 1 1 0 1 0 0


34/101

Implementacin fsica: ROM


= )5,3,2(3 mf

= )6,5,3,1(0 mf


35/101

Arreglo de interconexin


CODIFICADORM0

D3 D2 D1 D0

M7

2 1 ROM 8 4 bi I l i


36/101

38

decoderA0

CSword 0

word 1

word line

word 2

2.1 ROM 8 x 4 bits: Internal view

A2

A1

programmableconnection wired-OR

data line

D0D3 D2 D1

2 1 M i ROM R d O l M


37/101


Codificador:

funcin OR de N entradas: diodos



38/101


Codificador:

funcin NOR de N entradas: transistores



39/101


Codificador ROM: Diodos

= )5,3,2(3 mf

= )6,5,3,1(0 mf



40/101


Codificador ROM: Transistores

2 1 Memoria ROM: Read Only Memory


41/101


Codificador ROM: Fusibles

2 1 Diagrama de bloques ROM: 64 x 8 bits


42/101

DECODIFICADORCOLUMNA

3A3-A5

2.1 Diagrama de bloques ROM: 64 x 8 bits

ARREGLO

8 x 8

8

DECODIFICADOR

F

ILA

3A0-A2

8D7 D0

2 1 Diagrama de bloques ROM: 8K x 8 bits


43/101

2.1 Diagrama de bloques ROM: 8K x 8 bits

20 AA 73 AA 128 AA

5

5

3225=

COLUMN

DECODER DRIVER

ADDRESS

BUFFERS

ADDRESS

BUFFERS

256 x 32

ARRAY OF 8

BIT WORDS

OUTPUT BUFFERS

07 DD

3 25628=

1CS CHIP SELECT

1st LEVEL

ROW

SELECT

2st

LEVEL

ROW

SELECT

8

2 2 Memoria EPROM EEPROM


44/101

2.2 Memoria EPROM-EEPROM

Codificador EPROM/EEPROM: Transistor puerta flotante

2 2 Memoria EPROM-EEPROM


45/101

source drain

floating gate


(a)

2 2 Memoria EPROM-EEPROM


46/101

(b)source drain

+15V

5-30 min


(d)

(c)source drain

2 2 2716 EPROM (2k x 8bits)


47/101

2.2 2716 EPROM (2k x 8bits)

OUTPUT ENABLECHIP ENABLE

AND PROG LOGIC

OUTPUT

BUFFERS

VCCGND

VPP

OECE/PGM

DATA OUTPUTS: D7 D0

Y

DECODER

X

DECODER

Y GATING

16, 384-BIT

CELL MATRIX

ADDRESSINPUTS:A0-A10

2.2 W28C64 EEPROM Simplified Block Diagram


48/101

Row

Address

Latches

Column

Address

Latches

A6-12

A0-5

Row

Address

Decoder

Column

Address

Decoder

64 Byte

Page

Buffer

E2

Memory Array

2.2 W28C64 EEPROM Simplified Block Diagram

TimerEdge

Detect &

Latches

ControlLatch

ControlLogic

CE

WE

OE

CLK

I/O Buffer/

Data Polling

I/O7-0

Latch Enable

PE RSTB VW

2.3 Memoria EEPROM Flash


49/101

floating gate

control gate

Wordline

Bitline

ONO

Tunnel oxide

2.3 Memoria EEPROM Flash

Figure 1: Flash memory cell

SourceN+

DrainN+

P-Substrate

2.3 EEPROM Flash memory cell


50/101

2.3 EEPROM Flash memory cell

BL AS

ES

R

Q1 Q2Q3

WL 1

Q1 MEMORY TRANSISTOR

Q2 PASS GATE (EACH 16 COLUMNS)

Q3 SECTOR SELECT (EACH 16 ROWS)

EVERY 16 ROWS 2K BYTES 1 SECTOR

WL 2

2.3 Flash EEPROM:Memory Map Diagram


51/101

y p g

128 Kbyte

128 Kbyte

128 Kbyte

Intel StrataFlashMemory

64 Kbyte

64 Kbyte

64 Kbyte

FlashFile Memory

64 Kbyte

64 Kbyte

8x8 Kbyte

Boot Block0H

1FFFFFH

0H

1FFFFFH

0H

128 Kbyte

128 Kbyte

128 Kbyte

128 Kbyte

Blocked

32 Mbit

Memory Map Diagram

Asymmetrical andSymmetrical Blocking

y Blocked32 Mbit

1FFFFFH

Symmetrically

Blocked128 Mbit

3.RAM: Random Access Memory


52/101

y

Random Access (Read-Write) Memory

RAM used for storage of transient objects

global and static variables in C

the stack (auto variables)

the heap (unallocated memory)

types

SRAM (Static RAM)

DRAM (Dynamic RAM)

3.1 SRAM: Static RAM


53/101

Bit storedas the state of aflip-flop

Selected by AND-ed inputs: address + CS + OE + R/W

Retains contents as long as power applied - no refresh

Access time 12 ns to 200 ns

Faster, but less dense than DRAM

: usua y attery ac e

3.1 SRAM: Static RAM


54/101

Static RAM technology Highest speed

< 10 ns

Density

~ 1 Mbits / chip (Lower for fastest devices)

Packaging

128k x 8 bit, 64k x 16 bit Access protocol

Simple:

Read: assert address (+ CE, R, OE), then read data

Write: assert address and data + CE, W

Pins

17bits address (128k) + 8 data = 25 + control

3.1 SRAM 32k x 8bits


55/101

SRAM

A0 A15

16

8

x ts

CS

OE

D7 D0R/W

3.1 SRAM Cell: 6-Transistors


56/101

word (row select) word

10

0 1

bit bit

bit bit

replaced with pullupto save area

3.1 Diagrama de bloques SRAM: 16K x 1 bits


57/101

60 AA 128 x 128

CELL

ARRAY

R

O

W

S

E

LE

C

T

COLUMN SELECT

137 AA

CS

W

OIData /

CS: CHIP SELECT

W = 1: READ

W = 0; WRITE

DI: DATA IN

DO: DATA OUT

3.1 6264 SRAM (8k x 8bits)


58/101

ADDRESSDECODER

128 X 128

MEMORYARRAY

A0

A10

Vcc

GND

INPUT

DATA

CIRCUIT

CONTROL

CIRCUIT

I/O CONTROLI/O0

I/O7

CSOE

WE

3.2 DRAM: Dynamic RAM


59/101

Each bit stored as a charge on a storage capacitor

Must be refreshed (write accessed) periodically - at

intervals typically less than 8 ms

ManyPs, all SIMMS have built-in refresh

ess power, enser, u s ower an

3.2 Dynamic RAM


60/101

Refresh

DRAM has one-transistor cells

Charge leaks from storage capacitor

Refresh interval ~ 1-4 ms

RAM unavailable during refresh!

bit

word

ome an w oss

Vdd

3.2 Classical DRAM Organization (Square)


61/101

DRAM Cell Array

bit (data) lines

Each intersection represents

a 1-T DRAM Cell

row

deco

Row and column address together:

Select 1 bit a time

rowaddress

ColumnAddress

data

wor row se ect

Column Selector & I/O

Circuits

d

er

3.2DRAM Block Diagram: 4 Mbits


62/101

Square root of bits per RAS/CAS

Column Decoder

Sense Amps & I/O

Data I/O

Memory Array

(2,048 x 2,048)

A0A10

Word Line

Storage

Cell

3.2 DRAM Memory Array


63/101

Row

driver

Row

driver

Rowadd

ressdeco

data/bit line

word line

.. .. ..

...

...

...

precharge BL decode row

discharge BL

Row

driver

er

Sense

Amplifier

Sense

Amplifier

Sense

Amplifier

Column address decoder and data multiplexer

Clock generator

Addressbu

ffer

. . .

...

...

RAS

CAS

W/R

address

Data I/O

column select

data > out

3.2 DRAM Memory


64/101

row col--- --- ---rowdata

acces cycle time

(a) random

access

mode

RAS

CAS

addressData out

an om access t me

Column address cycle time

(b) page

mode

RAS

CASaddress

Data out

row c1--- ---

d1

c2 --- c3 ---

d2 d3

3.2 DRAM Memory


65/101

RAS

CAS

(c) static column mode

---addressData out

r c1 c2 c3 c4 c5 c6 c7d1 d2 d3 d4 d5 d6 d7

3.2 Synchronous DRAM: SDRAM


66/101

READACT READ PRE ACT READ

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

clk

cmnd

introduce a clock (asynchronous => synchronous) pipelining

ROW COL COL ROW COL

da1 db1 db2 db3 db4 dc1

CAS latency

1/2/3 for 33/66/99 MHz

Hi-Z

bank

addr

data

Burst length =

1/2/4/8/full page



67/101

ROW COL COL ROW COL

WRITACT WRIT PRE ACT WRIT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15clk

cmndbank

addr

da1 db1 db2 db3 db4 dc1 dc3dc2

Hi-Zdata

Final goal = 1 access each clock cycle

banking

burst length large enough (e.g. 8)



68/101


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15clk

cmnd

bank

da1 db1 db2 db3 db4 dc1db5 db6 db7 db8

CAS latency

data



69/101


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15clk

cmnd

bank

db1 db2 db3 db4 dc1db5 db6 db7 db8 dc3dc2da1data

3.2 DRAM Memory


70/101

Dynamic RAM technology highest density

64-256 Mbits / chip

semiconductor memories of several Gbytes feasible packaging

64M x 1 bit

16M x 4 bit

reduced pin count

64x106 = 226

use 13 pins only

Row/Column multiplexing

Rowaddress

Columnaddress

13 13

3.2 DRAM Memory


71/101

Dynamic RAM technology

Row / Column multiplexing

Two cycles to access

Assert Row address

Assert Column address

Rowaddress

Columnaddress

13 13

26

DRAMAddress

13 Data

1 or 4Control

RAS CS R/W

3.2 Diagrama de Bloques: DRAM 64K x 4


72/101

RAS

256 x 256

ARRAY OF

4 BITS

ROW

DECODER

ROW

ADDRESS

LATCH M

REFRESHCIRCUITRY

CONTROL

SENSE WRITE

AMPLIFIERS

LBS

8 8

25628=

CS R/W

READ/WRITE

SELECTCHIP

/

WR

CS

STROBEADDRESSCOLUMN

STROBEADDRESSROW

CAS

RAS

MBS

1STEP

2STEP

COLUMN DECODERCOLUMN

ADDRESSLATCH

8

A0-7A8-15

CAS D I/O 0-3

25628=

OUTDATA

INDATA

DO

DI

3.2 Advanced DRAM


73/101

DRAMs commonly used as main memory in processorbased embedded systems

high capacity, low cost

Many variations of DRAMs proposed need to keep pace with processor speeds

EDO DRAM: extended data out DRAM

SDRAM/ESDRAM: synchronous and enhanced synchronous

DRAM

RDRAM: rambus DRAM

3.2 DRAMs per PC over Time


74/101

ySize

DRAM Generation86 89 92 96 99 02

1 Mb 4 Mb 16 Mb 64 Mb 256 Mb 1 Gb

4 MB

8 MB

32 8

16 4

MinimumMem

o

16 MB

32 MB

64 MB

128 MB

256 MB

8 2

4 1

8 2

4 1

8 2

4. Memory Arrays:


75/101

Bank A Bank B

row

column

15 ------------------8 7 ------------------------0

13

07 D

LSB

13ACS

012A A


76/101

D

AT

A

3 BITDECODER

07D

07 D

07 D

MSB

15

14

A

A

8Kbyte

CS

CS

CS

1

LI

N

E

S

07

D

07 D

07 D

07 D

ROM 64Kx8 usando ROMs 8Kx8

CS

CS

CS

CS

8

1

0

A

A WR/

7BIT 6BIT 0BITBIT14


77/101

M

13

2

A

A ADDRBIT14

ADDRESSBIT16

8 1

cs

77DODI

15

14

AA

SRAM 64Kx8

usando SRAMs 16Kx1

2 BIT

DECODER

cs

cs cs

cs

cs

00DODI66DODI

)0:12(

1

2

AOE

)0:7(DW

E

E

1

2

E

EOrganizacin 1-D

1


78/101

AG

G

2

1

5

6

7

Y

Y

Y138`

DECODER

)0:12(

1

A

OE

)0:7(DW

E

)0:12(

1

2

AOE

)0:7(DW

E

E

)0:12(

1

2

A

OE

)0:7(DW

E

E

de una memoria de64Kbyte usando

SRAMs de 8Kx8

ASEL

BSEL

CSEL

BG2

0

1

2

3

4

Y

Y

Y

Y

Y

13

14

15

READWRITE

)0:12(

1

2

A

OE)0:7(DW

E

E

)0:12(

1

2

A

OE

)0:7(DW

E

E

)0:12(

1

2

A

OE)0:7(DW

E

E

)0:12(

1

2

AOE

)0:7(DW

E

E

:

ADDR (12:0)

ADDR (15:13)

8

ADDR

ADDR

)15(

)16(

DECODER139

GBA


79/101

EN3

EN2

EN3

EN2

)0:12(

)0:7(

1

2

AOE

DW

E

E

3210 YYYY

1

2

E

E

)0:12(

)0:7(

1

2

AOE

DW

E

E

1

2

E

E

Organizacin 2-Dde una memoria de

64Kbyte usando

SRAMs de 8Kx8

1

ADDR

ADDR

)13(

)14(

ADDR )0:12(DATA )0:7(

EN1

EN0

EN1

EN0

DECODER

A

B

G

0

1

2

3

Y

Y

Y

Y139

READ

WRITE

)0:12(

:

A

OE

)0:12(

)0:7(

1

2

A

OE

DW

E

E

)0:12(

)0:7(

1

2

A

OE

DW

E

E

)0:12(

:

A

OE

)0:12(

)0:7(

1

2

A

OE

DW

E

E

)0:12(

)0:7(

1

2

A

OE

DW

E

E

8

0COL 1COL 2COL 3COL

CS

Organizacin de

una memoria

1Mx8 usando


80/101

ROW064K x 8 64K x 8

K 4642 RAS2

RAS1

RAS0DRAMs de64Kx4

ROW1

ROW2

64K x 8

CASWE

AA 0607

BI-DIRECTIONAL DATA BUS DATA 7-0

WE

RAS3

ADOUT 0 - 7

DRC

3

2

1

0

CAS

CASCASCAS

IN/OUTDATA

STROBEADDRESSCOLUMN

STROBEADDRESSROW

SELECTCHIP

/

ODI

CAS

RAS

CS

ROW3

DI/O8

DI/O

8DO

8DO

8

5.1 SRAM cell: CMOS cell


81/101

Bit-lines

Word-lineVDD

5.1 SRAM cell: RMOS cell


82/101

VDD

5.1 SRAM cell: CMOS single-ended cell


83/101

VDD

5.2 DRAM cell


84/101

VDD

b) DRAM self-refresh cell

VDD

a) DRAM cell

5.3 EEPROM cell


85/101

....

a) ROM cell b) EEPROM cell

5.4 NVRAM cell


86/101

VDD

M M

6. Write ability/ storage permanence

rage

ence


87/101

Batterylife (10

EPROM

Mask-programmed ROM

EEPROM FLASH

NVRAM

Sto

perman

Nonvolatile

Ideal memory

OTP ROM

Tens ofyears

Life ofproduct

Write ability and storage permanence of memories,

showing relative degrees along each axis (not to scale)

External

programmer

OR in-system,block-oriented

writes, 1,000s

of cycles

years)

Write ability

SRAM/DRAMIn-systemprogrammable

During

fabrication

only

External

programmer,

1,000sof cycles

External

programmer,

one time only

External

programmer

OR in-system,1,000s

of cycles

In-system, fast

writes,

unlimitedcycles

Nearzero

6. Memory Hierarchy

V i


88/101

ProcessorRegisters

On Chip

Cache

Local

Higher

Cost

10 ns

10 ns

20 ns

1

1

2

Various memorydevices are used in a

computer system

They have differentspeeds and costs

SecondaryCache

GlobalMemory

MassStorage

Slower

Access

Higher

Density

60 ns

100 ns

12 ms

3

10

1,200

DRAM

HDD

6. Cache Memory

T i bl


89/101

Two main problems: mismatch in speed between processor and main memory

contention for contents of shared memory, or for

switching, significantly increases latency

6. What is a Cache?

Hi h d d l t d t f it


90/101

High-speed memory module connected to a processor for itsprivate use

Contains copies of actively referenced material

Copied between cache & memory in lines or blocks

Caching works because of

temporal locality - repeated references to same memory in a small

time

spatial locality - references to nearby memory addresses in a small

time

6.Primary and Secondary

Primary cache is usually on the CPU chip for speed


91/101

Primary cache is usually on the CPU chip, for speed

Few tens of kbytes, very fast

May be separate data and instruction caches

Secondary cache is off-chip

Much larger (several Mbytes) than primary cache

Dynamic RAM - Access Time Myth

Data book Access Time : tRAC

= 100ns


92/101

RowAddAD0-12

ColumnAdd

RAC

/RAS

/CAS1990 data!

X 0.5 for today!

(a) random

access

Time between accesses: tRC = 190ns1990 Data: apply appropriate factor! (~0.5 for 1998)

tRACtRC

/OEDATA (out)

DATA (in)

mo e

Dynamic RAM - Improving Bandwidth

Bandwidth = overall data rate 1/tRC


93/101

Bandwidth = overall data rate 1/tRC tRC determined by

packaging (stray C, L, lead R, etc)

need to drive PCB traces

program size

the IBM/Microsoft complexity factor J

DRAM manufacturers

Go for size rather than speed!

Dynamic RAM

refresh circuitry adds complexity

halved in 8 years!


tRC

is difficult to reduce


94/101

RC

So increase amount of data per tRC

Page mode DRAMs

/RAS

/CAS

ValidData

ValidData

ValidData

RowAddAD0-12

ColumnAdd

tRACtRC

WRITE

/OE

DATA (out)

DATA (in)

ColumnAdd

ColumnAdd


Assert one row address then multiple column addresses


95/101

Assert one row address, then multiple column addresses Locality of reference - many accesses within a page

/RAS

/CAS

ValidData

ValidData

ValidData

RowAddAD0-12

ColumnAdd

tRACtRC

WRITE

/OE

DATA (in)

ColumnAdd

ColumnAdd

DATA (out)

Refresh

5. Dynamic RAM


96/101

Refresh DRAM has one-transistor cells

Charge leaks from

storage capacitor Refresh interval ~ 1-4 ms

bit

word

Some bandwidth loss

Vdd

Dynamic RAM - EDO?

EDO = Extended Data Out


97/101

EDO = Extended Data Out

Extends time for which data is held

Allows new column address to be applied while data is being

read

- mprovemen y s r n ng e ec ve cyc e me

SDRAM/SLDRAM - Just more acronyms?

Synchronous


98/101

Synchronous more constraints on the designer

everything must respond in time!

faster

less time wasted in REQ/GNT protocols

time slots for commands/data

Bursts data for high throughput

SLDRAM - Synchronous Link DRAM

memory access protocol

SLDRAM memory is a subsystem

Dynamic RAM - RAMBUS

Packet mode of operation


99/101

Packet mode of operation Request large bursts of bits in one access

250MHz clock

Data bit on each clock edge 500Mbits / second / pin!

su a e or grap cs

large blocks of data streamed from memory to device game machines!

Bit-lines

Word-lineVDD VDD


100/101

b) RMOS cella) CMOS cell

c) CMOS single-ended cell d) DRAM cell

VDD

VDD

VDD


101/101

f) ROM cell

e) DRAM self-refresh cell

g) EEPROM cell

....

h) NOVRAM cell

M M

DD

Memorias-I-OK.pdf

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