MELJUN CORTES Shift Register and Counter
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Transcript of MELJUN CORTES Shift Register and Counter
8/8/2019 MELJUN CORTES Shift Register and Counter
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Master clock generator synchronizes allsubsystems of a sequential circuit
Load ControlInput
Shift Register and Counter * Property of STI
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Load control input using the clock and theassociated timing diagram
Load ControlInput
Shift Register and Counter * Property of STI
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LOAD
the control signal that will determine whetherthe subsystem where the CLOCK is connected
to needs to function
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Load control input using the input X1
Load ControlInput
the figure shows how a logic 1 at the LOAD willallow the input X 1 to be processed bysubsystem A during each clock transition
Shift Register and Counter * Property of STI
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Register
a fli -flo structure that handles multi le bits of
Register andShift Registers
data at any one time called a 4-bit parallel register or buffer
register
used in most computers as high-speedtemporary data storage
Detailed implementation using flip-flops
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Register andShift Registers
schematic symbol
Shift Register and Counter * Property of STI
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implementation
another way of drawing the register using thesame set of flip-flops but written horizontally
simplifies the correspondence between the flip-flop’s outputs and the way the output is writtenfrom the least significant bit (LSB) to the most
significant bit (MSB)
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Register andShift Registers
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shows how optional inputs of flip-flops may beused
inputs: CLEAR and PRESET
modifies the state of the associated flip-flopinstantaneously
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the LOAD input dictates when the register mayallow data from its inputs to be transferred and
Parallel Registerwith Load Control
stored
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Parallel/buffer register with load control input
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capable of shifting or rotating the binaryinformation stored in the register
Shift Register
has the capability of shifting stored bits to theleft or to the right for every clock pulse
used in microcomputer serial communications to transfer information
Shift Register and Counter * Property of STI
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A simple shift-left and shift-right register using D
flip-flops
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Summary of the input and output of the shift register:
Initial state Q = 0000
Shift Register
= = =
2nd rising edge: Q = 0011 SERIAL IN = 1 SERIAL OUT = 0
3rd rising edge: Q = 0111 SERIAL IN = 1 SERIAL OUT = 0
4th rising edge: Q = 1111 SERIAL IN = 1 SERIAL OUT = 1
Successive rising edges: Q = 1111 SERIAL IN = 1 SERIAL OUT = 1
when the SERIAL IN=0, the output of the register:
Initial state Q = 1111
1st rising edge: Q = 1110 SERIAL IN = 0 SERIAL OUT = 12nd rising edge: Q = 1100 SERIAL IN = 0 SERIAL OUT = 1
3rd rising edge: Q = 1000 SERIAL IN = 0 SERIAL OUT = 1
4th rising edge: Q = 0000 SERIAL IN = 0 SERIAL OUT = 0
Successive rising edges: Q = 0000 SERIAL IN = 0 SERIAL OUT = 0
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er a oa ng
the method of storing a word of information
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When the stored data in the register is Q=1111 and
SERIAL IN=0 at all times, the output will be:
Shift Register
Initial state Q = 1111
1st rising edge: Q = 0111 SERIAL IN = 0
2nd rising edge: Q = 0011 SERIAL IN = 0
3rd rising edge: Q = 0001 SERIAL IN = 0
4th rising edge: Q = 0000 SERIAL IN = 0
Successive rising edges: Q = 0000 SERIAL IN = 0
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Example 1:
Get the out ut of the followin shift re ister
Shift Register
after with the following conditions:(a) shift-left, Q =0000, SERIAL IN sequence is
0,0,0,1,0,1,1; after 7 cycles
(b) shift-left, Q =00001111, SERIAL IN alternating 0
and 1; after 10 cycles
Solution:
(a) initial Q = 0000
cycle 1 Q = 0000 SERIAL IN = 0
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cyc e 2 = =
cycle 3 Q = 0000 SERIAL IN = 0cycle 4 Q = 0001 SERIAL IN = 1
cycle 5 Q = 0010 SERIAL IN = 0
cycle 6 Q = 0101 SERIAL IN = 1
cycle 7 Q = 1011 SERIAL IN = 1
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Solution (cont.):
Shift Register
(b) initial Q = 00001111
cycle 1 Q = 00011110 SERIAL IN = 0
cycle 2 Q = 00111101 SERIAL IN = 1
cycle 3 Q = 01111010 SERIAL IN = 0
cycle 4 Q = 11110101 SERIAL IN = 1
cycle 5 Q = 11101010 SERIAL IN = 0
cycle 6 Q = 11010101 SERIAL IN = 1
cycle 7 Q = 10101010 SERIAL IN = 0
cycle 8 Q = 01010101 SERIAL IN = 1
cycle 9 Q = 10101010 SERIAL IN = 0
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Example 2:
Desi n an alternative im lementation of the
Shift Register
shift-left register using JK flip-flops.
Solution:
The basic operation of the 4-bit shift (left)register that is made using D flip-flops is asfollows:
1. D 0 takes in new value from SERIAL IN
2. D 1 takes old value of D 0; D 2 takes D 3; etc.
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JK flip-flop’s function table:
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A 4-bit shift-left register using JK flip-flops
Shift Register
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gates and feedback are also used to allow forincreased control over the operation of the shift
Shift Registerswith Load Control
register
Shift register with load control input
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are essentially registers that go through asequence of states whenever input pulses are
Counters
applied can be used to measure time or frequency (and
period)
handle binary numbers and are called binarycounters
Two types of counters:
Synchronous
the flip-flops are timed using a common clockpulse
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each of the outputs of the flip-flops is used totrigger the other flip-flops
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a simple type of counter that is usuallyimplemented with T flip-flops or JK flip-flops
Ripple Counter
the inputs of the CLK are derived from theoutputs of the flip-flops used
A 3-bit ripple counter using JK flip-flops
A ripple counter using JK flip-flops:
1. The CLK is tri ered durin hi h-to-low lo ic
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transitions.
2. The flip-flop that corresponds to the LSB is theJK flip-flop that is directly connected to theinput. Each subsequent flip-flop corresponds toa higher bit.
3. Since the inputs J and K of all the flip-flops aretied together, each flip-flop will merely toggle
(negate its input) when triggered.
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Ripple Counter
A 3-bit ripple counter using T flip-flops
This figure shows how some authors want to
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MSB to the LSB.
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Ripple Counter
Timing diagram of the ripple counter
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Ripple counter counting sequence
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SynchronousCounters
Ring counter with pre-load pulse
resembles the shift register using D flip-flopswith the difference that the output from the MSBis fed back0 to the LSB input
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Ring Counter
the action of going back to the beginning
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SynchronousCounters
Sequence of states
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Using the D flip-flops to get the state equation
directly from the state table, follow the steps below:
SynchronousCounters
Step 1: Get the sum of minterms expression
D Q 2 (Q2, Q1, Q0 ) = Σ(3, 4, 5, 6)
D Q 1 (Q2, Q1, Q0 ) = Σ(1, 2, 5, 6)
D Q 0 (Q2, Q1, Q0 ) = Σ(0, 2, 4, 6)
Step 2: Simplify using K-map method
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Step 2: Simplify using K-map method (cont.)
SynchronousCounters
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The simplified equation:
D = Q ’Q Q + Q Q ’ + Q Q ’
SynchronousCounters
D Q 1 = Q 1’Q 0 + Q 1Q 0’
D Q 0 = Q 0’
Step 3: Draw the logic diagram
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