Mechatronics Lab Manual MultSim PLC Ladder Simulation Circuits Diploma Mechanical Karnataka

MECHATRONICS LAB MANUAL

INTRODUCTION TO MECHATRONICS

Mechatronics is defined as the interdisciplinary field of engineering and design methodology. It deals with the design of products whose function relies on the integration of mechanical, electrical and electronics components connected by a control scheme. Mechatronics is a system–level approach to designing electro-mechanical systems that merges mechanical, electrical, control system and embedded software design. Mechatronics plays an important role in the design manufacturing and maintenance of a wide range of engineering products and process. Mechatronics provides solutions that are efficient and reliable systems. Introduction to the Multisim Interface Multisim is the schematic capture and simulation application of National Instruments Circuit Design Suite, a suite of EDA (Electronics Design Automation) tools that assists you in carrying out the major steps in the circuit design flow. Multisim is designed for schematic entry, simulation, and feeding to downstage steps, such as PCB layout.

Multisim’s user interface consists of the following basic elements:

• Menus are where you find commands for all functions. • The Standard toolbarcontains buttons for commonly-performed functions • The Simulation toolbar contains buttons for starting, stopping , and other simulation functions • The Instruments toolbar contains buttons for each instrument. • The Component toolbarcontains buttons that let you select components from the Mutisim databases

for placement in your schematic.

DEPARTMENT OF MECHANICAL ENGG, MSRP


• The Circuit Window (or workspace) is where you build your circuit designs. • The Design Toolbox lets you navigate through the different types of files in a project (schematics,

PCBs, reports), view a schematic’s hierarchy and show or hide different layers.

Standard Toolbar The Standard toolbar contains buttons for commonly performed functions. Its buttons are described below:

• New: Creates a new circuit file.

• Open: Opens an existing circuit file. • Open Sample: Opens a folder containing sample and getting started files. • Save: Saves the active circuit. • Print Circuit: Prints the active circuit. • Print Preview: Previews the circuit as it will be printed. • Cut: Removes the selected elements and places them on the Windows clipboard. • Copy: Copies the selected elements and places them on the Windows clipboard. • Paste: Inserts the contents of the Windows clipboard at the cursor location. • Undo: Undoes the most recently performed action. • Redo: Redoes the most recently performed undo.

Simulation Toolbar The Simulation toolbar contains buttons used during simulation.

• Run/resume simulation: Starts/resumes simulation of the active circuit. • Pause simulation: Pauses simulation. • Stop simulation: Stops the simulation. • Pause at Next MCU Instruction Boundary: For use with the Multisim MCU Module. • Step Into: For use with the Multisim MCU Module. • Step Over button: For use with the Multisim MCU Module. • Step Out button: For use with the Multisim MCU Module. • Run to Cursor: For use with the Multisim MCU Module. • Toggle Breakpoint: For use with the Multisim MCU Module. • Remove All Breakpoints: For use with the Multisim MCU Module.

View Toolbar The buttons in the View toolbar are described below:

• Toggle Full Screen: Displays only the workspace, with no toolbars or menu items. • Increase Zoom: Magnifies the active circuit.



• Decrease Zoom: Decreases the magnification of the active circuit. • Zoom Area: Drag the cursor to select an area on the workspace to magnify. • Zoom Fit to Page: Shows the entire circuit in the workspace.

Components Toolbar The buttons in the Components toolbar are described below. Each button will launch the place component browser (Select a Component browser) with the group specified on the button pre-selected.

• Source: Selects the Source components group in the browser. • Basic: Selects the Basic components group in the browser. • Diode: Selects the Diode components group in the browser. • Transistor: Selects the Transistor components group in the browser. • Analog: Selects the Analog components group in the browser. • TTL(Transistor Transistor logic): Selects the TTL components group in the browser. • CMOS: Selects the CMOS component group in the browser. • Miscellaneous Digital: Selects the Miscellaneous Digital component group in the browser. • Mixed: Selects the Mixed component group in the browser. • Power Components: Selects the Power component group in the browser. • Indicator: Selects the Indicator component group in the browser. • Miscellaneous: Selects the Miscellaneous component group in the browser. • Electromechanical: Selects the Electromechanical component group in the browser. • RF: Selects the RF component group in the browser. • Place Advanced Peripherals: Selects the Advanced Peripherals component group in the browser. • Place MCU Module:Selects the MCU Module component group in the browser.

INTRODUCTION TO DIGITAL LOGIC GATES

Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function. The types of basic gates available are the OR, AND, NOT, NAND, NOR, EXCLUSIVE-OR, EXCLUSIVE- NOR. Except for the exclusive-NOR gate, other gates are available in monolithic integrated circuit form.

The gate is a digital circuit with one or more input voltages but only one output voltage.By connecting the different gates in differentways, we can build circuits that perform arithmetic and other functions associated with the human brain because they simulate mental process.The operation of a logic gate can be easily understood with the help of “TRUTH TABLE”.A truth table is a table that shows all the input-output possibilities of a logic circuit .i.e, the truth table indicates the outputs for different possibilities of the inputs.



1.BASIC LOGIC GATES

1(a)OR GATE Aim: Design &Simulate a logic circuit of OR gate Components used:OR gate(7432N),2 clock voltage,2dig probe bulb,1dig probe green bulb,2DGND Theory: The OR gate performs logical addition,more commonly known as the ‘OR’ function. An OR gate has two or more inputs and one output as indicated by the standard logic symbol as shown in fig Procedure:

• Open Multisim,click on file, select new-schematic capture. • Click on ‘Place’,click Component, select aComponent window opens & select the following

Select TTL,74STD,OR gate(74s32) & click ok. Pick and place the OR gate on the screen. Select Sources, Signal Sources,Clock voltage & click ok. Place 2 clock voltages on the screen(for 2 inputs). Select Sources, Power source,DGND( ground)& click ok. Place 2 DGND on the screen(for 2 inputs). Select Indicators,Probe, Dig Probe, Red indicator bulb & click ok. Place 2 Dig Probe Red bulb on the screen.(for 2 inputs). Select Indicators, Probe,Dig probe Green indicator bulb & click ok. Place 1 Dig Probe Green bulb on the screen.(for 1 output).

• Now join the circuit as shown in fig. • Run/Simulate the circuit using simulation bar.

Result:Design of logic circuit of OR gate is completed.Simulation of logic circuit OR gate satisfies the truth table.

LOGIC CIRCUIT - OR

BOOLEAN EQUATION A+B=Y LOGIC SYMBOL TRUTH TABLE

U1A

7432N

V14 Hz 5 V

V23 Hz 5 V

GND GND

2.5 V 2.5 V Y

2.5 V

GND GND

12 3

7432N

INPUTS OUTPUT A B Y 0 0 0 0 1 1 1 0 1 1 1 1



1(b) AND GATE

Aim: Design &simulate a logic circuit of OR gate Components used: ANDgate (7408J), 2 clock voltage, 2dig probe red bulbs, 1dig probe green bulb, 2DGND Theory: The AND gate performs logical multiplication, more commonly known as the AND function. The AND gate may have two or more inputs and a single output, as indicated by the standard logic symbols shown in the fig. Procedure:

• Open Multisim,click on file, select new-schematic capture. • Click on Place,click Component, select aComponent window opens & select the following

Select TTL,74STD,ANDgate(7408J) & click ok. Place the AND gate on the screen. Select Sources, Signal, sources, Clock voltage & click ok. Place 2 Clock voltages on the screen(for 2 inputs). Select Sources, Power source,DGND & click ok. Place 2 DGND on the screen(for 2 inputs). Select Indicators,Probe,Dig probe red bulb & click ok. Place 2 dig probe red bulb on the screen.(for 2 inputs). Select Indicators, Probe, Dig probe green bulb & click ok. Place 1 dig probe green bulb on the screen.(for 1 output).


Result:Design of logic circuit of AND gate is completed.Simulation of logic circuitAND gate satisfies the truth table.

LOGIC CIRCUIT - AND

BOOLEAN EQUATION TRUTH TABLE A.B=Y LOGIC SYMBOL

V14 Hz 5 V

V23 Hz 5 V

GND GND

2.5 V 2.5 V Y

2.5 V

GND GND

U1A

7408J1 2

3

7408N




1(c) NOT GATE

Aim: Design & Simulate a logic circuit of NOT gate Components used: NOTgate (7404N),2 clock voltage,2Dig probe red bulbs,1Dig probe green bulb,2DGND Theory: A NOT gate produces an output that is a complement of the input. It has only one input signal and one output signal as indicated by the logic symbol as shown in fig. Procedure:

• Open Multisim, click on file, select new-schematic capture. • Click on Place, clickComponent, selecta Component window opens & select the following

Select TTL, 74STD, NOT gate(7404N) & click ok. Place the NOT gate on the screen. Select Sources, Signal Sources,Clock voltage & click ok. Place 1 clock voltages on the screen(for 1inputs). Select Sources, Power source,DGND & click ok. Place 1 DGND on the screen (for 1 input). Select Indicators,Probe,Dig probe red bulb & click ok. Place 1 dig probe red bulb on the screen. (for 1 inputs). Select Indicators, Probe, Dig probe green bulb & click ok. Place 1 dig probe green bulb on the screen.(for 1 output).


Result:Design of logic circuit of NOT gate is completed.Simulation of logic circuitNOT gate satisfies the truth table.

LOGIC CIRCUIT -NOT

BOOLEAN EQUATION 𝑨𝑨 = Y LOGIC SYMBOL TRUTH TABLE

V23 Hz 5 V

GND

2.5 V Y

2.5 V

GND

U2A

7405N

41

7404NINPUTS OUTPUT

A Y 0 1 1 0



1(d) NOR GATE Aim: Design &Simulate a logic circuit of NOR gate Components used:NOR gate(7402N),2 clock voltage,2dig probe red bulbs,1dig probe green bulb,2DGND Theory: The term NOR is a contraction of NOT-OR and implies an OR function with an inverted (compliment) output.A standard logic symbol for two inputs NOR gate is as shown in fig. Procedure:

• Open Multisim, click on file, select new-schematic capture. • Click on Place, click Component, select a Component window opens & select the following

Select TTL,74STD,NOR gate(7402N) & click ok. Place the NOR gate on the screen. Select Sources, Signal sources, Clock voltage & click ok. Place 2 clock voltages on the screen(for 2 inputs). Select Sources, Power source,DGND & click ok. Place 2 DGND on the screen(for 2 inputs). Select Indicators,Probe,Dig probe red bulb & click ok. Place 2 dig probe red bulb on the screen (for 2 inputs). Select Indicators,probe, Dig probe green bulb & click ok. Place 1 dig probe green bulb on the screen.(for 1 output).


Result: • Design of logic circuit of NOR gate is completed.Simulation of logic circuitNOR gate satisfiesthe truth table.

LOGIC CIRCUIT -NOR

BOOLEAN EQUATION TRUTH TABLE 𝐴𝐴 + 𝐵𝐵=Y LOGIC SYMBOL

V14 Hz 5 V

V23 Hz 5 V

GND GND

2.5 V 2.5 V Y

2.5 V

GND GND

U1A

7402N1 2

3

7402N




1(e) NAND GATE

Aim: Design & Simulate a logic circuit of NAND gate Components used:NANDgate(7400N),2 Clock voltage, 2Dig probe red bulbs,1Dig probe green bulb,2DGND Theory: The term NAND is a contraction of NOT-AND and implies an AND function with a complement (inverted) output. A standard logic symbol for 2-input NAND gate is as shown in fig. Procedure:

• Open Multisim, Click on file, select new-schematic capture. • Click on Place, click Component, select a Component window opens & select the following

Select TTL,74STD,NANDgate(7400N) & click ok. Place the NAND gate on the screen. Select Sources, Signal sources, Clock voltage & click ok. Place 2 clock voltages on the screen(for 2 inputs). Select Sources, Power source,DGND & click ok. Place 2 DGND on the screen(for 2 inputs). Select Indicators,Probe,Dig probe red bulb & click ok. Place 2 dig probe red bulb on the screen.(for 2 inputs). Select Indicators, Probe, Dig probe green bulb & click ok. Place 1 dig probe green bulb on the screen.(for 1 output).


Result: • Design of logic circuit of NAND gate is completed.Simulation of logic circuitNAND gate satisfies the truth table.

LOGIC CIRCUIT

BOOLEAN EQUATION TRUTH TABLE 𝐴𝐴.𝐵𝐵=Y LOGIC SYMBOL

V14 Hz 5 V

V23 Hz 5 V

GND GND

2.5 V 2.5 V Y

2.5 V

GND GND

U1A

7400N1 2

3

7400N




1(f) X-OR GATE

Aim: Design &Simulate a logic circuit of X-OR gate Components used:X-OR gate(7432N), 2 Clock voltage, 2Dig probe red bulbs, 1Dig probe green bulb,2DGND Theory: The X-OR is an abbreviation for Exclusive-OR gate. An X-OR gate has two or more inputs and one output as indicated by the standard logic symbol as shown in fig. Procedure:

• Open Multisim,click on file, select new-schematic capture. • Click on Place,click Component, select a Component window opens & select the following

Select TTL,74STD,X-OR gate(7486N) & click ok. Place the OR gate on the screen. Select Sources,signal sources, Clock voltage & click ok. Place 2 clock voltages on the screen(for 2 inputs). Select Sources, Power source,DGND & click ok. Place 2 DGND on the screen(for 2 inputs). Select Indicators,Probe,Dig probe red bulb & click ok. Place 2 dig probe red bulb on the screen.(for 2 inputs). Select Indicators,probe,dig probe green bulb & click ok. Place 1 dig probe green bulb on the screen.(for 1 output).


Result: • Design of logic circuit of X-OR gate is completed.Simulation of logic circuitX-OR gate satisfies the truth table.

LOGIC CIRCUIT

BOOLEAN EQUATION 𝐴𝐴⊕ 𝐵𝐵 =Y LOGIC SYMBOL TRUTH TABLE

V14 Hz 5 V

V23 Hz 5 V

GND GND

2.5 V 2.5 V Y

2.5 V

GND GND

U1A

7486N1 2

3

7486NINPUTS OUTPUT

A B Y 0 0 0 0 1 1 1 0 1 1 1 0



1(g)X-NOR GATE

Aim: Design &Simulate a logic circuit of X-NOR gate Components used:XOR gate(7486N),NOT gate(7405N),2 clock voltage,2dig probe red bulbs,1dig probe green bulb,2DGND Theory: An Exclusive-NOR(X-NOR) gate is a coincidence gate. It produces one output only when its two inputs are equal, i.e., when both inputs are either zero or one. Procedure:

• Open Multisim,click on file, select new-schematic capture. • Click on Place,click Component, select a component window opens & select the following

Select TTL,74STD,X-OR gate(7486N),NOT(7405N)& click ok. Place the X-OR gate, NOT gate on the screen. Select Sources, Signal sources, Clock voltage & click ok. Place 2 clock voltages on the screen(for 2 inputs). Select Sources, Power source,DGND & click ok. Place 2 DGND on the screen(for 2 inputs). Select Indicators,Probe,Dig probe red bulb & click ok. Place 2 dig probe red bulb on the screen.(for 2 inputs). Select Indicators,probe, Dig probe green bulb & click ok. Place 1 dig probe green bulb on the screen.(for 1 output).


Result: • Design of logic circuit of X-NOR gate is completed.Simulation of logic circuit X-NOR satisfies the truth table.

LOGIC CIRCUIT

BOOLEAN EQUATION 𝐴𝐴⊕ 𝐵𝐵=Y LOGIC SYMBOL TRUTH TABLE

V14 Hz 5 V

V23 Hz 5 V

GND GND

2.5 V 2.5 V Y

2.5 V

GND GND

U1A

7486N1 2

U2A

7405N

3 4

7486N 7404NINPUTS OUTPUT

A B Y 0 0 1 0 1 0 1 0 0 1 1 1



2.DEMORGAN’S THEOREM

2(a) DEMORGAN’S FIRST THEOREM Aim: Design & Simulate a logic circuit of Demorgan’s first theorem. Components used: One NOR gate(7402N), two NOT gate(7404N),one AND gate(7408J),4 clock voltage,4 dig probe red bulb,2 dig probe green bulb,4DGND Theory: Demorgan’s first theorem states that “The compliment of a sum is equal to the product of individual compliments”. Procedure:

• Open Multisim,click on file, select new-schematic capture. • Click on Place, click Component, select a Component window opens & perform the following

Place NOR gate(7402N),2 clock voltage voltages,2 DGND,2 dig probe red bulb & one dig probe green bulb on the screen.

Join the circuit as according to the equation 𝐴𝐴 + 𝐵𝐵. Place 2 NOTgates(7404N),one AND gate(7408J),2 clock voltages,2DGND,2 dig probe red bulbs & one dig

probe green bulb on the screen. Join the circuit as according to the equation 𝑨𝑨.𝑩𝑩 .

• Run/Simulate the circuit. Result:

• Design of logic circuit of 𝐴𝐴 + 𝐵𝐵=𝐴.𝐵𝐵 is completed.Simulation of logic circuit satisfies the truth table shown.

LOGIC CIRCUIT

BOOLEAN EQUATION 𝐴𝐴 + 𝐵𝐵=𝐴.𝐵𝐵 LOGIC SYMBOL TRUTH TABLE

U1

NOR2

V12 Hz 5 V

V23 Hz 5 V

GND GND

X1

2.5 V

X2

2.5 V

GND GND

12

X3

2.5 V

3

U2

NOT

U3

NOT

U4

AND2

V32 Hz 5 V

V43 Hz 5 V

GND GND

2.5 V

X5

2.5 V

X6

2.5 V4

5

GND GND

67 8

U5

NOR2

NOT

U7

NOT

U8

AND2109

= INPUTS OUTPUT A B 𝑨𝑨 + 𝑩𝑩 𝑨𝑨.𝑩𝑩 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0



2(b) DEMORGAN’S SECOND THEOREM Aim: Design & Simulate a logic circuit of Demorgan’s second theorem. Components used: One NAND gate(7400N), two NOT gate(7404N),one OR gate(7432N),4 clock voltage,4 dig probe red bulb,2 dig probe green bulb,4DGND Theory: Demorgan’s second theorem states that “The compliment of a product is equal to the sum of individual compliments”. Procedure:


Place One NAND gate(7400N), 2 clock voltage voltages, 2 DGND, 2 dig probe red bulb & one dig probe green bulb on the screen.

Join the circuit as according to the equation 𝐴𝐴.𝐵𝐵. Place 2 NOT gates(7404N), one OR gate(7432N), 2 clock voltages, 2DGND,2 dig probe red bulb,& one dig

probe green bulb on the screen. Join the circuit as according to the equation 𝑨𝑨+𝑩𝑩 .

• Run/Simulate the circuit. Result:

• Design of logic circuit of 𝐴𝐴.𝐵𝐵=𝑨𝑨+𝑩𝑩 . is completed .Simulation of logic circuit satisfies the truth table shown.

LOGIC CIRCUIT

BOOLEAN EQUATION TRUTH TABLE 𝐴𝐴.𝐵𝐵=𝐴+𝐵𝐵 LOGIC SYMBOL

V12 Hz 5 V

V23 Hz 5 V

GND GND

X1

2.5 V

X2

2.5 V

GND GND

X3

2.5 VU2

NOT

U3

NOTV32 Hz 5 V

V43 Hz 5 V

GND GND

2.5 V

X5

2.5 V

X6

2.5 V4

5

GND GND

U1

NAND2

U9

OR2

12

3 67 8

U4

NAND2=

NOT

U6

NOT

U7

OR21211

INPUTS OUTPUT A B 𝑨𝑨.𝑩𝑩 𝑨𝑨+𝑩𝑩 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0



3.COMBINATION OF GATES

3(a) HALF ADDER Aim: Design & Simulate a logic circuit of half adder. Components used: One XOR gate(7486N), one AND gate(7408J),2 clock voltage,2 dig probe red bulb,2 dig probe green bulb,2 DGND Theory: The half adder circuit adds two binary digits & produces a sum(∑) & a carry output(Co).In other words, the binary arithmetic operation (A+B) produces(∑) . Procedure:

• Open Multisim,click on file, select new-schematic capture. • Click on Place, click Component, select a component window opens & perform the following

Place XOR gate(7486N), one AND gate(7408J),2 clock voltage,2 dig probe red bulb,2 dig probe green bulb,2 DGND on the screen.

Join the circuit as shown in fig. • Run/Simulate the circuit.

Result: • Design of logic circuit of half adder is completed & is as shown in fig.Simulation of logic circuit satisfies the truth table.

LOGIC CIRCUIT

BOOLEAN EQUATION: Sum(∑)=𝐴B+A𝐵𝐵= 𝐴𝐴⊕ 𝐵𝐵 Carry output(Co)=A.B LOGIC SYMBOL TRUTH TABLE A

HALF ADDER

∑(Sum)

B

CO(Carry Output)

U1A

7486N

U2A

7408J

V12 Hz 5 V

V23 Hz 5 V

GND GND

2.5 V 2.5 V 2.5 V1

2 3

X4

2.5 V

4

GND GND

INPUTS OUTPUT A B CO SUM 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0



3(b) FULL ADDER

Aim: Design & Simulate a logic circuit of full adder. Components used: 2 XOR gate(7486N), 2 AND gate(7408J),one OR gate(7132N),3 clock voltage,3 dig probe red bulb,2 dig probe green bulb,3 DGND Theory: The full adder adds the bits A & B &Carry(Ci) from the previous column.It generates a sum (∑) and a Carry output(CO).The basic difference between a full adder & a half adder is that the full adder accepts an additional input. Procedure:


Place X-OR gate(7486N), one AND gate(7408J),2 clock voltage,2 dig probe red bulbs,2 dig probe green bulbs,2 DGND on the screen.


Result: • Design of logic circuit of full adder is completed & is as shown in fig.Simulation of logic circuit satisfies the truth table.

LOGIC CIRCUIT

BOOLEAN EQUATION: LOGIC SYMBOL Sum(∑)= (𝐴𝐴⊕𝐵𝐵) ⊕𝐶𝐶𝐶𝐶 Carry output(Co)=(𝐴𝐴⊕ 𝐵𝐵)𝐶𝐶𝐶𝐶 + AB TRUTH TABLE

U1A

7486N

U1B

7486N

U2A

7408N

U2B

7408N

V12 Hz 5 V

V24 Hz 5 V

V36 Hz 5 V

GND GND GND

U3A

7432N

2.5 V 2.5 V 2.5 V 2.5 V

CO

2.5 V

4

5

6

32

1 7

8

GND GND GND

Ci FULL ADDER

∑(Sum) A

B

CO(Carry Output)

INPUTS OUTPUT

A B Ci CO SUM 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1



3(c) HALF SUBTRACTOR

Aim: Design & Simulate a logic circuit of half subractor. Components used: One X-OR gate(7486N), one AND gate(7408J),one NOT gate(7404N),2 clock voltage,2 dig probe red bulb,2 dig probe green bulb,2 DGND Theory: A half Subtractor is an arithmetic circuit that subtracts one bit from another bit, producing a difference bit(D) and borrow bit(Bo). Procedure:


Place one X-OR gate(7486N), one AND gate(7408J), one NOT gate(7404N),2 clock voltage,2 dig probe red bulb,2 dig probe green bulb,2 DGND on the screen.


Result: • Design of logic circuit of half subtractor is completed. Simulation of logic circuit satisfies the truth table shown.

LOGIC CIRCUIT

BOOLEAN EQUATION: LOGIC SYMBOL Difference(D)=𝐴B+A𝐵𝐵=𝐴𝐴⊕𝐵𝐵 Borrow(Bo)=𝐴.B TRUTH TABLE

INPUTS OUTPUT A B D BO 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0

U1A

7486N

U2A

7408N

U3A

7404N

GND GND

V12 Hz 5 V

V23 Hz 5 V

2.5 V 2.5 V

D

2.5 V

BO

2.5 V3

12 4

5

GND GND

A HALF

SUBRACTOR

D(DIFF) B

Bo(BORROW)



3(d) FULL SUBTRACTOR Aim: Design & Simulate a logic circuit of full subtractor. Components used: One X-OR gate(7486N), one AND gate(7408J),one NOT gate(7404N),2 clock voltage,2 dig probe red bulb,2 dig probe green bulb,2 DGND Theory: It is an arithmetic circuit that subtracts one bit (subtrahend) from another bit(minuend) taking into consideration the borrow(Bo) from the column. It produces a difference bit (D) and a borrow bit (Bo) required for the next higher column. Procedure:

• Open Multisim, click on file, select new-schematic capture. • Click on Place, clickComponent, select a Component window opens & perform the following

Place one X-OR gate(7486N), one AND gate(7408J), one NOT gate(7404N),2 clock voltage,2 dig probe red bulb,2 dig probe green bulb,2 DGND on the screen.


Result: • Design of logic circuit of fullsubtractor is completed.Simulation of logic circuit satisfies the truth table shown.

LOGIC CIRCUIT

BOOLEAN EQUATION: LOGIC SYMBOL Difference(D)=(𝐴𝐴⊕ 𝐵𝐵) ⊕𝐵𝐵𝐶𝐶 Borrow out(Bo)= (𝐴𝐴⊕ 𝐵𝐵)𝐵𝐵𝐶𝐶 + 𝐴𝐵𝐵 TRUTH TABLE

INPUTS OUTPUT A B Bi D Bo 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

U1A

7486N

U2A

7408N

U3A

7404N

U4A

7486N

U5A

7408N

U6A

7404N

U7A

7432N

V15 Hz 5 V

V24 Hz 5 V

GND GND

2.5 V 2.5 VD

2.5 V

Bo

2.5 V

3

V33 Hz 5 V

GND

2.5 V

7

8

9

10

21

GND GND GND

4

116

Bi FULL

SUBTRACTOR

D A

B

Bo



4.DECODERS & ENCODERS 4(a) 2-4 DECODER

Aim: Design & Simulate a logic circuit of 2-4 decoders. Components used: Four AND gate(7408J), two NOT gate(7404N),2 clock voltage, 2 dig probe red bulb,4 dig probe green bulb,2 DGND Theory: A decoder is a logic circuit that looks at its inputs, determines which number is there and activates the one output that corresponds to that number.2-4 decoders are used where a decoder has two input lines and four output lines. It takes a two bit binary number and activates any one of the four outputs corresponding to that number. Procedure:

• Open Multisim, click on file, select new-schematic capture. • Click on Place, clickComponent,select a Component window opens & perform the following

Place Four AND gate(7408J), two NOT gate(7404N), 2 clock voltage, 2 dig probe red bulb,4 dig probe green bulb, 2 DGND on the screen.


Result: • Design of logic circuit of 2-4 decoder is completed. Simulation of logic circuit satisfies the truth table shown.

LOGIC CIRCUIT

TRUTH TABLE

INPUTS OUTPUTS A B D0 D1 D2 D3 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 0 0 0 1

U1A

7404N

U1B

7404N

U2A

7408J

U2B

7408J

U2C

7408J

U2D

7408J

V12 Hz 5 V

V23 Hz 5 V

GND GND

B

2.5 V

A

2.5 V

2.5 V

D2

2.5 V

D1

2.5 V

D0

2.5 V

GND GND

5

6

7

8

1

9

3

2



4(b) 3-8 DECODER Aim: Design & Simulate a logic circuit of 3-8 decoder. Components used: Eight AND gate(7408J), three NOT gate(7404N), 3 clock voltage, 3 dig probe red bulb,8 dig probe green bulb, 3 DGND Theory: A decoder is a logic circuit that looks at its inputs, determines which number is there, and activates the output that corresponds to that number.3-8 decoders are used where a decoder has three input lines and eight output lines. It takes a three bit binary number and activates any one of the eight outputs corresponding to that number. Procedure:

• Open Multisim, click on file, select new-schematic capture. • Click on Place, click Component,select aComponent window opens & perform the following

Place eight AND gate(7408J), three NOT gate(7404N), 3 clock voltage, 3 dig probe red bulb,8 dig probe green bulb, 3 DGND on the screen.


Result: • Design of logic circuit of 3-8 decoder is completed.Simulation of logic circuit satisfies the truth table shown.

LOGIC CIRCUIT

TRUTH TABLE

A B C D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

U1A

74S11DU1B

74S11D

U1C

74S11D

U2A

74S11D

U2B

74S11D

U2C

74S11D

U3A

74S11D

U4A

74S11D

U5A

7404N

U5B

7404N

U5C

7404N

2

3

V12 Hz 5 V

V24 Hz 5 V

V36 Hz 5 V

GND

GND

GND

X1

2.5 V

X2

2.5 V

X3

2.5 V

2.5 V

X6

2.5 V

X7

2.5 V

X8

2.5 V

X9

2.5 V

X10

2.5 V

X11

2.5 V

GND

4

GND

GND

5

8

9

10

11

12

13

X5

2.5 V

14

1

7 15



4(c) 8-3 ENCODER

Aim: Design & Simulate a logic circuit of 8-3 encoder. Components used: Nine OR gate(7432N), 8 clock voltage, 8 dig probe red bulb,3 dig probe green bulb, 8 DGND Theory: Encoder is a device or a circuit that converts information from one format or code to another.input=2n and output = n. They are combinational logic circuits that are exactly opposite to decoder Encoder perform exactly reverse of decoder. 8-3 encoders are used where aencoder has eight input lines and three output lines. It takes aneight bit binary number and activates any one of the three outputs corresponding to that number. Procedure:

• Open Multisim, click on file, select new-schematic capture.• Click on Place, click Component, select a Component window opens & perform the following

Place Nine OR gate(7432N), 8 clock voltage, 8 dig probe red bulb,3 dig probe green bulb, 8 DGND on thescreen.

Join the circuit as shown in fig.• Run/Simulate the circuit.

Result: • Design of logic circuit of 8-3 encoder is completed.Simulation of logic circuit satisfies the truth table shown.

LOGIC CIRCUIT

TRUTH TABLE

EQUATION

A1=I1+I3+I5+I7

A2=I2+I3+I6+I7

A3=I4+I5+I6+I7

U1A

7432N U2B

7432NU3C

7432NU4B

7432NU5B

7432NU6C

7432NU7D

7432N

U8D

7432N

U9C

7432N

V15 Hz 5 V

V26 Hz 5 V

V32 Hz 5 V

V47 Hz 5 V

V54 Hz 5 V

V63 Hz 5 V

V71 Hz 5 V

V88 Hz 5 V

GND

GND

GND

GND

GND

GND

GND

GNDX1

2.5 V

X2

2.5 VX3

2.5 V

X4

2.5 VX5

2.5 V

X6

2.5 V

X7

2.5 V

2.5 V

X9

2.5 V

X10

2.5 V

X11

2.5 V

GND

GND

GND

GND

GND

GND

GND

GND

1

9

10

11

12

13

14

15

16

17

2

3

4

5

6

78

INPUT OUTPUT

L0 L1 L2 L3 L4 L5 L6 L7 A1 A2 A3

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1



5.OSCILLATOR

Aim: Design & Simulate a logic circuit of simple oscillator. Components used: 2-NANDgate(7437),2-Resistor(300M Ω)capacitor(120P),one Dig green bulb,Clock voltage,DGND. Theory: Oscillator is a circuit that produces repetitive electronic signal often sine or square wave used as clock signal to regulate computer or quartz clock. Suppose the initial output at level 1 is (v2), then the input must therefore beat level 0 as which will be the output from 1st NAND gate (v1) capacitor C is connected between the (v2) output and its input device timing resistor r2, capacitor now charges up at a rate determined by the time constant r2 and capacitor c charges up the function between r2 and c decreases until the lower threshold valve of v1 is reached. Procedure:

• Open Multisim, click on file, select new-schematic capture.• Click on place, click Component, select a Componentwindow opens & perform the following

Place two NAND gate,two resistor,capacitor, one Dig green bulb, Clock voltage,DGND. Join the circuit as shown in fig.

• Run/Simulate the circuit.Result:

• Design of logic circuit of Oscillator is completed.

CIRCUIT



6.FLIP FLOP6(a) S-R FLIP FLOP

Aim: Design & Simulate a logic circuit of S-R Flip flop. Components used: Two NOT gate(7416N),two NAND gate(7402N), 2 clock voltage, 2 dig probe red bulb,2 dig probe green bulb, 2 DGND Theory:

The S-R Flip Flop using two NAND gates as shown in fig. The two NAND gates are cross coupled, so that the output of NAND gate 1 is connected to one of the inputs of NAND gate 2 and vice versa. The Flip Flop has two outputs Q and 𝑄𝑄 and two inputs Set and Reset. Procedure:

• Open Multisim, click on file, select new-schematic capture.• Click on Place, click Component, select aComponent window opens & perform the following

Place Two NOT gate(7416N),two NAND gate(7402N), 2 clock voltage, 2 dig probe red bulb,2 dig probegreen bulb, 2 DGND on the screen.

Join the circuit as shown in fig.• Run/Simulate the circuit.

Result: • Design of logic circuit of S-R flip flop is completed & is as shown in fig.• Simulation of logic circuit is according to the truth table shown.

LOGIC CIRCUIT

TRUTH TABLE

U1A

7402N

U2B

7402N

V12 Hz 5 V

V25 Hz 5 V

GND

GND

2.5 V

X2

2.5 V

2.5 V

X4

2.5 V

GND

GND

1

2

3

4

S R Q ACTION

0 0 LAST VALUE

NO CHANGE

0 1 0 RESET

1 0 1 SET

1 1 ? FORBIDDEN



PROGRAMMABLE LOGIC CONTROLLER

INTRODUCTION: The first programmable logic controller (PLC) was developed by a group of engineers at general Motors in 1968,when the companies were looking for an alternative to replace the complex relay controlled system.

A programmable logic controller, also called a PLCor programmable controller, is a computer-type microprocessor based circuit used to conduct multiple and complex control operations. The term programmable logic controller is defined as a digitally operating electronic system, designed for use in an industrial environment, which uses a programmable memory for the internal storage of user oriented instructions for implementing specific functions such as logic sequencing timing,counting,and arithmetic. It monitors crucial processes, parameters and controls the process operation accordingly. PLC replaces much complicated wiring by a single circuit. It allows selection of ON/OFF states of output devices. PLC has tremendous computing capacity at the same time is compact.

A programmable logic controller is therefore nothing more than a computer, tailored specifically for certain control tasks. The kinds of equipment that PLC’s can control are as varied like food processing machinery to auto assembly lines.

PROGRAMMING THE PLC Most of the programming methods in use today for PLC’s are based on the Ladder logic program.Ladder logic is a

programming languagethat represents a program by a graphical diagram based on the circuit diagrams of relay-based logic hardware and converted into machine code by use of PLC.The program takes one or more inputs called ‘Contacts’ and produces an output called ‘Coils’. The name is based on the observation that programs in this language resemble ladders, with two vertical rails and a series of horizontal rungs between then. When a PLC is set to run condition, it goes through the entire ladder in descending order starting from top in steps until last rung END.

ADDRESSING THE INPUT AND OUTPUTS: Addressing inputs and output are COMPULSORY and they may be suitably named. However, the numbers 0 to 16

available are not to be repeated as they refer to the indicators/ switches provided on the PLC unit. Inputs asI:0.0/0 to 16 outputs as O:0.0/0 to16

Timers are addressed as below and suitably named When used at output T4:01to16 When it is used at inputT4:01to16/DN

LATCH(Self Maintaining circuit):To hold a coil energized even when input switch is closed and opened, like a push button switch pushed and released.A latch is like a sticky switch - when pushed it will turn on, but stick in place.Example when A is closed, output is energized and contact associated with output is also energized. However if A is now open, output is still on, only way to release is to open contact B.If an output hasbeen latched on, it will keep its value, even if the power has been turned off.

TO START WITH NEW PROGRAM, CLICK ON THE START BUTTON, SELECT ALL PROGRAMS, SELECT ROCKWELL SOFTWARE, SELECT RS LOGIX 500 STARTER, SELECT RS LOGIX 500 STARTER 1-PT MICROLOGIX 1000 ENGLISH.

Ladder symbols used for programming are given below.



1(a) DRAW THE LADDER DIAGRAM TO REPRESENT ‘AND’ GATE Aim: Draw the ladder rungs to represent two switches normally open and both have to be closed for the coil to energise. Ladder symbols used: Two normally open switches and one output. Theory: Fig showsa actuation where a coil is not energized unless two normally open switches are both closed. Switch A and Switch B have both to be closed, which thus givenAND logic. The ladder diagram starts with input 1(switchA) in series withinput 2(switch B) and an output. Procedure:

• Click on new, Select Processor type,Click on OK.Click on User,select new rung• 1st rung: Drag and place two normally open switches andplace one output as shown.• Check the program for syntax error.• Downloading the PLC:Click on OFFLINE,click download, click on OK until ladder rungs shows green light.

Result: • AND gate is completed with output energized when both switches A & B are pressed.

TRUTH TABLE

1(b)DRAW THE LADDER DIAGRAM TO REPRESENT ‘OR’ GATE Aim: Draw the ladder rungs to represent either of the two switches normally open to be closed for the coil to be energized. Ladder symbols used: one rung with branch, two normally open switches and one output. Theory: Fig shows a situation where a coil is not energized until either of normally open switchesA or B is closed.The actuation is an OR logic gate. Either Switch A or Switch B have to be closed, which thus given OR logic. The ladder diagram starts with input 1(switch A) in parallel with input 2(switch B) and an output. Procedure:

• Click on new, Select Processor type, Click on OK. Click on User, select new rung• 1st rung: Drag and place two normally open switches and place one output as shown.• Check the program for syntax error.• Downloading the PLC: Click on OFFLINE, click download, click on OK until ladder rungs shows green light.

Result: • OR gate is completed with output energized when either switch A & B are pressed.

TRUTH TABLE

A B OUTPUT 0 0 0 0 1 0 1 0 0 1 1 1

A B OUTPUT 0 0 0 0 1 1 1 0 1 1 1 1



2.TIMER CIRCUIT

Aim: Program a timing circuit that will switch ON a MOTOR for 20s and then switch it OFF. Ladder symbols used: Two rungs, one with branch, three normally open switches, one normally closed switch,one output and one timer(TON). Procedure:

• Click on new, Select Processor type, Click on OK. Click on User, select new rung • Drag and place all selected symbols as shown. • Check the program for syntax error. • Downloading the PLC: Click on OFFLINE, click download, click on OK until ladder rungs shows green light.

Working of ladder program: Rung 0)With input1 pressed and released, latch is switched on. As input Timer T1/DN is normally closed, MOTOR is energized. Rung 1) MOTORbeing ON, output Timer T1 start and is energized after a lapse of set time. This opens normally closed T1/DN at input in rung 0 and switches offMOTOR. Rung 2) END Result:Functions as desired.

3.ON AND OFF CIRCUIT

Aim: Program a timing circuit that will switch ON for 10s and OFF 10s and so on. Ladder symbols used: Three rungs, three normally open switches, one normally closed switch, one Output and two timer(TON). Procedure:

• Click on new, Select Processor type, Click on OK. Click on User, select new rung • Drag and place all selected symbols as shown. • Check the program for syntax error. • Downloading the PLC: Click on OFFLINE, click download, click on OK until ladder rungs shows green light.

Working of ladder program: Rung 0)With input1 (TOGGLE Switch) is ON,as input Timer T2/DNbeing normally closed, Timer T1 starts and is energized after 10 seconds. This turns ON Timer T2 (rung 2) as well as OUTPUT 3(rung3). Rung 1)When input Timer T1/DN is ON, output Timer T2 starts and is energized after a lapse of 10 seconds. This opens normally closed T2/DN at input in Rung 1 and switches off output Timer T1. Rung 2)With input Timer T1/DN is OFF, OUTPUT 3 is de-energized. This starts Rung 1again and continues. Rung 3) END. Result: At OUTPUT 3, supply is first 10 second OFF, next 10 second ON, next 10 second OFF, next 10 second ON and so on.



4.MOTOR PUMP

Aim: Program a circuit that can be used to start a motor and then to start a pump after delay of 50s. Then the motor is switched off 10s before the pump is switched off when the pump remains on for 50s. Ladder symbols used: Six Rungs, Seven normally open switches, Three normally closed switches,three outputs and threetimers(TON). Procedure:

• Click on new, Select Processor type, Click on OK. Click on User, select new rung.• Drag and place all selected symbols as shown.• Check the program for syntax error.• Downloading the PLC: Click on OFFLINE, click download, click on OK until ladder rungs shows green light.

Working of ladder program: Rung 0)With input1 pressed and released (LATCH),as input timer T5/DN being normally closed, OUTPUT is energized. This output is used at rung 1 and rung 2. Rung 1) With OUTPUT energized, input timer T4/DN being normally closed, MOTORSTART. Rung 2)With OUTPUT energized, starts timer T3 and energises it after lapse of 50 second. This output is used at rung 3 and 4. Rung 3)With input timer T3/DN ON, input timer T5/DN normally closed, PUMP START (50 sec after MOTOR is ON) Rung 4)With input timer T3/DN ON, timer T4 STARTS and energises after set time of 40 second (50-10). Rung 5)With input timer T4/DN ON, timer T5 STARTS and energises after set time of 10 second. This will open normally closed switch timer T5/DN at rung 1 and switches OFF OUTPUT. This in turn switches MOTOR OFF. Rung 6) END Result:Ladder circuit is completed and works as desired.



5.WASHING MACHINE

Aim:Program a circuit that can be used with the domestic washing machine to switch ON a Pump to pump water for 100s into the machine. Then switch ON a Heater for 50s to heat the water. The Heater is switched OFF and another Pump is switched ON to empty the water for 100s. Ladder symbols used: Six rung branch, eight normally opened switches, six normally closed switch,three output and three timer. Procedure:

• Click on new, Select Processor type, Click on OK. Click on User, select new rung• Drag and place all selected symbols as shown.• Check the program for syntax error.• Downloading the PLC: Click on OFFLINE, click download, click on OK until ladder rungs shows green light.

Working of ladder program: Rung 0) With START switch pressed and released (LATCH),as STOP and HEATER switchs normally closed, SUPPLY PUMP is ON. This output is used at rung 1. Rung 1) With SUPPLY PUMP energized, timer T1 at output START and energises after 100 seconds. Rung 2) With timer T1/DN energized, STARTHEATER. This will also STOP SUPPLY PUMP. Rung 3) With HEATER switch ON, timer T2 at output START and energises after 50 seconds. Rung 4) Withtimer T2/DN ON, DELIVERY PUMP will START. This will switch OFF HEATER. Rung 5) With DELIVERY PUMP ON, timer T3 START and is energised after 100 seconds. This will STOP DELIVERY PUMP (after 100 second). Rung 6) END

Result: • Ladder circuit is completed and works as desired.



1.PNEUMATIC CYLINDER

Aim:Design and Simulate a ladder diagram for the forward and reverse movement of the piston in a pneumatic cylinder. The output 1 and output 6 of the PLC are to be connected to the forward and retract coil of the cylinder

Apparatus used: Simulation Chart-1, PLC device The following inputs and outputs addresses are used to simulate the program using animation/simulation chart. INPUT SWITCHES OUTPUT SWITCHES I:0.0/2-Start forward movement O:0.0/0-Piston position I:0.0/8-Start Reverse movement O:0.0/9-Piston forward indicator

O:0.0/4-Piston position O:0.0/10-Piston reverse indicator

Ladder symbols used: Six rung branch, eight normally opened switches, six normally closed switch,three output and three timer. Procedure:

• Click on new, Select Processor type, Click on OK. Click on User, select new rung• Drag and place all selected symbols as shown.• Check the program for syntax error.• Downloading the PLC: Click on OFFLINE, click download, click on OK until ladder rungs shows green light.• Place chart on the PLC unit and press switch 2 or 8 for forward or reverse movement respectively.

Working of ladder program: Rung 0)With input 2 switch pressed and released (LATCH), OUTPUT 1 turns ON Rung 1) OUTPUT 1 ON and Timer2/DN being normally closed, Timer1 START and energises after 5 second. Rung 2) Timer1/DN being ON will turn on PISTON F.Piston moves forward. Rung 3) Timer1/DN will also START forward movement of Piston, indicated by light 9 ON. Rung 4) With input 8 switch pressed and released(LATCH), OUTPUT 6 turns ON. Rung 5) OUTPUT 6 being ON will START timer T2 and energises after 5second. Rung 6) Timet2/DN will START PISTON B. Piston moves reverse. Rung 7) Timer2/DN will also START reverse movement of Piston, indicated by light 10 ON Result:Ladder circuit is completed and works as desired.



2.GARAGE DOOR

Aim: Design and Simulate a ladder diagram to operate a Garage door. Door is OPEN when car is sensed at the garage door and closes after car is parked inside.

Apparatus used: SimulationChart-2,PLC device INPUT SWITCHES OUTPUT SWITCHES I:0.0/9-open door O:0.0/2-Door open indicator I:0.0/3-close door O:0.0/10-car position

O:0.0/0-Door close indicator O:0.0/4-car position

Ladder symbols used: Ten rung, two normally opened switches, four normally closed switch, Procedure:

• Click on new, Select Processor type, Click on OK. Click on User, select new rung• Drag and place all selected symbols as shown.• Check the program for syntax error.• Downloading the PLC: Click on OFFLINE, click download, click on OK until ladder rungs shows green light.• Place chart on the PLC unit and operate..

Working of ladder program: Rung 0): Toggle switch 14 is used as input to sense the vehicle near the garage and shows the output in light10 ON Rung 1): Pressand release switch 9 (LATCH), will turn ON OUTPUT 7. Rung 2): Output 7 will start timer T8 and is energises after 5 seconds. Rung 3): Timer 1/DN being ON and Door close 0 being normally closed will produce OUTPUT 2(Door open) Rung 4): OUTPUT 2(LATCH) will turn OUTPUT 6 ON Rung 5):OUTPUT 6 will start Timer 5 and will energises after 5 second. Rung 6): Timer 5/DN being ON, will turn ON OUTPUT 4. Rung 7): Press switch 3 and release(LATCH), will turn ON OUTPUT 11. Rung 8): OUTPUT 11 will start timer T9 and is energises after 5 second. Rung 9): Timer 9/DN being ON will close DOOR CLOSE.

Result:Ladder circuit is completed and works as desired.



7



3.CAR PARKING

Aim: Program and Simulate a ladder diagram for car parking where caris to be detected and enter the parking space to a particular location if space is available. If there is no space, a lamp should indicate that parking is full.

Apparatus used: Simulation Chart-3,PLC device INPUT SWITCHES OUTPUT SWITCHES I:0.0/14-Switches O:0.0/2-car indicator I:0.0/6-Parking slot-1 O:0.0/8-slot-1 empty I:0.0/9-Parking slot-2 O:0.0/11-slot-2 empty

O:0.0/5-parking full

Ladder symbols used: Five rungs,three normally opened switches, four output and three timer. Procedure:

• Click on new, Select Processor type, Click on OK. Click on User, select new rung• Drag and place all selected symbols as shown.• Check the program for syntax error.• Downloading the PLC: Click on OFFLINE, click download, click on OK until ladder rungs shows green light.• Place chart on the PLC unit and operate..

Working of ladder program: Rung 0): Toggle switch is used as an Input and connected to output 4 indicating presence of the cartoindicate

Press switch 14 to indicate presence of CAR. OUTPUT 1 is ON Rung 1): Switch 6 and Switch 9 are not pressed indicating vacant, parking full light 5 will not glow. If both 6 and 9 are pressed indicating car inslot position, Parking full light 5 will glow. Rung 2): SLOT 1 is occupied (i.e, switch 6 is pressed), Slot 1 empty will not glow. Rung 3): SLOT 2 is occupied (i.e, switch 9 is pressed), Slot 2 empty will not glow.

Result:Ladder circuit is completed and works as desired.



4.CONVEYOR Aim: Design and Simulate a ladder diagram to detect a bottle without cap on a conveyer in a bottling plant and indicate the same through an indicator.

Apparatus used: Psim software

INPUT SWITCHES F1=I:100 NO F2=I:101 NC Photo switch=I:103 Level Full=I:104 OUTPUT SWITCHES O:100-motor ON O:101-Solenoid for valve O:102-Run light O:103-tand by light O:104-Tank full light

Procedure: • Rung 1;InputI:101 is latched to output O:102 to supply power continuosly to the output,inbetween there is a normally

open switch I:100 to stop the conveyor when the bottle without cap is detected. • Rung 2: The output O:102 is used to switch on the motor O:100, the normally cloed witch in between is used to stop the

motor(O:101) • Rung 3:I:103 is a input photo switch which detects the bottle and opens the solenoid O:101 to fill the bottle with the

liquid that has to be filled in the bottle. • Rung4:I:104 is an input witch to the output O:103 which glows when the liquid has leveled its peak point in the bottle.• Rung 5: Output O:103 is made to switch off the solenoid O:104 afetr the liquid has reached its peak point to stop

overflowing of the liquid that has been filled.


Mechatronics Lab Manual MultSim PLC Ladder Simulation Circuits Diploma Mechanical Karnataka

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Transcript of Mechatronics Lab Manual MultSim PLC Ladder Simulation Circuits Diploma Mechanical Karnataka