MCP6546/6R/6U/7/8/9 - Open-Drain Output Sub-Microamp ...

MCP6546/6R/6U/7/8/9Open-Drain Output Sub-Microamp Comparators

Features• Low Quiescent Current: 600 nA/Comparator (typical)• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V• Open-Drain Output: VOUT ≤ 10V• Propagation Delay: 4 µs (typical, 100 mV Overdrive)• Wide Supply Voltage Range: 1.6V to 5.5V• Single Available in SOT-23-5, SC-70-5* Packages• Available in Single, Dual and Quad• Chip Select (CS) with MCP6548• Low Switching Current• Internal Hysteresis: 3.3 mV (typical)• Temperature Range:

- Industrial: -40°C to +85°C- Extended: -40°C to +125°C

Typical Applications• Laptop Computers• Mobile Phones• Metering Systems• Hand-held Electronics• RC Timers• Alarm and Monitoring Circuits• Windowed Comparators• Multi-vibrators

Related Devices• CMOS/TTL-Compatible Output: MCP6541/2/3/4

DescriptionThe Microchip Technology Inc. MCP6546/6R/6U/7/8/9family of comparators, is offered in single (MCP6546, MCP6546R, MCP6546U), single with chip select (CS)(MCP6548), dual (MCP6547) and quad (MCP6549)configurations. The outputs are open-drain and arecapable of driving heavy DC or capacitive loads.

These comparators are optimized for low power,single-supply application with greater than rail-to-railinput operation. The output limits supply current surgesand dynamic power consumption while switching. Theopen-drain output of the MCP6546/6R/6U/7/8/9 familycan be used as a level-shifter for up to 10V using a pull-up resistor. It can also be used as a wired-OR logic.The internal Input hysteresis eliminates output switch-ing due to internal noise voltage, reducing current draw.These comparators operate with a single-supplyvoltage as low as 1.6V and draw a quiescent current ofless than 1 µA/comparator.

The related MCP6541/2/3/4 family of comparators fromMicrochip has a push-pull output that supports rail-to-rail output swing and interfaces with CMOS/TTL logic.

* SC-70-5 E-Temp parts are not available at thisrelease of the data sheet.

MCP6546U SOT-23-5 is E-Temp only.

Package Types

VIN+VIN–

MCP6546

VSS

VDDOUT

1

234

8765

-+

NC

NCNC

PDIP, SOIC, MSOP

4

1

2

3

-+

5

SOT-23-5

VDD

OUT

VIN+

VSS

VIN–

MCP6546R MCP6547

VINA+VINA–

VSS

1

234

8765

-

OUTA

+ -

+

VDD

OUTBVINB–VINB+

VIN+VIN–

MCP6548

VSS

VDD

OUT

1234

8765

-+

NC

CSNC

PDIP, SOIC, MSOP

PDIP, SOIC, MSOP

MCP6549

VINA+

VINA–

VSS

1

2

3

4

14

13

12

11

-

OUTA

+ -+

VDD

OUTD

VIND–

VIND+

109

8

5

67OUTB

VINB–

VINB+ VINC+VINC–OUTC

+- -+

PDIP, SOIC, TSSOP

4

1

2

3

-+

5

SC-70-5, SOT23-5

VSS

OUT

VIN+

VDD

VIN–

MCP6546

4

1

2

3

5

SC-70-5, SOT-23-5

VSS

VIN+

VIN–

VDD

OUT

MCP6546U

-+

© 2002-2012 Microchip Technology Inc. DS21714G-page 1

MCP6546/6R/6U/7/8/9

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †VDD - VSS .........................................................................7.0VOpen-Drain Output.............................................. VSS + 10.5VAnalog Input (VIN+, VIN-)††............. VSS - 1.0V to VDD + 1.0VAll Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3VDifference Input Voltage ...................................... |VDD – VSS|Output Short-Circuit Current .................................continuousCurrent at Input Pins ....................................................±2 mACurrent at Output and Supply Pins ............................±30 mAStorage Temperature.....................................-65°C to +150°CMaximum Junction Temperature (TJ) ..........................+150°CESD Protection on All Pins:

(HBM;MM) .....................................2 kV;200V (MCP6546U)(HBM;MM) ................................ 4 kV; 200V (all other parts)

† Notice: Stresses above those listed under “AbsoluteMaximum Ratings” may cause permanent damage tothe device. This is a stress rating only, and functionaloperation of the device, at those or any other conditionsabove those indicated in the operational listings of thisspecification, is not implied. Exposure to maximum rat-ing conditions for extended periods may affect devicereliability.

†† See Section 4.1.2 “Input Voltage and CurrentLimits”

DC CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS, RPU = 2.74 kΩ to VPU = VDD (Refer to Figure 1-3).

Parameters Sym Min Typ Max Units Conditions

Power SupplySupply Voltage VDD 1.6 — 5.5 V VPU ≥ VDDQuiescent Current(per comparator)

IQ 0.3 0.6 1 µA IOUT = 0

InputInput Voltage Range VCMR VSS −

0.3— VDD + 0.3 V

Common Mode Rejection Ratio CMRR 55 70 — dB VDD = 5V, VCM = -0.3V to 5.3VCommon Mode Rejection Ratio CMRR 50 65 — dB VDD = 5V, VCM = 2.5V to 5.3VCommon Mode Rejection Ratio CMRR 55 70 — dB VDD = 5V, VCM = -0.3V to 2.5VPower Supply Rejection Ratio PSRR 63 80 — dB VCM = VSSInput Offset Voltage VOS -7.0 ±1.5 +7.0 mV VCM = VSS (Note 1)

Drift with Temperature ΔVOS/ΔTA — ±3 — µV/°C TA = -40°C to +125°C, VCM = VSSInput Hysteresis Voltage VHYST 1.5 3.3 6.5 mV VCM = VSS (Note 1)

Linear Temp. Co. TC1 — 6.7 — µV/°C TA = -40°C to +125°C, VCM = VSS (Note 2)

Quadratic Temp. Co. TC2 — -0.035 — µV/°C2 TA = -40°C to +125°C, VCM = VSS (Note 2)

Input Bias Current IB — 1 — pA VCM = VSSAt Temperature (I-Temp parts) IB — 25 100 pA TA = +85°C, VCM = VSS (Note 3)At Temperature (E-Temp parts) IB — 1200 5000 pA TA = +125°C, VCM = VSS (Note 3)

Input Offset Current IOS — ±1 — pA VCM = VSSNote 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference

between the input-referred trip points.2: VHYST at differential temperatures is estimated using:

VHYST (TA) = VHYST + (TA -25°C) TC1 + (TA - 25°C)2TC2.3: Input bias current at temperature is not tested for the SC-70-5 package.4: Do not short the output above VSS + 10V. Limit the output current to Absolute Maximum Rating of 30 mA.

The minimum VPU test limit was VDD before Dec. 2004 (week code 52).

DS21714G-page 2 © 2002-2012 Microchip Technology Inc.

MCP6546/6R/6U/7/8/9

Common Mode Input Impedance ZCM — 1013||4 — Ω||pFDifferential Input Impedance ZDIFF — 1013||2 — Ω||pFOpen-Drain OutputOutput Pull-Up Voltage VPU 1.6 — 10 V (Note 4)High-Level Output Current IOH -100 — — nA VDD = 1.6V to 5.5V, VPU = 10V

(Note 4)Low-Level Output Voltage VOL VSS — VSS + 0.2 V IOUT = 2 mA, VPU = VDD = 5VShort-Circuit Current ISC — ±1.5 — mA VPU = VDD = 1.6V (Note 4)

ISC – 30 — mA VPU = VDD = 5.5V (Note 4)Output Pin Capacitance COUT — 8 — pF

AC CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,Step = 200 mV, Overdrive = 100 mV, RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF (Refer to Figure 1-2 and Figure 1-3).


Fall Time tF — 0.7 — µs (Note 1)Propagation Delay (High-to-Low) tPHL — 4.0 8.0 µsPropagation Delay (Low-to-High) tPLH — 3.0 8.0 µs (Note 1)Propagation Delay Skew tPDS — -1.0 — µs (Notes 1 and 2)Maximum Toggle Frequency fMAX — 225 — kHz VDD = 1.6V

fMAX — 165 — kHz VDD = 5.5VInput Noise Voltage Eni — 200 — µVP-P 10 Hz to 100 kHzNote 1: tR and tPLH depend on the load (RL and CL); these specifications are valid for the indicated load only.

2: Propagation Delay Skew is defined as: tPDS = tPLH - tPHL.

DC CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS, RPU = 2.74 kΩ to VPU = VDD (Refer to Figure 1-3).


Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points.

2: VHYST at differential temperatures is estimated using: VHYST (TA) = VHYST + (TA -25°C) TC1 + (TA - 25°C)2TC2.

3: Input bias current at temperature is not tested for the SC-70-5 package.4: Do not short the output above VSS + 10V. Limit the output current to Absolute Maximum Rating of 30 mA.

The minimum VPU test limit was VDD before Dec. 2004 (week code 52).


MCP6546/6R/6U/7/8/9

FIGURE 1-1: Timing Diagram for the CS pin on the MCP6548.

FIGURE 1-2: Propagation Delay Timing Diagram.

MCP6548 CHIP SELECT (CS) CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS, RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF (Refer to Figures 1-1 and 1-3).


CS Low Specifications

CS Logic Threshold, Low VIL VSS — 0.2 VDD

V

CS Input Current, Low ICSL — 5 — pA CS = VSS

CS High Specifications

CS Logic Threshold, High VIH 0.8 VDD — VDD V

CS Input Current, High ICSH — 1 — pA CS = VDD

CS Input High, VDD Current IDD — 18 — pA CS = VDD

CS Input High, GND Current ISS — -20 — pA CS = VDD

Comparator Output Leakage IO(LEAK) — 1 — pA VOUT = VSS+10V, CS = VDD

CS Dynamic Specifications

CS Low to Comparator Output Low Turn-on Time

tON — 2 50 ms CS = 0.2VDD to VOUT = VDD/2,VIN– = VDD

CS High to Comparator Output High Z Turn-off Time

tOFF — 10 — µs CS = 0.8VDD to VOUT = VDD/2,VIN– = VDD

CS Hysteresis VCS_HYST — 0.6 — V VDD = 5V

VIL

High-Z

tON

VIHCS

tOFF

VOUT

-20 pA (typ.)

High-Z

ISS

ICS

-20 pA (typ.)-0.6 µA (typ.)

1 pA (typ.) 1 pA (typ.)5 pA (typ.)

VOL

tPLH

VOUT

VIN–100 mV

100 mV tPHL

VOL

VIN+ = VDD/2

VOH


MCP6546/6R/6U/7/8/9

1.1 Test Circuit ConfigurationThis test circuit configuration is used to determine theAC and DC specifications.

FIGURE 1-3: AC and DC Test Circuit for the Open-Drain Output Comparators.

TEMPERATURE CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V and VSS = GND.


Temperature RangesSpecified Temperature Range TA -40 — +85 °COperating Temperature Range TA -40 — +125 °C NoteStorage Temperature Range TA -65 — +150 °CThermal Package ResistancesThermal Resistance, 5L-SC-70 θJA — 331 — °C/WThermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/WThermal Resistance, 8L-MSOP θJA — 211 — °C/WThermal Resistance, 8L-PDIP θJA — 89.3 — °C/WThermal Resistance, 8L-SOIC θJA — 149.5 — °C/WThermal Resistance, 14L-PDIP θJA — 70 — °C/WThermal Resistance, 14L-SOIC θJA — 95.3 — °C/WThermal Resistance, 14L-TSSOP θJA — 100 — °C/W

Note: The MCP6546/6R/6U/7/8/9 I-temp family operates over this extended temperature range, but with reducedperformance. In any case, the Junction Temperature (TJ) must not exceed the absolute maximumspecification of +150°C.

VDD

VSS = 0V

200 kΩ

200 kΩ

100 kΩ

VOUT

VIN = VSS

36 pF

MCP654XRPU =

VPU = VDD

(2 mA)/ VDD


MCP6546/6R/6U/7/8/9

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.

FIGURE 2-1: Input Offset Voltage at VCM = VSS.

FIGURE 2-2: Input Offset Voltage Drift at VCM = VSS.

FIGURE 2-3: The MCP6546/6R/6U/7/8/9 Comparators Show No Phase Reversal.

FIGURE 2-4: Input Hysteresis Voltage at VCM = VSS.

FIGURE 2-5: Input Hysteresis Voltage Linear Temp. Co. (TC1) at VCM = VSS.

FIGURE 2-6: Input Hysteresis Voltage Quadratic Temp. Co. (TC2) at VCM = VSS.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

0%

2%

4%

6%

8%

10%

12%

14%

-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7Input Offset Voltage (mV)

Perc

enta

ge o

f Occ

urre

nces 1200 Samples

VCM = VSS

0%2%4%6%8%

10%12%14%16%

-14

-12

-10 -8 -6 -4 -2 0 2 4 6 8 10 12 14

Input Offset Voltage Drift (µV/°C)

Perc

enta

ge o

f Occ

urre

nces 1200 Samples

VCM = VSSTA = -40°C to +125°C

-1

0

1

2

3

4

5

6

7

0 1 2 3 4 5 6 7 8 9 10Time (1 ms/div)

Inve

rtin

g In

put,

Out

put

Volta

ge (V

)

VOUT

VIN–

VDD = 5.5V

0%2%4%6%8%

10%12%14%16%18%

1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0Input Hysteresis Voltage (mV)

Perc

enta

ge o

f Occ

urre

nces 1200 Samples

VCM = VSS

0%

5%

10%

15%

20%

25%4.

6

5.0

5.4

5.8

6.2

6.6

7.0

7.4

7.8

8.2

8.6

9.0

9.4

Input Hysteresis Voltage –Linear Temp. Co.; TC1 (µV/°C)

Perc

enta

ge o

f Occ

urre

nces 596 Samples


VDD = 1.6VVDD = 5.5V

0%2%4%6%8%

10%12%14%16%18%20%

-0.0

60

-0.0

56

-0.0

52

-0.0

48

-0.0

44

-0.0

40

-0.0

36

-0.0

32

-0.0

28

-0.0

24

-0.0

20

-0.0

16

Input Hysteresis Voltage –Quadratic Temp. Co.; TC2 (µV/°C2)

Perc

enta

ge o

f Occ

urre

nces 596 Samples


VDD = 5.5V

VDD = 1.6V


MCP6546/6R/6U/7/8/9
FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature at VCM = VSS.

FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.6V.

FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V.

FIGURE 2-10: Input Hysteresis Voltage vs. Ambient Temperature at VCM = VSS.

FIGURE 2-11: Input Hysteresis Voltage vs. Common Mode Input Voltage at VDD = 1.6V.

FIGURE 2-12: Input Hysteresis Voltage vs. Common Mode Input Voltage at VDD = 5.5V.

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

-50 -25 0 25 50 75 100 125Ambient Temperature (°C)

Inpu

t Offs

et V

olta

ge (m

V)

VDD = 1.6V

VDD = 5.5V

VCM = VSS

-2.0-1.5-1.0-0.50.00.51.01.52.0

-0.4

-0.2 0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Common Mode Input Voltage (V)

Inpu

t Offs

et V

olta

ge (m

V) VDD = 1.6V

TA = +125°CTA = +85°CTA = +25°CTA = -40°CTA = +125°C

-2.0-1.5-1.0-0.50.00.51.01.52.0

-0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0


Inpu

t Offs

et V

olta

ge (m

V) VDD = 5.5V

TA = +85°CTA = +125°C

TA = -40°CTA = +25°C

1.52.02.53.03.54.04.55.05.56.06.5


Inpu

t Hys

tere

sis

Volta

ge (m

V)

VDD = 1.6V

VDD = 5.5V

VCM = VSS

1.52.02.53.03.54.04.55.05.56.06.5

-0.4

-0.2 0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0


Inpu

t Hys

tere

sis

Volta

ge (m

V)

TA = +25°CTA = -40°C

TA = +125°CTA = +85°C

VDD = 1.6V

TA = +125°C

1.52.02.53.03.54.04.55.05.56.06.5

-0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0


Inpu

t Hys

tere

sis

Volta

ge (m

V) VDD = 5.5V TA = +125°CTA = +85°CTA = +25°CTA = -40°C


MCP6546/6R/6U/7/8/9
FIGURE 2-13: CMRR,PSRR vs. Ambient Temperature.

FIGURE 2-14: Input Bias Current, Input Offset Current vs. Ambient Temperature.

FIGURE 2-15: Quiescent Current vs. Common Mode Input Voltage at VDD = 1.6V.

FIGURE 2-16: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage.

FIGURE 2-17: Quiescent Current vs. Power Supply Voltage.

FIGURE 2-18: Quiescent Current vs. Common Mode Input Voltage at VDD = 5.5V.

55

60

65

70

75

80

85

90


CM

RR

, PSR

R (d

B)

Input Referred

PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V

CMRR, VIN+ = -0.3 to 5.3V, VDD = 5.0V

0.1

1

10

100

1000

55 65 75 85 95 105 115 125

Ambient Temperature (°C)

Inpu

t Bia

s, O

ffset

Cur

rent

s(p

A) IB

| IOS |

VDD = 5.5VVCM = VDD

0.00.10.20.30.40.50.60.70.8

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6Common Mode Input Voltage (V)

Qui

esce

nt C

urre

ntpe

r Com

para

tor (

µA) VDD = 1.6V

Sweep VIN+, VIN– = VDD/2

Sweep VIN–, VIN+ = VDD/2

IQ does not include pull-up resistor current

0.1

1

10

100

1000

10000

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Common Mode Input Voltage (V)

Inpu

t Bia

s, O

ffset

Cur

rent

s (A

)

VDD = 5.5V

100f

100p

1p

10p

1n

10nIB, TA = +125°C

IB, TA = +85°C

IOS, TA = +125°CIOS, TA = +85°C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Power Supply Voltage (V)

Qui

esce

nt C

urre

ntpe

r Com

para

tor (

µA)

TA = +125°CTA = +85°CTA = +25°CTA = -40°C

0.00.10.20.30.40.50.60.70.8


Qui

esce

nt C

urre

ntpe

r Com

para

tor (

µA) VDD = 5.5V

Sweep VIN+, VIN– = VDD/2

Sweep VIN–, VIN+ = VDD/2

IQ does not include pull-up resistor current


MCP6546/6R/6U/7/8/9
FIGURE 2-19: Supply Current vs. Pull-Up Voltage.

FIGURE 2-20: Supply Current vs. Toggle Frequency.

FIGURE 2-21: Output Voltage Headroom vs. Output Current at VDD = 1.6V.

FIGURE 2-22: Supply Current vs. Pull-Up to Supply Voltage Difference.

FIGURE 2-23: Output Short Circuit Current Magnitude vs. Power Supply Voltage.

FIGURE 2-24: Output Voltage Headroom vs. Output Current at VDD = 5.5V.

0.1

1

10

0 1 2 3 4 5 6 7 8 9 10 11Pull-Up Voltage, VPU (V)

Supp

ly C

urre

ntpe

r Com

para

tor (

µA) VDD = 2.1V

VDD = 2.6VVDD = 3.6VVDD = 4.6VVDD = 5.6V

IDD spike near VPU = 1.3V

VDD = 1.6V

0.1

1

10

0.1 1 10 100Toggle Frequency (kHz)

Supp

ly C

urre

ntpe

r Com

para

tor (

µA)


100 mV OverdriveVCM = VDD/2IDD does not includepull-up resistor current

0.00.10.20.30.40.50.60.70.8

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6Output Current (mA)

Out

put V

olta

ge H

eadr

oom

(V)

VDD = 1.6VVOL–VSS:TA = +125°CTA = +85°CTA = +25°CTA = -40°C

0.1

1

10

-4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9Pull-up to Supply Voltage Difference,

VPU – VDD (V)

Supp

ly C

urre

ntpe

r Com

para

tor (

µA) VDD = 5.6V

VDD = 4.6VVDD = 3.6VVDD = 2.6V

VPU = 1.6V to 10.5V


0

5

10

15

20

25

30

35

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Power Supply Voltage (V)

Out

put S

hort

Circ

uit C

urre

ntM

agni

tude

(mA

)

TA = -40°CTA = +25°CTA = +85°C

TA = +125°C

0.00.10.20.30.40.50.60.70.80.91.0

0 5 10 15 20 25Output Current (mA)

Out

put V

olta

ge H

eadr

oom

(V) VDD = 5.5V

TA = +125°CTA = +85°CTA = +25°CTA = -40°C

VOL – VSS:


MCP6546/6R/6U/7/8/9
FIGURE 2-25: High-to-Low Propagation Delay.

FIGURE 2-26: Propagation Delay Skew.

FIGURE 2-27: Propagation Delay vs. Power Supply Voltage.

FIGURE 2-28: Low-to-High Propagation Delay.

FIGURE 2-29: Propagation Delay vs. Ambient Temperature.

FIGURE 2-30: Propagation Delay vs. Input Overdrive.

0%5%

10%15%20%25%30%35%40%45%50%

0 1 2 3 4 5 6 7 8High-to-Low Propagation Delay (µs)

Perc

enta

ge o

f Occ

urre

nces 408 Samples

100 mV OverdriveVCM = VDD/2


0%5%

10%15%20%25%30%35%40%45%50%

-2.0

-1.6

-1.2

-0.8

-0.4 0.0

0.4

0.8

1.2

1.6

2.0

Propagation Delay Skew (µs)

Perc

enta

ge o

f Occ

urre

nces 408 Samples


VDD = 1.6V

VDD = 5.5V

0123456789

1011121314

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Power Supply Voltage (V)

Prop

agat

ion

Del

ay (µ

s)

VCM = VDD/2tPHL

10 mV Overdrive

100 mV Overdrive tPLH

0%5%

10%15%20%25%30%35%40%45%50%55%60%65%

0 1 2 3 4 5 6 7 8Low-to-High Propagation Delay (µs)

Perc

enta

ge o

f Occ

urre

nces 408 Samples



012345678


Prop

agat

ion

Del

ay (µ

s)


tPHL

tPLH

VDD = 5.5V

VDD = 1.6V

1

10

100

1 10 100 1000Input Overdrive (mV)

Prop

agat

ion

Del

ay (µ

s)

VCM = VDD/2

tPLH

VDD = 5.5VtPHL

VDD = 1.6V


MCP6546/6R/6U/7/8/9
FIGURE 2-31: Propagation Delay vs. Common Mode Input Voltage at VDD = 1.6V.

FIGURE 2-32: Propagation Delay vs. Pull-up Resistor.

FIGURE 2-33: Propagation Delay vs. Pull-up Voltage.

FIGURE 2-34: Propagation Delay vs. Common Mode Input Voltage at VDD = 5.5V.

FIGURE 2-35: Propagation Delay vs. Load Capacitance.

FIGURE 2-36: Output Leakage Current (CS = VDD) vs. Output Voltage (MCP6548 only).

012345678

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6Common Mode Input Voltage (V)

Prop

agat

ion

Del

ay (µ

s)

VDD = 1.6V100 mV Overdrive

tPLH

tPHL

0

1

2

3

4

5

6

7

8

0 10 20 30 40 50 60 70 80 90 100Pull-up Resistor, RPU (k�)

Prop

agat

ion

Del

ay (µ

s) VCM = VDD/2VIN+ = VCM

VDD = 5.5V

VIN– = 100 mV Overdrive

tPHL

tPLH

VDD = 1.6V

012345678

0 1 2 3 4 5 6 7 8 9 10 11Pull-up Voltage (V)

Prop

agat

ion

Del

ay (µ

s) VCM = VDD/2VIN+ = VCM

tPHL

VIN– = 100 mV Overdrive

VDD = 5.5V

VDD = 1.6V tPLH

012345678


Prop

agat

ion

Del

ay (µ

s)

VDD = 5.5V100 mV Overdrive

tPHL

tPLH

020406080

100120140160180200

0 10 20 30 40 50 60 70 80 90Load Capacitance (nF)

Prop

agat

ion

Del

ay (µ

s)

100 mV OverdriveVCM = VDD/2 tPLH

tPHLVDD = 1.6VVDD = 5.5V

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

0 1 2 3 4 5 6 7 8 9 10 11Output Voltage (V)

Out

put L

eaka

ge C

urre

nt (A

)

TA = +85°CCS = VDDVIN+ = VDD/2VIN– = VSS

TA = +125°C

TA = +25°C

10n

1n

100p

10p

1p

100f


MCP6546/6R/6U/7/8/9
FIGURE 2-37: Supply Current (Shoot- through Current) vs. Chip Select (CS) Voltage at VDD = 1.6V (MCP6548 only).

FIGURE 2-38: Supply Current (Charging Current) vs. Chip Select (CS) pulse at VDD = 1.6V (MCP6548 only).

FIGURE 2-39: Chip Select (CS) Step Response (MCP6548 only).

FIGURE 2-40: Supply Current (Shoot- through Current) vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6548 only).

FIGURE 2-41: Supply Current (Charging Current) vs. Chip Select (CS) pulse at VDD = 5.5V (MCP6548 only).

FIGURE 2-42: Input Bias Current vs. Input Voltage.

1.E-111.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-03

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6Chip Select (CS) Voltage (V)

Supp

ly C

urre

ntpe

r Com

para

tor (

A)

ComparatorShuts Off

ComparatorTurns On

VDD = 1.6V

CS Hysteresis

CSHigh-to-Low

CSLow-to-High

1m

1µ10µ

100n

1n10n

100p10p

100µ

0

5

10

15

20

25

30

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14Time (1 ms/div)

Supp

ly C

urre

nt (µ

A)

-8.1

-6.5

-4.9

-3.2

-1.6

0.0

1.6

Out

put V

olta

ge,

Chi

p Se

lect

Vol

tage

(V),

Start-upIDDCharging output

capacitance

VDD = 1.6V

VOUT

CS

-0.50.00.51.01.52.02.53.03.54.04.55.05.56.0

0 1 2 3 4 5 6 7 8 9 10Time (ms)

Chi

p Se

lect

, Out

put V

olta

ge

(V)

VOUT

VDD = 5.5V

CS

1.E-111.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-03

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Chip Select (CS) Voltage (V)

Supp

ly C

urre

ntpe

r Com

para

tor (

A)

ComparatorShuts Off

ComparatorTurns On

VDD = 5.5V

1m

1µ10µ

100n

1n10n

100p10p

CSLow-to-High

CSHysteresis

CSHigh-to-Low

100µ

020406080

100120140160180200

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5Time (0.5 ms/div)

Supp

ly C

urre

ntpe

r Com

para

tor (

µA)

-24-21-18-15-12-9-6-3036

Out

put V

olta

ge,

Chi

p Se

lect

Vol

tage

(V)

Start-up IDD

Charging outputcapacitance

VDD = 5.5V

VOUTCS

1.E-121.E-111.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-031.E-02

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0Input Voltage (V)

Inpu

t Cur

rent

Mag

nitu

de (A

)

+125°C+85°C+25°C-40°C

10m1m

100µ10µ1µ

100n10n1n

100p10p1p


MCP6546/6R/6U/7/8/9

3.0 PIN DESCRIPTIONSDescriptions of the pins are listed in Table 3-1.

3.1 Analog InputsThe comparator non-inverting and inverting inputs arehigh-impedance CMOS inputs with low bias currents.

3.2 CS Digital InputThis is a CMOS, Schmitt-triggered input that places thepart into a low power mode of operation.

3.3 Digital OutputsThe comparator outputs are CMOS, open-drain digitaloutputs. They are designed to make level shifting andwired-OR easy to implement.

3.4 Power Supply (VSS and VDD)The positive power supply pin (VDD) is 1.6V to 5.5Vhigher than the negative power supply pin (VSS). Fornormal operation, the other pins are at voltagesbetween VSS and VDD, except the output pins whichcan be as high as 10V above VSS.

Typically, these parts are used in a single (positive)supply configuration. In this case, VSS is connected toground and VDD is connected to the supply. VDD willneed a local bypass capacitor (typically 0.01 µF to0.1 µF) within 2 mm of the VDD pin. These can share abulk capacitor with nearby analog parts (within100 mm), but it is not required.

TABLE 3-1: PIN FUNCTION TABLEM

CP6

546

MC

P654

6

MC

P654

6R

MC

P654

6U

MC

P654

7

MC

P654

8

MC

P654

9

Symbol Description

PDIP,SOIC,MSOP

SC-70, SOT-23 SOT-23-5 SC-70,

SOT-23-5

PDIP,SOIC,MSOP

PDIP,SOIC,MSOP

PDIP,SOIC,

TSSOP

6 1 1 4 1 6 1 OUT, OUTA

Digital Output (comparator A)

2 4 4 3 2 2 2 VIN–, VINA–

Inverting Input (comparator A)

3 3 3 1 3 3 3 VIN+, VINA+

Non-inverting Input (comparator A)

7 5 2 5 8 7 4 VDD Positive Power Supply— — — — 5 — 5 VINB+ Non-inverting Input

(comparator B)— — — — 6 — 6 VINB– Inverting Input (comparator B)— — — — 7 — 7 OUTB Digital Output (comparator B)— — — — — — 8 OUTC Digital Output (comparator C)— — — — — — 9 VINC– Inverting Input (comparator C)— — — — — — 10 VINC+ Non-inverting Input

(comparator C)4 2 5 2 4 4 11 VSS Negative Power Supply— — — — — — 12 VIND+ Non-inverting Input

(comparator D)— — — — — — 13 VIND– Inverting Input (comparator D)— — — — — — 14 OUTD Digital Output (comparator D)— — — — — 8 — CS Chip Select

1, 5, 8 — — — — 1, 5 — NC No Internal Connection


MCP6546/6R/6U/7/8/9
NOTES:

MCP6546/6R/6U/7/8/9

4.0 APPLICATIONS INFORMATIONThe MCP6546/6R/6U/7/8/9 family of push-pull outputcomparators are fabricated on Microchip’s state-of-the-art CMOS process. They are suitable for a wide rangeof applications requiring very low power consumption.

4.1 Comparator Inputs

4.1.1 PHASE REVERSALThe MCP6546/6R/6U/7/8/9 comparator family usesCMOS transistors at the input. They are designed toprevent phase inversion when the input pins exceedthe supply voltages. Figure 2-3 shows an input voltageexceeding both supplies with no resulting phaseinversion.

4.1.2 INPUT VOLTAGE AND CURRENT LIMITS

The ESD protection on the inputs can be depicted asshown in Figure 4-1. This structure was chosen to pro-tect the input transistors, and to minimize input biascurrent (IB). The input ESD diodes clamp the inputswhen they try to go more than one diode drop belowVSS. They also clamp any voltages that go too farabove VDD; their breakdown voltage is high enough toallow normal operation, and low enough to bypass ESDevents within the specified limits.

FIGURE 4-1: Simplified Analog Input ESD Structures.In order to prevent damage and/or improper operationof these amplifiers, the circuits they are in must limit thecurrents (and voltages) at the VIN+ and VIN– pins (seeAbsolute Maximum Ratings † at the beginning ofSection 1.0 “Electrical Characteristics”). Figure 4-3shows the recommended approach to protecting theseinputs. The internal ESD diodes prevent the input pins(VIN+ and VIN–) from going too far below ground, andthe resistors R1 and R2 limit the possible current drawnout of the input pin. Diodes D1 and D2 prevent the inputpin (VIN+ and VIN–) from going too far above VDD.When implemented as shown, resistors R1 and R2 alsolimit the current through D1 and D2.

FIGURE 4-2: Protecting the Analog Inputs.It is also possible to connect the diodes to the left ofresistors R1 and R2. In this case, the currents throughdiodes D1 and D2 need to be limited by some othermechanism. The resistor then serves as in-rush currentlimiter; the DC current into the input pins (VIN+ andVIN–) should be very small.

A significant amount of current can flow out of theinputs when the common mode voltage (VCM) is belowground (VSS); see Figure 2-42. Applications that arehigh impedance may need to limit the usable voltagerange.

4.1.3 NORMAL OPERATIONThe input stage of this family of devices uses twodifferential input stages in parallel, one operates at lowinput voltages, and the other at high input voltages.With this topology, the input voltage is 0.3V above VDDand 0.3V below VSS. The input offset voltage ismeasured at both VSS - 0.3V and VDD + 0.3V to ensureproper operation.

The MCP6546/6R/6U/7/8/9 family has internally-sethysteresis that is small enough to maintain input offsetaccuracy (<7 mV), and large enough to eliminateoutput chattering caused by the comparator’s owninput noise voltage (200 µVP-P). Figure 4-3 illustratesthis capability.

BondPad

BondPad

BondPad

VDD

VIN+

VSS

InputStage

BondPad

VIN–

V1MCP6G0XR1

VDD

D1

R1 ≥VSS – (minimum expected V1)

2 mA

VOUT

V2R2 R3

D2

+

–

R2 ≥VSS – (minimum expected V2)

2 mA


MCP6546/6R/6U/7/8/9

FIGURE 4-3: The MCP6546/6R/6U/7/8/9 Comparators’ Internal Hysteresis Eliminates Output Chatter Caused By Input Noise Voltage.

4.2 Open-Drain OutputThe open-drain output is designed to make level-shifting and wired-OR logic easy to implement. Theoutput can go as high as 10V for 9V battery-poweredapplications. The output stage minimizes switching cur-rent (shoot-through current from supply-to-supply)when the output changes state. See Figures 2-15, 2-18and 2-37 through 2-41, for more information.

4.3 MCP6548 Chip Select (CS)The MCP6548 is a single comparator with a ChipSelect (CS) pin. When CS is pulled high, the totalcurrent consumption drops to 20 pA (typical). 1 pA(typical) flows through the CS pin, 1 pA (typical) flowsthrough the output pin and 18 pA (typical) flows throughthe VDD pin, as shown in Figure 1-1. When thishappens, the comparator output is put into a high-impedance state. By pulling CS low, the comparator isenabled. If the CS pin is left floating, the comparator willnot operate properly. Figure 1-1 shows the outputvoltage and supply current response to a CS pulse.

The internal CS circuitry is designed to minimizeglitches when cycling the CS pin. This helps conservepower, which is especially important in battery-poweredapplications.

4.4 Externally Set HysteresisGreater flexibility in selecting hysteresis, or input trippoints, is achieved by using external resistors.

Input offset voltage (VOS) is the center (average) of the(input-referred) low-high and high-low trip points. Inputhysteresis voltage (VHYST) is the difference betweenthe same trip points. Hysteresis reduces outputchattering when one input is slowly moving past theother, thus reducing dynamic supply current. It alsohelps in systems where it is best not to cycle betweenstates too frequently (e.g., air conditioner thermostaticcontrol).

4.4.1 INVERTING CIRCUITFigure 4-4 shows an inverting circuit for a single-supplyapplication using three resistors, besides the pull-upresistor. The resulting hysteresis diagram is shown inFigure 4-5.

FIGURE 4-4: Inverting Circuit with Hysteresis.

FIGURE 4-5: Hysteresis Diagram for the Inverting Circuit.In order to determine the trip voltages (VTHL and VTLH)for the circuit shown in Figure 4-4, R2 and R3 can besimplified to the Thevenin equivalent circuit withrespect to VDD, as shown in Figure 4-6.

FIGURE 4-6: Thevenin Equivalent Circuit.

-3-2-1012345678

Time (100 ms/div)

Out

put V

olta

ge (V

)

-30-25-20-15-10-50510152025

Inpu

t Vol

tage

(10

mV/

div)

VOUT

VIN–

VDD = 5.0V

Hysteresis

VIN

VOUTMCP654X

VDD

R2

RFR3

VPU

RPU

VDD IOLIRF

IPU

VOUT

High-to-LowLow-to-High

VOH

VOLVSS

VSS VDDVTLH VTHL

VIN

VPU

VTLH = trip voltage from low to high

VTHL = trip voltage from high to low

V23

VOUTMCP654X

VPU

R23 RF

+

- RPU


MCP6546/6R/6U/7/8/9
EQUATION 4-1:
Using this simplified circuit, the trip voltage can becalculated using the following equation:

EQUATION 4-2:

Figures 2-21 and 2-24 can be used to determine typi-cal values for VOL. This voltage is dependent on theoutput current IOL as shown in Figure 4-4. This currentcan be determined using the equation below:

EQUATION 4-3:

VOH can be calculated using the equation below:

EQUATION 4-4:

As explained in Section 4.1 “Comparator Inputs”, itis important to keep the non-inverting input belowVDD+0.3V when VPU > VDD.

4.5 Supply BypassWith this family of comparators, the power supply pin(VDD for single supply) should have a local bypasscapacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for goodedge-rate performance.

4.6 Capacitive LoadsReasonable capacitive loads (e.g., logic gates) havelittle impact on propagation delay (see Figure 2-27).The supply current increases with increasing togglefrequency (Figure 2-30), especially with highercapacitive loads.

4.7 Battery LifeIn order to maximize battery life in portableapplications, use large resistors and small capacitiveloads. Avoid toggling the output more than necessary.Do not use Chip Select (CS) too frequently, in order toconserve power. Capacitive loads will draw additionalpower at start-up.

4.8 PCB Surface LeakageIn applications where low input bias current is critical,PCB (Printed Circuit Board) surface leakage effectsneed to be considered. Surface leakage is caused byhumidity, dust or other contamination on the board.Under low-humidity conditions, a typical resistancebetween nearby traces is 1012Ω. A 5V differencewould cause 5 pA of current to flow. This is greaterthan the MCP6546/6R/6U/7/8/9 family’s bias current at25°C (1 pA, typical).

The easiest way to reduce surface leakage is to use aguard ring around sensitive pins (or traces). The guardring is biased at the same voltage as the sensitive pin.An example of this type of layout is shown inFigure 4-7.

FIGURE 4-7: Example Guard Ring Layout for Inverting Circuit.1. For the Inverting Configuration (Figures 4-4 and

4-7):a) Connect the guard ring to the non-inverting

input pin (VIN+). This biases the guard ringto the same reference voltage as thecomparator (e.g., VDD/2 or ground).

b) Connect the inverting pin (VIN–) to the inputpad, without touching the guard ring.

R23R2R3

R2 R3+-------------------=

V23R3

R2 R3+------------------- VDD×=

VTHL VPUR23

R23 RF RPU+ +----------------------------------------⎝ ⎠⎜ ⎟⎛ ⎞

V23RF RPU+

R23 RF RPU+ +---------------------------------------⎝ ⎠⎛ ⎞+=

VTLH VOLR23

R23 RF+-----------------------⎝ ⎠⎜ ⎟⎛ ⎞

V23RF

R23 RF+----------------------⎝ ⎠⎛ ⎞+=

VTLH = trip voltage from low to high

VTHL = trip voltage from high to low

IOL IPU IRF+=

IOLVPU VOL–

RPU--------------------------⎝ ⎠

⎛ ⎞ V23 VOL–R23 RF+------------------------⎝ ⎠

⎛ ⎞+=

VOH VPU V23–( )R23 RF+

R23 RF RPU+ +---------------------------------------⎝ ⎠⎛ ⎞×=

Guard Ring

VSSVIN- VIN+


MCP6546/6R/6U/7/8/9
4.9 Unused ComparatorsAn unused amplifier in a quad package (MCP6549)should be configured as shown in Figure 4-8. Thiscircuit prevents the output from toggling and causingcrosstalk. It uses the minimum number of componentsand draws minimal current (see Figure 2-15 andFigure 2-18).
FIGURE 4-8: Unused Comparators.

4.10 Typical Applications

4.10.1 PRECISE COMPARATOR

Some applications require higher DC precision. Aneasy way to solve this problem is to use an amplifier(such as the MCP6041) to gain-up the input signalbefore it reaches the comparator. Figure 4-9 shows anexample of this approach.

FIGURE 4-9: Precise Inverting Comparator.

4.10.2 WINDOWED COMPARATORFigure 4-10 shows one approach to designing awindowed comparator. The wired-OR connectionproduces a high output (logic 1) when the input voltageis between VRB and VRT (where VRT > VRB).

FIGURE 4-10: Windowed Comparator.

¼ MCP6549

VDD

–

+

VREF

VDD

VDD

R1 R2 VOUT

VIN

VREF

VPU

RPU

MCP6546

MCP6041

VRT

1/2

VRB

VIN

VPU

RPU

VOUT

MCP6547

1/2MCP6547


MCP6546/6R/6U/7/8/9

5.0 PACKAGING INFORMATION5.1 Package Marking Information

5-Lead SC-70 (MCP6546, MCP6546U) Example: (I-temp)

Device I-Temp Code

E-Temp Code

MCP6546 ACNN Note 2MCP6546U BBNN Note 2Note 1: I-Temp parts prior to March 2005 are

marked “ACN”2: SC-70-5 E-Temp parts not available at

this release of the data sheet.

Example: (I-temp)

ORAC25AC25 (Front)

148 (Back)

5-Lead SOT-23 (MCP6546, MCP6546R, MCP6546U) Example: (I-temp)

Device I-Temp Code

E-Temp Code

MCP6546 ACNN GWNNMCP6546R AHNN GXNNMCP6546U — AWNN

Note: Applies to 5-Lead SOT-23

AC25AC25

8-Lead PDIP (300 mil) (MCP6546, MCP6547, MCP6548, MCP6549) Examples:

ORMCP6546

I/P^^2561148

3e

MCP6546I/P256

1148

8-Lead SOIC (150 mil) (MCP6546, MCP6547, MCP6548, MCP6549)

ORMCP6547 MCP6547I/SN1148

256 256

S N ^^11483e

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e


MCP6546/6R/6U/7/8/9
Package Marking Information (Continued)
8-Lead MSOP (MCP6546, MCP6547, MCP6548) Example:

6546I148256

14-Lead PDIP (300 mil) (MCP6549) Example:

OR

OR

MCP6549-I/P1148256

1148256

1148256

MCP6549-E/P 3e

I/P^ 3̂eMCP6549



3e

3e


MCP6546/6R/6U/7/8/9
Package Marking Information (Continued)
XXXXXXXXXX

Example:14-Lead SOIC (150 mil) (MCP6549)

OR

MCP6549ISL1148256

MCP6549

1148256E/SL^ 3̂e

14-Lead TSSOP (MCP6549) Example:

MCP6549I

1148256



3e

3e


MCP6546/6R/6U/7/8/9

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1 2 3

e

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A

A1

A2 c

L

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�� -�� *��)


MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging


MCP6546/6R/6U/7/8/9

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MCP6546/6R/6U/7/8/9

APPENDIX A: REVISION HISTORY

Revision G (February 2012)The following is the list of modifications:

1. Updated the Package Types drawing to correctthe device representation of the SC-70 package.

2. Updated package temperatures in theTemperature Characteristics table.

3. Corrected the marking information table for the5-Lead SC-70 package (MCP6546 andMCP6546U) in Section 5.1, Package MarkingInformation.

4. Updated the package outline drawings inSection 5.1 “Package Marking Information”,to show all views for each package.

5. Minor editorial changes.

Revision F (September 2007)The following is the list of modifications:

1. Corrected polarity of MCP6546U SOT-23-5 pin-out diagram on the first page.

2. Updated package outline drawings inSection 5.1 “Package Marking Information”per Marcom.

Revision E (September 2006)The following is the list of modifications:

1. Added MCP6546U pinout for the SOT-23-5package.

2. Clarified Absolute Maximum Analog InputVoltage and Current Specifications.

3. Added application information on unusedcomparators.

4. Added disclaimer to package outline drawings.

Revision D (May 2006)The following is the list of modifications:

1. Added E-temp parts.2. Changed minimum pull-up voltage specification

(VPU) to 1.6V for parts starting Dec. 2004 (weekcode 52); previous parts are specified at aminimum of VDD.

3. Changed VHYST temperature specifications tolinear and quadratic temperature coefficients.

4. Changed specifications and plots to include E-Temp parts.

5. Added Section 3.0 “Pin Descriptions”.6. Corrected package markings (Section 5.1

“Package Marking Information”).7. Added Appendix A: “Revision History”.

Revision C (May 2003)• Undocumented changes.

Revision B (December 2002)• Undocumented changes.

Revision A (February 2002)• Original Release of this Document.


MCP6546/6R/6U/7/8/9
NOTES:

MCP6546/6R/6U/7/8/9

PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP6546: Single Comparator

MCP6546T: Single Comparator (Tape and Reel)(SC-70, SOT-23, SOIC, MSOP)

MCP6546RT: Single Comparator (Rotated - Tape and Reel) (SOT-23 only)

MCP6546UT: Single Comparator (Tape and Reel)(SC-70, SOT-23)(SOT-23-5 is E-Temp only)

MCP6547: Dual ComparatorMCP6547T: Dual Comparator

(Tape and Reel for SOIC and MSOP)MCP6548: Single Comparator with CSMCP6548T: Single Comparator with CS

(Tape and Reel for SOIC and MSOP)MCP6549: Quad ComparatorMCP6549T: Quad Comparator

(Tape and Reel for SOIC and TSSOP)

Temperature Range: I = -40°C to +85°CE * = -40°C to +125°C

* SC-70-5 E-Temp parts not available at this release of the data sheet.

Package: LT = Plastic Package (SC-70), 5-leadOT = Plastic Small Outline Transistor (SOT-23), 5-leadMS = Plastic MSOP, 8-leadP = Plastic DIP (300 mil Body), 8-lead, 14-leadSN = Plastic SOIC (150 mil Body), 8-leadSL = Plastic SOIC (150 mil Body), 14-lead (MCP6549)ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6549)

PART NO. –X /XX

PackageTemperatureRange

Device

Examples:a) MCP6546T-I/LT: Tape and Reel,

Industrial Temperature,5LD SC-70.

b) MCP6546T-I/OT: Tape and Reel, Industrial Temperature,5LD SOT-23.

c) MCP6546-I/MS: Tape and Reel, Industrial Temperature,8LD MSOP.

d) MCP6546-E/P: Extended Temperature, 8LD PDIP.

e) MCP6546-E/SN: Extended Temperature, 8LD SOIC.

a) MCP6546RT-I/OT: Tape and Reel, Industrial Temperature,5LD SOT23.

a) MCP6546UT-E/LT: Tape and Reel, Industrial Temperature,5LD SC-70

b) MCP6546UT-E/OT: Tape and Reel, Extended Temperature,5LD SOT23.

a) MCP6547-I/MS: Industrial Temperature,8LD MSOP.

b) MCP6547T-I/MS: Tape and Reel, Industrial Temperature,8LD MSOP.

c) MCP6547-I/P: Industrial Temperature, 8LD PDIP.

d) MCP6547-E/SN: Extended Temperature, 8LD SOIC.

a) MCP6548-I/SN: Industrial Temperature,8LD SOIC.

b) MCP6548T-I/SN: Tape and Reel,Industrial Temperature,8LD SOIC.

c) MCP6548-I/P: Industrial Temperature, 8LD PDIP.

d) MCP6548-E/SN: Extended Temperature, 8LD SOIC.

a) MCP6549T-I/SL: Tape and Reel, Industrial Temperature,14LD SOIC.

b) MCP6549T-E/SL: Tape and Reel,Extended Temperature,14LD SOIC.

c) MCP6549-I/P: Industrial Temperature,14LD PDIP.

d) MCP6549-E/ST: Extended Temperature, 14LD TSSOP.


MCP6546/6R/6U/7/8/9
NOTES:

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

© 2002-2012 Microchip Technology Inc.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2002-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-62076-019-2

DS21714G-page 43

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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