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MB87M3400

Fujitsu WiMAX 802.16-2004 SoC Application Guide

Revision: 1.4 (Initial Release)

Last Updated: November 15, 2005

Document # MB87M3400-DOC-04

Copyright © 2002–2003 Fujitsu Microelectronics America. All rights reserved. This file is protected by Federal Copyright Law, with all rights reserved. No part of this file may be reproduced, stored in a retrieval system, translated, transcribed, or transmitted, in any form, or by any means manual, electric, electronic, mechanical, electro-magnetic, chemical, optical, or otherwise, without prior explicit written permission from Fujitsu Microelectronics America.

This document contains proprietary information, and except with written permission of Fujitsu Microelectronics America, such information shall not be published, or disclosed to others, or used for any purpose, and the document shall not be duplicated in whole or in part.

The information contained herein may be preliminary and is subject to change.

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Revision History:

Rev Date Authors Description

1.4 11/15/05 R. Golshan / S. Azhar Release 1.0 – 11/15/05

MB87M3400

Fujitsu Microelectronics America, Inc.

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Table of Contents

1. Application Notes ..............................................................................................................................................................1

1.1 MB87M3400 Block Diagram ......................................................................................................................................11.2 Clock Generation for MB87M3400 and Synchronization of Clocks ..................................................................................2

1.2.1 Clock Requirements for MB87M3400 SoC...........................................................................................................21.2.2 Off-Chip Clock Oscillator Requirements for the MB87M3400 Internal PLLs ............................................................21.2.3 VCTCXO and AFC (Automatic Frequency Correction) ..........................................................................................31.2.4 DDS Requirements ...........................................................................................................................................31.2.5 Bandwidth Requirements ..................................................................................................................................31.2.6 Sampling Frequency (FS) Requirements for the ADC/DAC.....................................................................................31.2.7 How Does AFC Work in MB87M3400? ...............................................................................................................5

1.3 System Memory Interface............................................................................................................................................51.3.1 MB87M3400 Memory Controller .......................................................................................................................51.3.2 FLASH Memory Application .............................................................................................................................61.3.3 SDRAM Memory Application ............................................................................................................................71.3.4 SDRAM Organization ......................................................................................................................................81.3.5 Bus Shared by FLASH and SDRAM ...................................................................................................................81.3.6 SDRAM-related Programmable Registers ............................................................................................................9

1.4 Internal Mode and External Mode Operations ...............................................................................................................91.4.1 Internal Processor Mode ...................................................................................................................................91.4.2 External Processor Mode.................................................................................................................................10

1.5 MB87M3400 Radio Interface – Analog/Digital ...........................................................................................................161.5.1 MB87M3400 RF Interface Signals....................................................................................................................161.5.2 Connecting MB87M3400 SoC Board to the SiGe Radio Board .............................................................................161.5.3 Zero-IF Receiver.............................................................................................................................................171.5.4 Low-IF Receiver.............................................................................................................................................181.5.5 RF Interface On-chip ADC/DAC.......................................................................................................................191.5.6 RF System Test Plan .......................................................................................................................................30

1.6 AGC Operations ......................................................................................................................................................371.6.1 SS Receiver....................................................................................................................................................371.6.2 BS Receiver ...................................................................................................................................................37

1.7 AGC Table Calibration Lab Procedure ........................................................................................................................381.7.1 Summary ......................................................................................................................................................381.7.2 Requred Materials ..........................................................................................................................................381.7.3 AGC Operation ..............................................................................................................................................391.7.4 AGC Table Calibration Procedure .....................................................................................................................401.7.5 Verification....................................................................................................................................................401.7.6 Conclusion ....................................................................................................................................................41



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1.7.7 Appendix A – System Setup Calibration Procedure ............................................................................................. 411.7.8 Notes Regarding the AGC Calibration Procedure............................................................................................... 41

1.8 AGC Programming Table ......................................................................................................................................... 421.8.1 Default Values for AGC Related Registers .......................................................................................................... 421.8.2 AGC ATTENUATION TABLE (Pin vs AGC[9:0] ) .............................................................................................. 421.8.3 Results, Conclusions ...................................................................................................................................... 43

1.9 Tutorial on FRAME LENGTH CALCULATION for MB87M3400 802.16 SoC............................................................... 441.10 Data Endianness Considerations with DSI Bus Access ................................................................................................. 46

1.10.1 Word Access Through the DSI Bus .................................................................................................................. 461.10.2 Byte Access Through the DSI Bus ................................................................................................................... 47

1.11 Channel Delay Calculation ..................................................................................................................................... 481.12 VOIP Applications for MB87M3400 SoC.................................................................................................................. 48

1.12.1 VOIP Chip Sets Examples.............................................................................................................................. 501.13 T1/E1 Application................................................................................................................................................. 52

1.13.1 Introduction to T1/E1 .................................................................................................................................. 521.13.2 MPC8560 TDM Interface for T1/E1 Application .............................................................................................. 521.13.3 MPC8560 Communication Processor Module .................................................................................................. 531.13.4 Reference Board for T1/E1 ............................................................................................................................ 55

2. MB87M3400 Frequently Asked Questions........................................................................................................................... 56

2.1 FAQ on Standards, System Design and Testing ............................................................................................................ 562.2 FAQ on Testing and FTRP (Fujitsu Test/Reference Program)......................................................................................... 562.3 FAQ on Radio Interface ........................................................................................................................................... 572.4 FAQ on MB87M3400 Pins and Electrical Characteristics ............................................................................................. 572.5 FAQ on Fujitsu Reference Boards .............................................................................................................................. 592.6 FAQ on UMAC/LMAC Interface ............................................................................................................................... 60

3. 802-16-2004 OFDM PHY Performance ............................................................................................................................. 69

3.1 Introduction .......................................................................................................................................................... 693.2 BER Performance in AWGN ..................................................................................................................................... 693.3 System Implemantation Margin ................................................................................................................................ 69

4. Simulation Results Using SUI Channel Models .................................................................................................................... 70

4.1 SNR vs BER simulations of the 802.16d PHY ............................................................................................................ 704.2 SUI-1 Channel Model Simulation Results ................................................................................................................... 704.3 SUI-3 Channel Model Simulation Results ................................................................................................................... 72

5. Performance Measurements .............................................................................................................................................. 75

5.1 SiGe Radio Performance Testing ............................................................................................................................... 755.1.1 RF Performance Testing ................................................................................................................................. 75


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List of Figures

Figure 1:1 MB87M3400 SoC Block Diagram ............................................................................................................................1

Figure 1:2 Clock Generation for MB87M3400 SoC....................................................................................................................1

Figure 1:3 MB87M3400 System Memory Interface.....................................................................................................................6

Figure 1:4 MB87M3400 Application of 16-bit FLASH Memory .................................................................................................7

Figure 1:5 MB87M3400 Application of 4M x 32 SDRAM Memory..............................................................................................8

Figure 1:6 MB87M3400 Functional Signal Group in Internal Processor Mode ...........................................................................10

Figure 1:7 MB87M3400 in External Processor........................................................................................................................11

Figure 1:8 MB87M3400 External Processor Mode Pins............................................................................................................12

Figure 1:9 TDD or HDX FDD Reference Board Evaluation System Using External Processor .......................................................13

Figure 1:10 PowerPC External Mode (Full Duplex FDD Reference Board Evaluation System).......................................................14

Figure 1:11 PowerPC sub-system Block Diagram.....................................................................................................................14

Figure 1:12 MB87M3400 DSI Slave Interface and PowerPC Pin Mapping...................................................................................15

Figure 1:13 MB87M3400 RF Interface ..................................................................................................................................16

Figure 1:14 MB87M3400 Connections to SiGe Radio Board.....................................................................................................17

Figure 1:15 Down-Conversion in Zero-IF Receiver...................................................................................................................18

Figure 1:16 Down-Conversion in Low-IF Receiver ...................................................................................................................19

Figure 1:17 MB87M3400 Receive RF ADC Interface ................................................................................................................20

Figure 1:18 MB87M3400 Transmit RF DAC Interface ..............................................................................................................20

Figure 1:19 DC Offset Shift from Radio to SoC Board ..............................................................................................................21

Figure 1:20 Transistor-based DC Offset Shift from Radio to SoC Board.......................................................................................22

Figure 1:21 Transistor-based DC Offset Example from Reference Radio Board .............................................................................23

Figure 1:22 Buffer OP AMP for Peak-to-Peak and Offset Voltage Shift .......................................................................................24

Figure 1:23 DC Offset Shift from SoC Board to Radio Board.....................................................................................................25

Figure 1:24 MB87M3400 External ADC/DAC Signals from Reference Board Schematics...............................................................26

Figure 1:25 Digital RX I/Q Interface using External ADC ........................................................................................................27

Figure 1:26 Digital TX I/Q Interface using External DAC .........................................................................................................28

Figure 1:27 MB87M3400 High-Speed ADC Typical Application Circuit......................................................................................29

Figure 1:28 Spectral Mask Test Setup .....................................................................................................................................30

Figure 1:29 Spectral Flatness Test Setup .................................................................................................................................31

Figure 1:30 Receive Sensitivity Test Setup ...............................................................................................................................31

Figure 1:31 RSSI Test Setup..................................................................................................................................................32

Figure 1:32 CINR Test Setup.................................................................................................................................................32

Figure 1:33 MB87M3400 High-Speed ADC Typical Application Circuit......................................................................................33



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Figure 1:34 Maximum Receivable Signal Test Setup ................................................................................................................. 34

Figure 1:35 MB87M3400 AGC Loop in SS Receive Operation................................................................................................... 37

Figure 1:36 Example Radio Block Diagram Interface to MB87M3400 ....................................................................................... 39

Figure 1:37 Measurement Setup Diagram .............................................................................................................................. 40

Figure 1:38 Calibration Setup Diagram................................................................................................................................. 41

Figure 1:39 Splitter Loss Measurement.................................................................................................................................. 41

Figure 1:40 Word Access Example through DSI....................................................................................................................... 46

Figure 1:41 Byte Access Example through DSI ........................................................................................................................ 47

Figure 1:42 MB87M3400 Interface to a VOIP Chip ................................................................................................................. 48

Figure 1:43 VOIP based WiMAX System................................................................................................................................ 49

Figure 1:44 VOIP Module (MB87M3400-based) ..................................................................................................................... 49

Figure 1:45 CODEC VOIP Chip for MB87M34-based VOIP System ........................................................................................... 50

Figure 1:46 TI VOIP Chip for MB87M34-based VOIP System ................................................................................................... 51

Figure 1:47 FUJITSI VOIP Macro for MB87M34-based VOIP System........................................................................................ 51

Figure 1:48 MPC8560 Block Diagram with TDM Interface ...................................................................................................... 52

Figure 1:49 MPC8560 Communication Processor Module Block Diagram.................................................................................. 53

Figure 1:50 MPC8560 Serial Interface Block Diagram ............................................................................................................ 54

Figure 1:51 T1/E1 Application Example using Reference Board and PowerPC Module ................................................................. 55

Figure 3:1 BER plot for AWGN ............................................................................................................................................ 69

Figure 4:1 QAM64-3/4 BER vs SNR Simulation Plot .............................................................................................................. 70




Figure 4:5 QPSK-3/4 BER vs SNR Simulation Plot ................................................................................................................ 71

Figure 4:6 QPSK-1/2 BER vs SNR Simulation Plot ................................................................................................................ 71

Figure 4:7 BPSK-3/4 BER vs SNR Simulation Plot ................................................................................................................ 71

Figure 4:8 BPSK-1/2 BER vs SNR Simulation Plot ................................................................................................................ 72


Figure 4:10 QAM64-2/3 BER vs SNR Simulation Plot ............................................................................................................ 72



Figure 4:13 QPSK-3/4 BER vs SNR Simulation Plot .............................................................................................................. 73

Figure 4:14 QPSK-1/2 BER vs SNR Simulation Plot .............................................................................................................. 73

Figure 4:15 BPSK-3/4 BER vs SNR Simulation Plot............................................................................................................... 73

Figure 4:16 BPSK-1/2 BER vs SNR Simulation Plot............................................................................................................... 74


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Figure 5:1 Constellation Diagram of BPSK

3

/

4

.......................................................................................................................75

Figure 5:2 Error Data from VSA (BPSK

3

/

4

)...........................................................................................................................75

Figure 5:3 CCDF Curve from VSA (BPSK

3

/

4

) ........................................................................................................................75

Figure 5:4 Constellation Diagram of QPSK

3

/

4

.......................................................................................................................76

Figure 5:5 Error Data from VSA (QPSK

3

/

4

)...........................................................................................................................76

Figure 5:6 CCDF Curve from VSA (QPSK

3

/

4

) ........................................................................................................................76

Figure 5:7 Constellation Diagram of QAM16

3

/

4

....................................................................................................................76

Figure 5:8 Error Data from VSA (QAM16

3

/

4

) ........................................................................................................................76

Figure 5:9 CCDF Curve from VSA (QAM16

3

/

4

) ......................................................................................................................76

Figure 5:10 Constellation Diagram of QAM64

3

/

4

...................................................................................................................77

Figure 5:11 Error Data from VSA (QAM64

3

/

4

) ......................................................................................................................77

Figure 5:12 CCDF Curve from VSA (QAM64

3

/

4

) ....................................................................................................................77

List of Tables

Table 1-1: Channel Bandwidth Versus ADC/DAC Front End Clock ...............................................................................................4

Table 1-2: Shared Signals for Different Modes of Operation ......................................................................................................13

Table 1-3: Referenced Documents...........................................................................................................................................30

Table 1-4: Spectral Mask Test Vectors......................................................................................................................................30

Table 1-5: RCE Test Parameters .............................................................................................................................................31

Table 1-6: Receive Sensitivity Test Parameters ..........................................................................................................................32

Table 1-7: CINR Test Parameters ...........................................................................................................................................33

Table 1-8: Adjacent Channel Test Parameters ...........................................................................................................................33

Table 1-9: Spectral Mask Test Vectors......................................................................................................................................34

Table 1-10: Pin vs Attenuation and Corresponding AGC Output Values .......................................................................................43

Table 1-11: The Truth Table for DSI Bus Byte Access .................................................................................................................47

Table 3-1: Calculation of System Implementation Margin .........................................................................................................69

Table 5-1: Allowed Relative Constellation Error Versus Data Rate...............................................................................................75



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1. Application Notes

1.1 MB87M3400 Block Diagram

The following MB87M3400 System-on-a-Chip (SoC) block diagram (Figure 1:1) will be applicable in the discussions of this chapter.

Figure 1:1 MB87M3400 SoC Block Diagram

Figure 1:1 represents the SoC interface for developing a system with external off-chip components. The SoC interfaces with the following off-chip devices:

1. Clock generation components: VCTCXO, DDS

2. External memory: FLASH, SDRAM

3. RF interface board (for interfacing with a Radio Board)

4. Temperature sensor

5. External mode application processor (example: an external PowerPC-based system)

In the subsequent sections, application of these components will be described.

Notes:1. The PHY Macro only interfaces through the ARC Sub-SYSTEM to other parts of the SOC2. The PHY Macro Contains an Analog (or RF) Interface (also called the Analog Front End) 3. The PHY Macro can receive from and send data to ARC Sub-System at the same time.4. The External Processor shown here is only for External Mode use (when CMODE = 1)

ARM 926Sub-System(802.16 MAC)

PHYBase Band Processor

ADC

ADC

MemoryController

GPIO

SPI

I2C

DAC

DMAController

EthernetPHY

SDRAM

FLASH

DAC

DAC

RFInterface

I

Q

Q

I

PLL20 MHz

Reference Clock

DDS

ADC

10/100MAC

MACDMA

VCTCXO20MHz

PowerDetector

TemperatureSensor

2x Sample Clock

40/80/160MHz

16KBICache

4KBDCache

FECARC-Tangent RISC/DSPSub-System

64KBI-Store

32KBLD/ST

ARM GPIO

DES CRC

UARTDebug I/F

DebugPort

ETM/JTAG RS232 I/FJTAG

Debug I/F

JTAGDebug I/F

GPIOARC GPIO16KB

Scratch

AES

ExternalProcessor

Mode Select(Internal orExternal)


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1.2 Clock Generation for MB87M3400 and Synchronization of Clocks

The following subsections will describe clock generation with the MB87M3400 SoC.

1.2.1 Clock Requirements for MB87M3400 SoC

Figure 1:2 shows the clock generation and clock sources for the MB87M3400 SoC. The clock system within the SoC consists of the

three internal PLLs. These PLLs are contained within three clock logic blocks shown in Figure 1:2 as ARM PLL, PHY PLL, ARC PLL. Some external (off-chip) components are required for clock generation by the PLLs for the SoC.

Figure 1:2 Clock Generation for MB87M3400 SoC

1.2.2 Off-Chip Clock Oscillator Requirements for the MB87M3400 Internal PLLs

An external VCTCXO generates the 20 MHz REFCLK for the three PLLs which provide the three system clocks: ARM_CLK, ARC_CLK, PHY_CLK. In addition, sampling clocks for the (low-speed) ADC/DACs are generated from the internal ARM PLL (see Figure 1:2). The following are the typical frequency requirements for the correct operation of the three sub-systems in the chip:

ARM_CLK = 160 MHz, ARC_CLK = 160 MHz, PHY_CLK = 100 MHz.

In addition: AHB_CLK = 80 MHz, ADC/DAC_CLK = 10 MHz are provided by the ARM PLL.

The above clocks are programmable, and different frequencies can be selected by use of the PLL speed pins. The following example describes pin values to obtain typical frequencies.

ARMPLL

PHYPLL

ARCPLL

ARMSub-System

ARCSub-System

802.16-2004PHY

12- bit DAC(Low -Speed)

VCTCXO

(AFC Data)

(AFC Data)

(AFC Data)

DAC

ADC

12- bit ADC(Low -Speed)

DDS_CLK

ARC_GPIO (2-bit input)

(Selects DDS_CLK Frequency)MB87M3400 Blocks(802.16-2004 SOC)

Clock DivisorDDS

SPI Interface

SamplingFrequency (FS) x2

REFCLK (20 MHZ)

Incoming (Receive)

Analog Data

AFC Logic

MB87M3400 Clock Sources

80 MHZ

100 MHz

160 MHz

160 MHz

(AFC VCTCXO Control)

(for DDS FS Control)

10 MHz

80 MHz

Note: 1) Typical Clock Frequencies (MHz)

are shown for ARM, PHY, ARC PLLs Outputs and for DDS_CLK input to DDS.

2) Samples for AFC are initial sync samples of the received 802.16 Frame

Samples

for AFC

Outgoing (Transmit)

Analog DataData/Control

AR

M_C

LK

AD

C/D

AC

Clo

cks

AH

B_C

LK

PH

Y_C

LK

AR

C_C

LK

AR

C_C

LK

RE

FC

LK1

RE

FC

LK3

RE

FC

LK2

AR

C-A

RM

Sig

nals

PH

Y_C

LK

AR

C_C

LK

AD

C/D

AC

Clo

cks

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Example 1:

Typical frequency

requirements for the correct operation of the MB87M3400 three sub-systems (PHY, ARC, ARM) in internal mode:

REFCLK = 20 MHz

,

PLL1_S = 1

,

PLL1_SPEED[1:0] = 01

,

CMODE=0

ARM_CLK = 160 MHz, AHB_CLK/SDRAM_CLK = 80 MHz, ADC/DAC_CLK = 10 MHz

REFCLK = 20 MHz, PLL2_S = 1, PLL2_SPEED[1:0] =01, DDS_SEL[1:0] = 01

ARC_CLK = 160 MHz, DDS_CLK = 80 MHz

For

REFCLK = 20 MHz, PLL3_S = 1, PLL3_SPEED = 1

PHY_CLK = 100 MHz

Note:

Refer to Table 6-1, 6-2, and 6-3 of the MB87M3400 Datasheet (Revision 1) for programming details so that these frequencies can be

generated.

Note:

In addition to the VCTCXO for the internal PPLs, an external DDS provides the sampling frequency (clock) for the (high-speed) ADC/DAC (see Figure 1:2).

1.2.3 VCTCXO and AFC (Automatic Frequency Correction)

A 20 MHz VCTCXO provides the clock source for the three internal PLLs in the SoC, and a reference clock to feed the local oscillators in the RF circuit. A single clock source allows the entire system to be synchronized. The VCTCXO frequency adjustment is controlled by the PHY AFC function via 12-bit DAC. The PHY uses the incoming samples from the ADC to estimate frequency adjustments. The adjustments are passed via the ARC to ARM Sub-Systems to the 12-bit DAC which controls the VCTCXO

1

. AFC function is described in the MB87M3400 Datasheet Revision 1.

VCTCXO voltage control range is ±10 ppm (±200 Hz) with a frequency stability of ±4.5 ppm and phase noise of –145 dBc/Hz at 10 KHz or better.

1.2.4 DDS Requirements

An off-chip DDS (or programmable PLL) is required to generate th sampling frequency (FS) clock for the high-speed ADC and DACs. The requirements for DDS input clock frequency and requirements for DDS-generated ADC/DAC sampling frequency (FS) will be described in subsections 1.2.6.1 and 1.2.6.2.

Bit resolution of the DDS output frequency should conform to better than the bit resolution of the 12-bit DAC. As a general rule DDS output frequency should be less than 30% of input.

1.2.5 Bandwidth Requirements

The sampling frequency clock for the high-speed ADC and DAC is generated from an external programmable clock source (the above-mentioned DDS). The actual sampling frequency depends on the bandwidth of the system. Supported bandwidth range is 1.75 MHz to 20 MHz. Once a particular bandwidth is chosen for operation:

1. The external DDS must be programmed to generate the sampling frequency clock.

2. An appropriate low-pass filter needs to be designed to support the bandwidth. This type of filter is implemented in the Radio Board (see later subsections 1.5.5.3 and 1.5.5.4 and also Figure 1:22 and Figure 1:23 for low-pass use examples).

1.2.6 Sampling Frequency (FS) Requirements for the ADC/DAC

1.2.6.1

Input Clock Frequency Requirements for the External DDS

An external DDS provides the sampling frequency (FS) clock for the (high-speed) ADC/DAC. Input clock to the DDS (DDS_CLK) comes from the on-chip ARC PLL. Its frequency can be programmed through internal ARC GPIO pins. This input clock can be set to 40 MHz, 80 MHz, or 160 MHz.

Refer to Table 6-2 (ARC Clock, DDS Clock Frequencies) of the MB87M3400 Datasheet, Revision 1 for more details.

1. For example: In SoC Reference Board Schematics the signal VCTCXO_CNTL from MB87M3400 controls the VCTCXO.


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1.2.6.2 Sampling Frequency (FS) Requirements from the DDS

Sampling frequency (FS) depends on the bandwidth chosen for operation. The actual frequency depends on the data bandwidth the system is supporting. The sampling clock frequency is given by the following formula:

FS = floor (BW*n/0.008)*0.008BW = bandwidthn = sampling factor

The actual sampling clock (FECLK or front-end clock) to the ADC/DAC is of twice the frequency of the sampling frequency clock. That is, FECLK = FS x 2. This is because the OFDM PHY supports 2x oversampling. The value of the sampling factor (n = FS/BW) is given in the following table extracted from the IEEE 802.16-2004 standard. Using this table of sampling factors, FECLK values can be computed for various channel bandwidths (see Example 2 in the next subsection).

1.2.6.3 Sampling Clock Frequency Requirements for the ADC/DAC

ADC and DAC sampling rates must support the maximum data bandwidth of the system and oversampling requirements of the PHY. Maximum supported bandwidth is 20 MHz.

Example 2:

For a 20 MHz channel bandwidth, the front-end clock (FECLK) of 46.08 MHz to the ADC/DAC is computed as follows:

Sampling frequency = FS = (144/125) * 20.00 = 23.04MHz.

Since the PHY supports 2x oversampling, ADC/DAC sampling clock frequency (FECLK frequency) is 46.08 MHz. That is: FECLK = 23.04 MHz x 2 = 46.08 MHz.

We can use a SPI or GPIO to control DDS to generate the desired frequency for any particular BW.

The following table shows the 2 x FS (FECLK to ADC/DAC) values computed for various channel bandwidths:

Table 1-1:

Channel Bandwidth Versus ADC/DAC Front End Clock

Note:

The bandwidths are assumed to be selectable upon power-up of the chip and will be otherwise fixed during normal operation.

Channel Bandwidth (Mhz) Fs/Bw

1.5 86/75

3 86/75

5.5 316/275

1.75 8/7

3.5 8/7

7 8/7

10 144/125

14 8/7

20 144/125

Channel Bandwidth (Mhz) Fs/BwMax Uncoded Data Rate for

QAM-64 (Mbps)Max Coded Data Rate for

QAM-64 (Mbps)Front End (FECLK)

Clock Rate 2xFs (MHz)

1.5 86/75 7.6 5.7 3.44

3 86/75 15.3 11.5 6.88

5.5 316/275 27.4 20.6 12.64

1.75 8/7 8.7 6.6 4

3.5 8/7 17.5 13.1 8

7 8/7 34.9 26.2 16

10 144/125 49.9 37.4 23.04

14 8/7 69.8 52.4 32

20 144/125 96.8 72.6 46.08

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1.2.7 How Does AFC Work in MB87M3400?

There are two loops for frequency tracking but they operate independently:

1. The main AFC operation involves measuring the frequency offset from the long preamble. This frequency offset is measured by the PHY on one frame, and the correction is manually applied to the 20MHz VCTCXO for the next frame. It is important to mention that the VCTCXO is only adjusted by the SS when it is not transmitting or receiving a burst. Therefore, the VCTCXO is constant while the PHY is trans-mitting or receiving. The AFC is designed to remove any large frequency offsets between the BS and SS.

2. The other frequency correction block removes the remaining frequency offset error in the received burst by measuring the error of the amplitude and phase of the received pilot subcarriers. The internal frequency correction runs on the received data, and compensates for any phase offset in the digital domain and not adjusted through the VCTCXO.

3. The above two functions are not operating at the same time and do not interfere with each other.

Some AFC-related questions can be clearly answered:

Q: How many frames will be neeeded for AFC to settle down?

A: AFC is calculated on every long preamble, and the local oscillator clock is adjusted accordingly on the next frame.

Q: MB87M3400 estimates frequency every frame; does this mean MB87M3400 will reset its estimation and redo it again or will it average with the result from the previous one?

A: Yes, the AFC frequency offset is measured for each frame on the long preamble of the DL burst. The VCTCXO should be adjusted on the SS at the end of the frame, when it is not receiving or transmitting.

Q: At which point in a frame can the external VCXO be adjusted? (Is it end of frame?) There must be some timing requirement for the external VCXO adjustment.

A: We do not have any specific timing requirements for this. However, the VCTCXO must be adjusted such that it is stable when the SS is scheduled to receive or transmit a frame.

Q: How acurate of a frequency does AFC adjust to?

A: The PHY is typically able to detect frequency offsets as small as 40 Hz. It is up to the 12-bit DAC and VCTCXO to adjust the 20 MHz local oscillator to remove the frequency error between BS and SS.

Q: For each modulation type, what is the frequency offset requirement?

A: Allowable frequency offsets are not defined by modulation type, but by channel bandwidth. This is found in the 802.16-2004 standard in section 12.3.2; here’s the summary:

1.3 System Memory Interface

1.3.1 MB87M3400 Memory Controller

The system memory controller is derived from the MB87M3400 Memory Controller. The memory controller is a subblock of the ARM subsystem (see Figure 1:1). Figure 1:3 shows the system memory interface in detail:

BW (MHz)Max Allowable |BS-SS|

Frequency Difference (Hz)

1.75 156.25

3.5 312.5

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Figure 1:3 MB87M3400 System Memory Interface

In the FUJITSU Reference Board design, FLASH memory (Chip Select = ECS0#) has been used for initial system boot code. System memory is supported by SDRAM using ECS4# as the chip select.

In the next two subsections applications of FLASH memory and SDRAM memory are described.

1.3.2 FLASH Memory Application

FLASH memory is used for initial system boot up during power-on reset. FLASH memory is selected by assertion of ECS0# during power-on reset. The user has the choice of using 8-, 16-, or 32-bit by controlling the two MB87M3400 BOOT[1:0] pins. This is shown as follows:

When FLASH SELECT (

ECS#[0] is active)

BOOT[1:0] = 00

8 bit Flash/ROMBOOT[1:0] = 01

16 bit Flash/ROMBOOT[1:0] = 10

32 bit Flash/ROM

Note:

BOOT[1:0] is only used for applying ECS#[0] during system boot-up sequence. Other ECS# are programmable by internal registers.

Note:

For ECS#[5:1] pins, these pins are tri-stated during power-on reset. To avoid bus contention when sharing with FLASH/Boot ROM, external pull-up is required for pins ECS#[5:1].

FLASH/SRAM

FLASH/SRAM

ExternalPeripheral 0

SDRAM(Bank 0)

SDRAM(Bank 1)

ExternalPeripheral 1

Addr

ess

DATA

Cont

rols

MB87M3400 Memory Controller

ARM AHB

FUJITSU MB87M3400 802.16-2004 SOC

ECS0# ECS1# ECS2# ECS3# ECS4# ECS5#

MB87M3400 Memory Interface (Shared Bus)

• Supports maximum of 6 Memory Device with shared the address and data bus.

• Supports glue-less interface to Flash ROM, EPROM, SRAM, synchronous DRAM’s, and other peripherals

• FUJITSU Reference Design is used for illustration of the Interface• The Reference Design uses ECS#0 for 16-bit FLASH, and ECS4# for SDRAM

Applicable in Internal mode onlyPart of the ARM Sub-System

MB87M3400


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Figure 1:4 shows an example use of 16-bit FLASH with the MB87M3400 Memory Interface.

Figure 1:4 MB87M3400 Application of 16-bit FLASH Memory

1.3.3 SDRAM Memory Application

ECS#[5:4] pins are used for SDRAM when multiple external banks are used. In Reference Board design ECS#[4] has been used.

Figure 1:5 shows an example of a 4M x 32 SDRAM with the MB87M3400 Memory Interface.

SD_RAS#

SD_CAS#

SD_WE#

SD_RAS#

SD_CLK

SD_CKE

SD_DQM[3:0]/

EWE#[3:0]

ECS[5:0]#

ERE#

EALE#

ERDY#

EDATA[31:0]

EADR[25:17]

BOOT[1:0]EADR[16:0]

Set BOOT[1:0] = 01 (for 16 bit Flash/ROM)

32MBit(2M x 16)FLASHMemory

EDATA[15:0]

ECS0#

EADR[23:0]

Notes: During BOOT-UP1) ECS#0 is active2) Set BOOT[1:0] = 01 if 16-bit FLASH is used3) To avoid bus contention when sharing with

FLASH/Boot ROM, external Pull-up is required for pins SD_RAS#, SD_CAS#,EWE#[3:0], ECS#[3:0] (because these pins are tri-stated and must be driven high during Power-on reset)

3) EADDR,EDATA Bus are shared with SDRAM

4) ERE# - External Device Read Enable (Output).This signal is asserted for external device read operations.

OE#

DQ[15:0]

A[24:1]

ERE# (LBW/RD#)

RP# PRESET#

CE1#CE2#

GNDGND

WE#SD

RAM

Inte

rface

A[0]

FUJITSUMB87M3400802.16-2004SOC

SystemMemoryInterface

EWE0#

(not needed for FLASH ROM, needed for Custom Device)

CE0#

BYTEGND3.3V

OPEN

Note: In Reference Board design, BYTEGND is tied to 3.3V, (A0 may float) for 16-bit access.


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Figure 1:5 MB87M3400 Application of 4M x 32 SDRAM Memory

1.3.4 SDRAM OrganizationThe above example shows the use of a 4M x 32 SDRAM. The SDRAM organization is as follows:

4Mx32 4 Banks x 32 Organization4Mx32 4 Banks x 128 M x 32 Bits4Mx32 4096 Rows x 256 Columns x 4 Banks x 32 Bits

Note: EADDR[11:0] decodes 4096 rows, EADDR[7:0] decodes 256 columns, EADDR[14:13] decodes 4 banks.

1.3.5 Bus Shared by FLASH and SDRAM These shared signals are as follows (from the MB87M3400 Datasheet, Revision 1):

SD_RAS#

SD_CAS#

SD_WE#

SD_CLK

SD_CKE

SD_DQM[3:0]/

EWE#[3:0]

ECS[5:0]#

ERE#

EALE#

ERDY#

EDATA[31:0]

EADR[25:17]

BOOT[1:0]

FUJITSUMB87M3400802.16-2004SOC

SystemMemoryInterface

EADR[16:0]

SDRAM

SD_CKE LOGIC HIGH***

(4M x 32)

ECS4#

EADR[11:0]DQ[31:0]

A[11:0]EADR[14:13]BA[1:0]

CS#

SD_RAS#

SD_CAS#

SD_WE#

SD_CLK

DQM3DQM2DQM1DQM0

SD_WE3#SD_WE2#SD_WE1#SD_WE0#

4M X 32 SDRAM*** for next Revision of the Chip, this pin needs to be connectedto MB87M3400 SD_CKE Pin

(for Flash/ROM)

(not needed for SDRAM, needed for Custom Device)

(not needed for SDRAM, needed for Flash/ROM)

Notes: 1. EADDR, EDATA, ECS# Bus are also shared with the FLASH memory.2. Refer to MB87M3400 Datasheet, Revision 1, and Chapter 2 (Memory and External Device Interface Section)

for detailed SDRAM related pin descriptions.3. Refer to MB87M3400 Datasheet, Revision 1, and Chapter 3 (Memory Controller Section) for SDRAM

programming details.

MB87M3400

Fujitsu Microelectronics America, Inc. 9Confidential

Chip Selectt (ECS#[5:0]):

Address Bus:

Data Bus:

Refer to Table 2-2 of the MB87M3400 Datasheet (Revision 1) for complete description of the memory and external device interface signals.

1.3.6 SDRAM-related Programmable RegistersIn order for the SDRAM memory to work for a particular application, a number of SDRAM memory control registers have been defined. These programmable registers are described in Chapter 3 of the MB87M3400, Revision 1. In most cases, the reset values of these registers are sufficient for a given operation.

1.4 Internal Mode and External Mode Operations1.4.1 Internal Processor ModeCMODE pin is set to 0 for this mode. In this mode, the ARM-926 CPU and subsystem is used to run the 802.16 Upper MAC. The MB87M3400 block diagram shown in Figure 1:1 is applicable in this mode with the exception that 1) the external processor interface (using the DSI bus) is disabled and 2) the external PowerPC is not there. This mode is most common for Subscriber Station (SS) applications.

Internal Processor Mode:ECS#[5:0]

External Processor Mode:ECS#[5]= LB_CS#ECS#[4]=LB_RDYMODEECS#[3]= reservedECS#[2:0]= LB_SIZE[2:0]

I/O 4mA External Device Chip Select (Outputs). Active low signals.FLASH: ECS#[0] used for FLASH.Other Devices: ECS#[3:1] used for other devicesSDRAM: ECS#[5:4] used for SDRAM when multiple external banks are used.

For ECS#[5:1] pins, these pins are tri-stated during power-on reset. To avoid bus contention when sharing with FLASH/Boot ROM, external pull-up is required for pins ECS#[5:1].

EADDR[25:17] O 4mA External Device Upper Address Bus (Output). This is the address bus shared by FLASH and external devices.

Internal Processor Mode:EADDR[16:0]

I/O 4mA External Device Lower Address Bus (Output). This is the address bus shared by SDRAM, FLASH, and external devices (output only)EADDR[12:0] : SDRAM addressEADDR[14:13] : SDRAM bank select.

External Processor Mode: LB_ADDR[16:0]

Local Bus Address (Input). Address bus bits 16-0 for the local bus (DSI) interface used by external host processor to access the internal address space of ARC Code RAM (64Kbyte) & Load/Store RAM (32Kbyte). – Input Only.

Internal Processor Mode:EDATA[31:0]

I/O 4mA External Device Data Bus (I/O). This is the data bus shared with SDRAM, FLASH, and other external devices.

External Processor Mode: LB_DATA[31:0]

Local Bus Data (I/O). Data bus bits 31-0 for the local bus (DSI) interface used by external host processor for data transfer between host and ARC Code RAM and Load/Store RAM. In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave (ARC) drives the valid data on this bus.


10 Fujitsu Microelectronics America, Inc. Confidential

Figure 1:6 MB87M3400 Functional Signal Group in Internal Processor Mode

1.4.2 External Processor ModeCMODE is set to 1 for this mode. It is typically used for BS implementation where more processor power may be needed. In this mode, the ARM-926 CPU and subsystem is disabled. An external Processor is connected to the Direct Slave Interface (DSI)2 of the MB87M3400 Chip. With DSI, the External Processor is the master

and the MB87M3400 chip is slave. The physical pins of the DSI signals are shared with the external memory bus as it is disabled in external processor mode. In this application, the 802.16 Upper MAC runs on a more powerful External Processor.

SD_RAS#SD_CAS#SD_WE#SD_CLKSD_CKE

SD_DQM[3:0]/EWE#[3:0]ECS#[5:0]

ERE#EALEERDY

EDATA[31:0]EADDR[25:0]

BOOT[1:0]

AGC_CTRL[9:0]AGC_STROBERF_ENABLELD#LDTX_ENRX_ENTR_SW

BS_SYNC_INBS_SYNC_OUTFT_IN

TX_PWR_DETECTRX_PWR_DETECT

ATX_I_OUTpATX_I_OUTnDTX_I_OUT[9:0]ATX_Q_OUTpATX_Q_OUTn

DTX_Q_OUT[9:0]

ADC_DAC_CLK

ARX_I_IN+ARX_I_IN-DRX_I_IN[9:0]ARX_Q_IN+ARX_Q_IN-DRX_Q_IN[9:0]

SED_OUT_CLKSED_OUT_DATA SED_OUT_FS

ARC_TDIARC_TMSARC_TCKARC_TDOARC_SS1

ARM_BYPASSSYNCARM_NTRSTARM_TMSARM_TCKARM_TDIARM_TDOARM_RTCK

TRACECLKTRACEPKT[7:0]TRACESYNCPIPESTAT[2:0]

JTCKJTDIJTMSJTRSTJTDO

ADC2_VRHADC2_VRLADC2_VR

DAC2_VRHDAC2_VRL

DAC_I_VRODAC_I_VREFDAC_I_COMPDAC_Q_COMP

ADC_I&Q_VREFADC_I&Q_VRHADC_I&Q_VRLADC_I&Q_SG

ExternalMemoryInterface

Ethernet PHYInterface

RadioInterface

ARC DebugPort

ARC JTAGPort

VoltageReferences

ARM ETM(Debug)

Port

JTAGBoundary

ScanClocks&

Reset

Power

Peripherals &InterruptsInterface

MB87M3400

(InternalProcessor

Mode)

MII_TXD[3:0]MII_TXENMII_TXER

MII_TXCLKMII_RXD[3:0]

MII_RXDVMII_RXER

MII_RXCLKMII_COLMII_CRSMII_MDC

MII_MDIOMII_LINK#

MII_FD#MII_100M#

MII_conn

SPI_DISPI_DO

SPI_CLKSPI_CS[2:0]#

SDASCL

ARM_GPIO [24:0]ARM_EXT_IRQ[1:0]

DDS_CLK_OUTSAMPL_CLK_2XVCTCXO_CNTL

REFCLK1PLL1_S

PLL1_SPEED[1:0]PLL1_VDDPLL1_VSS

REFCLK2PLL2_S

PLL2_SPEED[1:0]PLL2_VDDPLL2_VSS

REFCLK3PLL3_S

PLL3_SPEEDPLL3_VDDPLL3_VSS

PWR_RESET#EXT_RESET#

CMODEVPD

Digital 3.3VDigital 1.8V

Analog 3.3VAnalog 1.8V

Digital GroundAnalog Ground

ARC_GPIO[3:0]ARC_EXT_IRQ#[1:0]

PTEST

UART_TXDUART_RXDUART_CTSUART_RTS

LBCLK (for BS Mode)

2. DSI Bus Interface is described in subsequent subsections

MB87M3400


1.4.2.1 MB87M3400 Disabled Blocks in External ModeA number of ARM AHB and APB peripherals are disabled during

External Mode. The following Figure shows the disabled blocks in the MB87M3400 when used in external Mode.

Notes:

Figure 1:7 shows:

1. An external processor (like the PowerPC) is interfaced using the DSI Bus

2. Disabled Blocks: AHB Peripherals (FLASH, SDRAM, Memory Controller), all ABP Peripher-als, Network Interface, Debug Ports

3. Disabled Blocks need to be supported by the External Processor sub-system (like the Pow-erPC sub-System) that replaces the on-chip ARM Sub-System. That is, the External Proces-sor Board needs to provide many of the disabled blocks of the MB87M3400 SoC.

Figure 1:7 MB87M3400 in External Processor

1.4.2.2 MB87M3400 External Processor Mode PinsThe following diagram shows the Pins applicable when using MB87M3400 in External Mode Note: (the pins of the DSI Bus are needed to interface an external processor):

ARM 926Sub-System(802.16 MAC)

PHYBase Band Processor

ADC

ADC

MemoryController

GPIO

SPI

I2C

DAC

DMAController

AP

BEthernetPHY

SDRAM

FLASH

DAC

DAC

RFInterface

I

Q

Q

I

PLL20 MHz

Reference Clock

DDS

ADC

AH

B

10/100MAC

MACDMA

VCTCXO20MHz

PowerDetector

TemperatureSensor

2x Sample Clock

40/80/160MHz

16KBICache

4KBDCache

FECARC-Tangent RISC/DSPSub-System

64KBI-Store

32KBLD/ST

ARM GPIO

DES CRC

UARTDebug I/F

DebugPort

ETM/JTAG RS232 I/FJTAG

Debug I/F

JTAGDebug I/F

GPIOARC GPIO

DS

I

16KBScratch

AES

ExternalProcessor

Mode Select(Internal orExternal)

In External Processor Mode:1. The ARM926, AHB Bus peripherals, ARM Debug I/F, ETM/JTAG are disabled.2. Mode Select Must be set to External (i.e.; CMODE = 1)

(RS232 IF: from External Processor or PowerPC)

(GPIO IF: from External Processor or PowerPC)

(I2C IF: from External Processor or PowerPC)

(SPI IF: from External Processor or PowerPC)

(DAC IF: from External Processor or PowerPC)

(ADC IF: from External Processor or PowerPC)

from PowerPC

Part

of P

ower

PC



Figure 1:8 MB87M3400 External Processor Mode Pins

MB87M3400 Datasheet, Revision 1 contains full descriptions of these Pins.

Note: Local Bus DSI Interface Pins are shared Pins. See Table 1-2: Shared Signals for Different Modes of Operation in later subsection for a listing of the shared DSI Pins. MB87M3400 Datasheet, Revision 1 contains full descriptions of the shared pins.

1.4.2.3 MB87M3400 Unconnected Pins in External ModeIn External Mode, the ARM subsystem and the module linked to AHB and APB bus are wholly bypassed. The pins for MII port, ARM GPIO, ARM JTAG, RS232 I/F, I2C, SPI, PLL1, DAC for VCTCXO control, ADC for Power Detector are unused. Proper terminations must be provided for unconnected Pins as explained in the MB87M3400 Datasheet, Revision 1.

An example unconnected-pins file is also available that describes the terminations of the unused pins.

1.4.2.4 DSI Bus for External ModeDirect Slave Interface (DSI) is a synchronous interface that can be

connected to a bus interface running at a different clock frequency from the ARC bus. The ARC bus runs at 160MHz; for optimum data transfer, the external processor bus should a multiple of 80MHz. With bus systems greater than 80MHz, a bus clock divider reduces the bus clock feeding into the DSI. For example, a bus running at 160MHz will require a divide-by-2 clock divider. Synchronizing logic synchronizes the external processor data transfer at the beginning of the DSI clock cycle and also generates wait signals to extend data latency over the DSI clock cycle.

In the external processor configuration an external processor (such as Motorola PowerPC) running the 802.16 MAC layer can be connected to DSI (Direct Slave Interface) of Fujitsu’s MB87M3400 SoC. For a FDD BS, two MB87M3400 SoCs can be connected to the same DSI bus. In this case, the external processor will be master and the SoCs will be slave.

The physical pins of DSI interface are shared with the external memory bus, which is disabled in the external processor mode. The following table contains the list of the shared pins:

LB_CLKLB_SIZE[2:0]LB_BE#[3:0]

LB_CS#LB_W/RD#

LB_RDYMODELB_RDY#

LB_DATA[31:0]LB_ADDR[16:0]

AGC_CTRL[9:0]AGC_STROBE

RF_ENABLELDLD#TX_ENRX_ENTR_SW

BS_SYNC_INBS_SYNC_OUTFT_INTATX_I_OUTpATX_I_OUTn

DTX_I_OUT[9:0]ATX_Q_OUTpATX_Q_OUTn

DTX_Q_OUT[9:0]ADC_DAC_CLKARX_I_INpARX_I_INnDRX_I_IN[9:0]ARX_Q_INpARX_Q_INnDRX_Q_IN[9:0]

SED_OUT_CLKSED_OUT_DATASED_OUT_FS

DAC_I_VRODAC_I_VREFDAC_I_COMPDAC_Q_COMP

ADC_I&Q_VREFADC_I&Q_VRHADC_I&Q_VRLADC_I&Q_SG

JTCKJTDIJTMSJTRSTJTDO

ARC_GPIO[3:0]ARC_EXT_IRQ#[1:0]

REFCLK3PPL3_S

PLL3_SPEEDPLL3_VDDPLL3_VSS

PWR_RESET#EXT_RESET#

CMODEVPD

ARC_TDIARC_TMSARC_TCKARC_TDOARC_SS1

Digital 3.3VDigital 1.8V

Analog 3.3VAnalog 1.8V

Digital GroundAnalog Ground

DDS_CLK_OUTSAMPL_CLK_2X

PTEST

MB87M3400

(ExternalProcessor

Mode)

Local BusDSI

Interface

ARCInterrupts &

GPIO

RadioInterface

VoltageReferences

JTAGBoundary

Scan

Clocks&

Reset

ARC DebugPort

Power

MB87M3400


Table 1-2: Shared Signals for Different Modes of Operation

Details of DSI can be found under the section “ARC Sub-system Specifications” of the MB87M3400 Datasheet, Revision 1.

The following two examples show external mode using PowerPC.

1.4.2.5 PowerPC ExamplesIn the external processor configuration an external processor running the 802.16 MAC layer (such as Motorola PowerPC MPC8560) can be connected to DSI (Direct Slave Interface) of Fujitsu’s MB87M3400 SoC. Two examples of using PowerPC as the external processor are shown below:

1.4.2.5.1 TDD/HDX FDD and Full Duplex FDD ConfigurationsFigure 1:9 shows an example of Reference Board using an external PowerPC processor for TDD (or HDX FDD) application:

Figure 1:9 TDD or HDX FDD Reference Board Evaluation System Using External Processor

For a full-duplex FDD BS, two MB87M3400 SoCs can be connected to the same DSI bus. In this case, the external processor will be master and the SoCs will be slave. This is shown in Figure 1:10:

Internal Processor Mode External Processor Mode

ECS#[5] LB_CS#

ECS#[2:0] LB_SIZE[2:0]

EWE[3:0] LB_BE#[3:0]

EADDR_L[16:0] LB_ADDR[16:0]

ECS#[4] LB_RDYMODE

ERE# LBW/RD#

ERDY LB_RDY#

EDATA[31:0] LB_DATA[31:0]

Radio Module

DDSSPI

FS Clock Clock IN

Radio ModuleVCTCXO

Reference Board(External Processor Configuration)

PowerPCDebug Port

NetworkInterface

Temp.Sensor

FLASH

DDRSDRAM

I2CPowerPCMPS8560

PowerPC Module(MPC8560)

DSIAerMANFujitsuChip

Power Module

Radio Module

DDSSPI

FS Clock Clock IN

Radio ModuleVCTCXO


PowerPCDebug Port

NetworkInterface

Temp.Sensor

FLASH

DDRSDRAM

I2CPowerPCMPS8560


PowerPCDebug Port

NetworkInterface

Temp.Sensor

FLASH

DDRSDRAM

I2CPowerPCMPS8560


DSIMB87M3400FujitsuChip

Power Module



Figure 1:10 PowerPC External Mode (Full-Duplex FDD Reference Board Evaluation System)

1.4.2.5.2 PowerPC System Block DiagramFigure 1:11 shows a more detailed block diagram of the PowerPC (MPC8560) subsystem that can replace the ARM subsystem in external mode.

Note: System memory and many disabled ARM peripherals are now provided by the PowerPC subsystem.

Figure 1:11 PowerPC Subsystem Block Diagram

DDS

VCTCXO

FujitsuWiMAX

Chip

DDS ClockFS Clock

Clock

FujitsuWiMAX

Chip

FS Clock

Clock

DSI

RX Radio

TX Radio

PowerPCDebug Port

NetworkInterface

Temp.Sensor

FLASH

DDRSDRAM

I2CPowerPCMPS8560


SPI Control

CPM -SerialCommunicationInterface

T1/E1Interface

1.2V for MPC8560 Core

MPC8560Communication Processor

JTAG

I2C

TSEC1

TSEC2

DDRController

CPM

DDRSODIMM256MB

DDR, 64-bit, 2.5V I/O

RS232Xícvr UARTMicro DB9

LXT971A10/100PHY

MIIRJ45

CPM_PA

MIC

TO

RE

XP

AN

SIO

N38

-PIN

CPM_PB

CPM_PD

MIC

TO

RE

XP

AN

SIO

N15

2-P

IN GPCM /UPMLocal Bus, Debug, Ethernet Media Interface

FLASH8MB

GlueLogic

Loca

l Bus

POWERCONNECTOR

(for Debug)

POWERSUPPLY

2.5V for DDR SDRAM

CLOCKGENERATION

MPC8560 SysClock

25MHz Clocks for PHYs

JTAGHEADER

I2CEEPROM

MarvellMV88E101110/100/1000

PHY

GMII RJ45

RapidI/O

PCI-X

MAX6721Reset Generatorwith Watchdog

Reset from Baseboard

VCC3

MB87M3400


1.4.2.5.3 PowerPC System Features(from Motorola PowerPC Rreference Manual):

1. High performance super scalar 32-bit Book E e500 processor core

2. OceaN (On Chip Network) switch fabric

3. Integrated 4 channel DMA & EPIC controller

4. 64-bit, 166 MHz, 2.5 V I/O, DDR SDRAM interface, supports up to 4GB.

5. 64-bit, 133 MHz, PCI-X 1.0 compatible interface

6. 64-bit, 66 MHz, PCI-2.2 compatible interface

7. 8-bit, 500 MHz, LVDS, rapid I/O interface

8. Communication Processor Module

9. Triple Speed (10/100/1000 Mbps) Ethernet Controller

10. 32-bit multiplexed address & data bus, 166 MHz, Local Bus*, supports up to 8 MB flash memory.

11. I2C interface

12. IEEE 1149.1 compatible JTAG interface

13. 4 wire dual UART

* Local Bus3 (through UPM) – is used to connect PowerPC to the DSI bus.

1.4.2.5.4 PowerPC/DSI Bus Signal ConnectionsFigure 1:12 shows the exact pin-to-pin mapping of the MB87M3400 DSI slave interface and the corresponding pins on the PowerPC:

Figure 1:12 MB87M3400 DSI Slave Interface and PowerPC Pin Mapping

DSI slave pins from the MB87M3400 SoC are shared pins. Refer to Table 1-2: Shared Signals for Different Modes of Operation to see the DSI shared pins of the MB87M3400.

3. See MPC8560RM (Motorola PowerPC Rreference Manual), Chapter 12 for Local Bus Details.

LB_CS#LBW/RD#

LB_CLK

LB_RDY_MODE

AEC_EXT_IRQ#0

LB_DATA[31:0]

LB_ADDR[16:0]

LB_SIZE[2:0]

LB_BE#[3:0]

MB87M3400DSI SLAVEPowerPC

LATCH

LCS0

LGPL3

LBCLK0

IINT0

LAD[0:31]

LGPL[2:0]

LBS[0:3]

LUPWAIT

LSYNC_OUT

LSYNC_IN



1.5 MB87M3400 Radio Interface – Analog/Digital1.5.1 MB87M3400 RF Interface SignalsThe MB87M3400 RF Interface contains signals that connect the

SoC to a Radio Board. The SoC Reference Board contains a connector for this Radio Board interface. A SoC level interface diagram is shown in Figure 1:13.

Figure 1:13 MB87M3400 RF Interface

This interface shows the following category of RF signals:

1. ADC/DAC signals

a. Internal I and Q DAC analog interfaceb. Internal I and Q ADC analog interfacec. Digital interface to optionally usable external I and Q

DACd. Digital interface from optionally usable external I and Q

ADC

2. AGC control signals

3. RF PLL unlock status signals

4. Transmitter/receiver control signals

5. External 12-bit serial DAC interface

6. Base station synchronization signals

7. Transmitter/receiver power detection signals

Reference Board schematics that contain the signals are indicated in Figure 1:13 above.

The RF Interface pins can be identified at the Reference Board level; the next subsection shows the signals of the RF Interface at the Reference Board. This is reproduced from the Reference Radio Board and SoC Reference Board schematics.

1.5.2 Connecting the MB87M3400 SoC Board to the SiGe Radio BoardA separate Radio Board exists for the radio block that needs to be connected to the SoC Reference Board. The MB87M3400 Reference Board RF Interface contains a connector (RF Board Connector) to the Radio Board. Figure 1:14 shows the connections to the Radio Board:

MB87M3400

RFInterface

DTX_I_OUT[9:0]

DTX_Q_OUT[9:0]

DRX_I_IN[9:0]

DRX_Q_IN[9:0]

ATX_I_OUTp

ATX_I_OUTn

ATX_Q_OUTp

ATX_Q_OUTn

ARX_I_OUTp

ARX_I_OUTn

ARX_Q_OUTp

ARX_Q_OUTn

Optional Digital I and Q Output to externalI and Q DAC (reference shows jumpers for bypass)(see Sheet 3,10 Reference Board Schematics)

Analog Outputs from InternalI and Q DAC to Radio Board(see Sheet 3,10,12 Reference Board Schematics)

Optional Digital I and Q Input from externalI and Q ADC (if used)(see Sheet 3,10 Reference Board Schematics)

Analog inputs to InternalI and Q ADCfrom Radio Board(see Sheet 3,10,12 Reference Board Schematics)

ADC_DAC_CLK Sampling Clock for the optionally usable External ADC/DAC(see Sheet 3,10 Reference Board Schematics)


External 12-bit serial DAC Interface(used for test purpose)

AGC_CTRL[9:0]

AGC_STROBE

LD

LD#

TX_ENRX_EN

RF_ENABLE

BS_SYNC_INBS_SYNC_OUTFT_INT

Base Station Synchronization

AGC Control(to Radio Board, see note 2)

External Processor Enables RF Circuit

Indicates if RF PLL is unlocked(when asserted, from Radio Board)

TR_SW

TX_EN enables TransmitterRX_EN enables ReceiverTR_SW allows switch betweenTransmitter and Receiver(to Radio Board)

TX_PWR_DETECTRX_PWR_DETECT

Notes:1) Only LD# have a connection to Radio Board; LD is an NC for the RF Board2) AGC_STROBE can be used to strobe data on AGC_CTRL[9:0]. It is not used in Reference Radio Board Design.3) RX_PWR_DETECT not used in current implementation4) In addition to above signal;s, the Radio Board uses SPI, I2c, and some ARM GPIO signals for its control.

Tx/RX Power Detection(from Radio Board, see note 3)

MB87M3400


Figure 1:14 MB87M3400 Connections to SiGe Radio Board

This connection accommodates the following category of RF signals:

1. ADC/DAC connections to and from the Radio Board

2. ARMGPIO7 for external LNA_SW control (LNA = Low Noise Amplifier)

3. AGC_CTRL[9] for SE7351L LNA_SW control

4. AGC_CTRL[8:6] for RF stage RX gain control using 0.5dB steps

5. AGC_CTRL[8:6] for RF stage TX gain control using 0.5dB steps

6. AGC_CTRL[5:0] for IF stage RX gain control

7. RX_EN to enable receiver

8. LD# to detect RF PLL UnLOCK

9. SDA, SDL for temperature sensing

10. TX_PWR_DETECT for transmitter detection

11. TX_EN for enabling transmitter and external Power Amplifier (PA)

12. ARMGPIO24 for gain control of external power amplifier (PA)

13. SPI_DO, SPI_CLK, SPI_CS[1]# for gain control of TX/RX

14. ARMGPIO22 for power down of SE7051L circuit

1.5.3 Zero-IF ReceiverIn a zero-IF (ZIF) receiver the incoming signal is converted related to baseband (i.e. the IF = 0). This conversion is performed using a quadrature down-converter (a “sine” and “cosine” or, mathematically, a complex exponential = e^(jωτ)).

The advantages of a zero-IF receiver:

1. No high-Q bandpass IF filter (an off-chip component) is required

2. Channel selectivity is performed using integrated baseband filters (as shown in Figure 1:15).

MB87M3400/Radio BoardConnections

ARX_I_IN+ARX_I_IN-

ARX_Q_IN+ARX_Q_IN-

ATX_I_OUT+ATX_I_OUT-

ATX_Q_OUT+ATX_Q_OUT-

SPI_DOSPI_CLKSPI_CS[1]#

Data(SPI_DO)CLK(SPI_CLK)LE(SPI_CS[2]#

Rx_I+ (ARX_I_IN+)

RX_ I- (ARX_I_IN-)

Rx_Q+ (ARX_Q_IN+)

RX_ Q- (ARX_Q_IN-)

Tx_I+ (ATX_I_OUT+)TX_ I- (ATX_I_OUT-)

Tx_Q+ (ATX_Q_OUT+)TX_ Q- (ATX_Q_OUT-)

SE7351LSAW

SAW

RF Modulator/De_modulator

LD_RF_PLLLD_IF_PLL

NANDLD_PLL#(LD#)

ARMGPIO22 PD_SE7051L(Spare_EN_A2)TX IF Gain Control50dB of range with 1dBResolution. Controlled via SPI REG C, Bits D1-D6

Modulator Gain Control12dB of range with 6dBResolution. Controlled via SPI REG C, Bits D11-D14

CSDACSCL

TemperatureSensor

SDL_VTTMP (SDL)SCL_VTTMP (SCL)

From Low-Speed DAC20MHz_REF_CLOCKVCTCXO

VCTCXO_CNTL(VCTCXO_CNTL)PLL_Ref_Freq (20MHz_REF_CLK

ARMGPIO24TX_PWR_DETECT

ATT20 (ARMGPIO24)PWR_DET(TX_PWR_DETECT)

3.3VDCRx 5.0VDCTx 5.0VDC5.0VDC_PA

DC Regulation6.5V (1.5A)

8.5V (1.0A)

TX_ENARMGPIO11

TR_SWARMGPIO7

Tx_EN (TX_EN)

ANT_SWT/R_SW (TR_SW)

Ext_LNA_EN (GPIO[7])AGC_CTRL[9]AGC_CTRL[8:6]

RX_ENAGC_CTRL[5:0]

LNA_SW (AGC_CTRL[9])

FE_AGC[2:0] (RX_ATTN[2:0])Rx_EN (RX_EN)

RX_AGC[5:0] (AGC_CTRL[5:0])

Rx IF Gain Control50dB of range with 1dBResolution. Bit 0 is LSB

3.3VDC

FE_AGC[2:0] for RxBit 0 = 4dB stepBit 1 = 8dB stepBit 2 = 16dB stepControlled via SPI REG C, Bits D8-D10

Rx 5.0VDC

Tx 5.0VDCFE_AGC[2:0] for TxBit 0 = 5dB stepBit 1 = 10dB stepBit 2 = 20dB stepControlled via SPI REG C, Bits D8-D10

5Db1 Bit

30Db2 Bits

I/O SelectNo control needed

(set on Board)

Ext_

LNA_

EN (G

PIO

[7])

LNA_

SW (R

X_AT

TN[3

])

FE_AGC[2:0] (RX_ATTN[2:0])

External PowerAmplifier (PA)

PA Enable(TX_EN)

TxDetect

Rx 3.5 – 3.6 GHz

DiversityControl Logic

T/R_SW (TR_SW)

ANT_SW – not used

ANT_SW1 = ANT10 = ANT2

T/R_SW1 = Tx0 = Rx

Tx 3.5 – 3.6 GHz

2

TX/RX Switch

2 – diversity not used

SE7051LIF Modulator/De-Modulator



Figure 1:15 Down-Conversion in Zero-IF Receiver

The disadvantages of a zero-IF receiver:

1. The zero-IF approach is sensitive to amplitude and phase matching of the I-Q paths, which affects the mirror signal suppression (approx. 40 dB required).

2. The DC-offset after the mixer may be larger than the signal and may saturate the baseband filters. Thus ZIFs require some form of dc offset removal or cancellation scheme. Note: This problem does not exist in the low-IF receiver since the signal is not situated at the DC. This is shown in Figure 1:16, next subsection.

1.5.4 Low-IF ReceiverIn a low-IF topology the received signal is converted to a low-IF. It is based on a compromise between the high-IF and the zero-IF design approaches.

The main disadvantage is that the mirror signal suppression required is larger. In a ZIF the mirror signal is the wanted signal itself, while in the low-IF case it may be larger than the wanted signal.

Low-IF receiver frequency conversion is shown in Figure 1:16.

wanted signal wanted signal

Freq

Freq

BBFsin(wt)

cos(wt)

LNA DSPAD

I

Q

LO (ejwt)

MB87M3400


Figure 1:16 Down-Conversion in Low-IF Receiver

1.5.5 RF Interface On-chip ADC/DAC1.5.5.1 Receiver Interface to the Internal ADCThe receiver will interface to dual (I and Q) 10-bit ADC’s running at a maximum sample rate of 46.08 MHz (assuming a 20 MHz channel bandwidth)

The FECLK or Sample_CLK_2X (= 2x sampling frequency (FS)) signal is from the output of a DDS or a fixed clock source. This clock is used for sampling data provided to the high-speed ADCs and DACs.

The Miscellaneous Control Register (MCR) contains various control bits for the analog front end. Figure 1:17 shows the on-chip MCR control signals for I/Q ADC.

mirror mirror

mirror

wanted

wanted

wanted

Freq

= complex

-IF IF

Polyphase BPF

Freq

LNADSPA

D

LO (ejwt)

ej(wi)tej(wc-wi)t



Figure 1:17 MB87M3400 Receive RF ADC Interface

1.5.5.2 Transmitter Interface from the Internal DACThe transmitter will interface to dual 10-bit DAC’s running at a nominal sample rate of 46.06 MHz (assuming a 20 MHz channel

bandwidth). It is a simple interface and is shown Figure 1:18:

Figure 1:18 MB87M3400 Transmit RF DAC Interface

1.5.5.3 ADC Common Mode Voltage (DC Offset Voltage)The typical value of common mode voltage for built-in 10-bit ADC blocks is 0.55 V. When receiver signals from the Radio Board need to be interfaced to the MB87M3400 l and Q ADC, there needs to be a level shift of the common mode voltage from the Radio Board.

An example of this is shown in Figure 1:19. This example is from the Sapphire Radio Board used with the Fujitsu MB87M3400 SoC Reference Board.

Receiver Analog Front End

AGC

AutomaticGain Control

DecimationFilter

DO

OMODEOUTDIS

PDADCPDBGRPDBR

DO

PDADCPDBGRPDBR

OMODEOUTDIS

ADC_2S_CMP_SEL

ADC_OUT_EN_n

ADC_PD

BANDGAP_PD

VREF_PDMCR

RXFIFO

RX_I[9:0]

RX_Q[9:0]

FECLK

MB87M3400 Receive ADC Interface

From

Rad

io B

oard

From

Rad

io B

oard

1. The AFE Rx interface - provides the interface between the 10-bit I&Q data from the ADC’s and theAGC, Rx FIFO and Decimation filters.

2. ARX_I_OUT+, ARX_I_OUT-, ARX_Q_OUT+, ARX_Q_OUT- from Radio Board.3. ADC Control Signals - adc_2s_cmp_sel, adc_out_en_n, adc_pd, bandgap_pd and vref_pd are set

through the MCR (MISC Control Register). 4. RX FIFO/ADC IF - The 10-bit in-phase and quadrature data, RX_I[9:0] and RX_Q[9:0], is fed directly to the

Rx FIFO where it is resynchronized to the PHY_CLK domain. 5. After resynchronization the I&Q data is sent directly to the AGC and then the Decimation Filters.

IADC

QADC

DRX_I_IN[9:0]

DRX_Q_IN[9:0]

ARX_I_OUT+

ARX_I_OUT-

ARX_Q_OUT+

ARX_Q_OUT-

(Digital Input from External ADC)

(Digital Input from External ADC)

FECLK(Sampling Clock fromOff-Chip DDS)

DTX_I_OUT[9:0]

DTX_Q_OUT[9:0]

ATX_I_OUT+

ATX_I_OUT-

ATX_Q_OUT+

ATX_Q_OUT-

TXFIFO

QDAC

MCR

IDAC

Transmitter Analog Front End

ADC_PD

DITX_Q[9:0]

DITX_Q[9:0]

To R

adio

Boa

rd

(Digital Output for External DAC)

( Digital Output for External DAC)

InterpolationFilter

TX Buffer

MB87M3400 Transmit DAC Interface

PD

PD

FECLK

FECLK(Sampling Clock from Off-Chip DDS)

MB87M3400


Figure 1:19 DC Offset Shift from Radio to SoC Board

Note that the common mode voltage (CMV) for the Sapphire Radio Board varies from 1.0 V to 1.6 V, whereas the CMV for the on-chip ADC is fixed at 0.55 V. The CMV needs to be shifted to 0.55 V so that the I/Q signals can be used by the on-chip ADC.

There are two types of electronic circuits that can achieve this shift.

1. Transistor based

2. Op-amp based

+1.15

+1.65V

V(p-p) = 0.5V (Single Output Range with CMV at 1.4V)CMV = +1.0 <-> 1.6V

Sapphire Radio Board Signal Output Characteristics

+0.25V

+0.85V

+0.55V

V(p-p) = 0.6V (Single Input Range with CMV at 0.55)CMV = 0.55VUpper Reference Voltage = +0.85VLower Reference Voltage = +0.25V

MB87M3400 Internal ADCSignal Input Characteristics

0.3V

0.3V

I+/Q+

Notes: 1. The above gives V(p-p) = 1.0V (Differential Output Range)2. CMV actually varies from 1.0V to 1.6V for Sapphire SE7051L3. CMV, V(p-p) Voltages will also depend on Vendor providing the Radio Board4. DC Offset (CMV) Voltage) Voltage need to be shifted to match 0.55V

+0.25V

+0.85V

+0.55V

V(p-p) = 0.6V (Single Input Range with CMV at 0.55)CMV = 0.55VUpper Reference Voltage = +0.85VLower Reference Voltage = +0.25V

0.3V

0.3V

I-/Q-

Notes: 1. Definition: CMV DC Offset Voltage common to both +, - signals2. CVM = 0.55 the DC offset that exist on both I+, I- signals3. The above gives V(p-p) = 1.2V (Differential Input Range)4. MB87M3400 Specification states: CMV = 0.55V5. MB87M3400 Specification states: Differential Voltage = 1.2V(p-p)

I+/Q+

+1.4V0.25V

0.25V

CMV Shift Circuit(+1.6V +0.55V)

+1.15

+1.65V

V(p-p) = 0.5V (Single Output Range with CMV at 1.4V)CMV = +1.0 <-> 1.6V

I-/Q-

+1.6V0.25V

0.25V

(ARX_I/Q_OUT+) from Radio Board

(ARX_I/Q_OUT-) from Radio Board

SE7051L MB87M3400

CMV = +1.4V

CMV = +0.55V

CMV = +1.4V

CMV = +0.55V

(ARX_I/Q_OUT+ to MB87M3400)

(ARX_I/Q_OUT- to MB87M3400)

Common-Mode Voltage Shifting Example:Shift from 1.4V to 0.55V



Example 1

The desire is to level shift the ~1-1.6 V SE7051L common mode level to be compatible with the ADC’s 0.55 level. To do this an NPN emitter-follower circuit will be required. A fixed common mode voltage (say 1.4 V) can be shifted down to 0.55 volts by setting the output current via external resistors to provide the desired output voltage. The shunt resistance, between the bases of each pair, is needed to provide a real load impedance for the SE7051L. If the

impedance is made sufficiently high (~2K) this circuit will be transparent to the radio’s operation.

The Figure 1:20 shows an NPN emitter-follower circuit that implements the 1.4 V to 0.55 V level shift of the common mode voltage:

Figure 1:20 Transistor-based DC Offset Shift from Radio to SoC Board

Figure 1:21 shows an example of how it is implemented in the Radio Board.

Note: CVM = 0.55V the DC offset that exist on both I+, I- signals

+0.25V

+0.85V

+0.55V0.25V

0.25V

+0.25V

+0.85V1-1.6V

1-1.6V

2K1K

I+

I–

0.55mA

0.55mA

0.55V

0.55V1K

Vcc

+0.55V0.25V

0.25V

SE7051L

Radio Board Component Proposed Solution #1 Note: 1) Only I+/I- is shown. 2) Solution for the Q+/Q- is similar.

MB87M3400


Figure 1:21 Transistor-based DC Offset Example from Reference Radio Board

The low-pass filter is needed for the baseband spectral mask.

Advantage:

Less expensive component costs.

Disadvantage:

May result in I/Q imbalance if two separate packages (each containing two transistors) are used. If a single package is used, the I/Q imbalance may be less of a problem.

MB87M3400

ARX_I_IN+

ARX_I_IN-

3-Pole ButterworthLow-PASS Filter

15 µH

15 µH 15 µH

15 µH

75pF

F3dB = 2.5 MHz1 KOHM Differential In, 200 Out

SE7051L(Sapphire Radio)

RX_I+

RX_I-

RX I Channel

VDD 3.3

0.01µF 100pF

1K

1K

1K

100pF0.01µF

CMV = 0.55V

CMV = 0.55V

22 µH

22 µH

49.9

49.9

750

750

For 7 MHz RF Channel BW, use:F3dB = 5.1 MHzImplement the same changes to both filters:All = 10 µH, 0805 LSUse 56pF CAP

VDD 3.3

ARX_Q_IN+

ARX_Q_IN-


15 µH

15 µH 15 µH

15 µH

75pF


RX_Q+

RX_Q-

RX Q Channel

VDD 3.3

0.01µF 100pF

1K

1K

1K

100pF0.01µF

CMV = 0.55V

CMV = 0.55V

22 µH

22 µH

49.9

49.9

750

750

VDD 3.3



Example 2

Note that the DC Offset Voltage and the Differential Peak-to-Peak Voltages are different for different Radio Boards. An OP AMP Buffer Curcuit needs to be implemented in the SoC Reference Board.

This is shown in Figure 1:22.

Figure 1:22 Buffer OP AMP for Peak-to-Peak and Offset Voltage Shift

Advantage:

It is a better solution – allows better control of the DC offset.

Disadvantage:

1. Need –5V power supply

2. Need more expensive parts

MB87M3400


15 µH

15 µH 15 µH

15 µH

75pF


SE7051LSapphire Radio)

RX_I+

RX_I-

RX I Channel

22 µH

22 µH

49.9

49.9

750

750

For 7 MHz RF Channel BW, use:F3dB = 5.1 MHzImplement the same changes to both filters:All = 10 µH, 0805 LSUse 56pF CAP

10.0K

10.0K

+5VDD

-5VDD

V+

V-

-

+

+

-

ARX_I_IN-

ARX_I_IN+

10.0K

10.0K

NPNNPN

+0.55V

2 (VCM)4

57 8

1

NC 3

6


15 µH

15 µH 15 µH

15 µH

75pF


RX_I+

RX_I-

RX I Channel

22 µH

22 µH

49.9

49.9

750

750

10.0K

10.0K

+5VDD

-5VDD

V+

V-

-

+

+

-

ARX_I_IN-

ARX_I_IN+

10.0K

10.0K

NPNNPN

+0.55V

2 (VCM)4

57 8

1

NC 3

6

ARX_I/Q_IN_+/- trace lengthsNeed to be equalized

MB87M3400


1.5.5.4 DAC Common Mode Voltage (DC Offset Voltage)For DAC the common mode voltage is 0 V (see Table 8-2 and 8-3 of MB87M34 Datasheet, Revision 1).

ATX_I_OUT+ is the analog current output. (A resistor of 75Ω typically is connected between this pin and Analog GND.)

ATX_I_OUT– is the complementary analog current output. (A resistor of 75Ω typically is connected between this pin and Analog.)

An example of common mode voltage shift is shown in the Figure 1:23:

Figure 1:23 DC Offset Shift from SoC Board to Radio Board

1.5.5.5 MB87M3400 Digital I and Q Interface for External ADC/DACThe MB87M3400 relevant digital signals for the external ADC/DAC are shown in Figure 1:24 (reproduced from Reference Board schematics):

SE7051L(Sapphire Radio)MB87M3400

TX_I+

TX_I-

TX_Q+

TX_Q-

150, 1% 150, 1%

64.9, 1%

300, 1%

150, 1% 150, 1%

64.9, 1%

300, 1%

ATX_I_OUT+

ATX_I_OUT-

ATX_Q_OUT+

ATX_Q_OUT-

VCM = 1.5V

VCM = 1.5V

VCM = 1.5V

VCM = 1.5V

Note:1) TX_I/Q+, TX_I/Q- are shifted to CMV of 1.5V before inputting to Radio Board2) This is achieved by the 3 Voltage Division Resistors



10 µH

10 µH 10 µH

10 µH

10 µH

10 µH10 µH

10 µH

390pF 56pF

390pF 56pF

F3dB = 2.5 MHz300 OHM Differential In, 300 Out

F3dB = 2.5 MHz300 OHM Differential In, 300 Out

For 7 MHz RF Channel BW, use:F3dB = 5 MHzImplement the same changes to both filters:All = 6.8 µH, 0805 LSRemove 56pF CAP

FS V(out) = 781.5 mV (1.56 V(p-p)FS I(out) = 10.52mAVirtual CMV = 0.3945V

FS V(out) = 781.5 mV (1.56 V(p-p)FS I(out) = 10.52mAVirtual CMV = 0.3945V

DAC Load Impedance = 150 OHMS Differential

DAC Load Impedance = 150 OHMS Differential

TX I Channel

TX Q Channel

A

B

A

B

GND

GND



Notes:

1. Digital I/Q interface to external ADC/DAC is shown in the above figure

2. The following connections of these signals are described in the next subsections.

a. Digital I/Q interface to external ADC

b. Digital I/Q interface to external DAC

Figure 1:24 MB87M3400 External ADC/DAC Signals from Reference Board Schematics

The connections of the next two sub-sections show how the on-chip ADC and and on-chip DAC can be bypassed and replaced by external ADC and external DAC, respectively. The diagrams are reproduced from Reference Board schematics.

1.5.5.5.1 External ADC ApplicationThe internal ADC can be bypassed and MB87M3400 can be interfaced to external ADC using the input pins DRX_I_IN[9:0] and DRX_Q_IN[9:0]. Figure 1:25 shows the received analog I/Q signals from the Radio Board going into an external ADC. The digital outputs of the external ADC will then go the Digital I/Q Interface of the MB87M3400 SoC.

AGC_CTRL0

1.2Vpp. 0.55 Vcm for ARX_IN+/– I&Q

R196 33.2R C11AGC_CTRL1

AGC_CTRL[0:9]

R197 33.2R A10AGC_CTRL2 R199 33.2R B10AGC_CTRL3 R219 33.2R C10AGC_CTRL4 R220 33.2R D10AGC_CTRL5 R221 33.2R A9AGC_CTRL6 R251 33.2R B8AGC_CTRL7 R252 33.2R C8AGC_CTRL8 R268 33.2R A7AGC_CTRL9

AGC_CTRL0

U3–B

802_16_SOC

AGC_CTRL1AGC_CTRL2AGC_CTRL3AGC_CTRL4AGC_CTRL5AGC_CTRL6AGC_CTRL7AGC_CTRL8AGC_CTRL9

DTX_I_OUT0DTX_I_OUT1DTX_I_OUT2DTX_I_OUT3DTX_I_OUT4DTX_I_OUT5DTX_I_OUT6DTX_I_OUT7DTX_I_OUT8DTX_I_OUT9R269 33.2R B7

B32B31A31C30B30A30C29B29A29C28

R29R30R53R69R70R72R73R74R75R76

33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R

TX_I_DATA0

TX_I_DATA[0:9](10,13)

TX_Q_DATA[0:9]

Dig

ital I

/Q In

terf

ace

to E

xter

nal A

DC

/DA

C

RX_I_DATA[0:9]

RX_Q_DATA[0:9]

TX_I_DATA1TX_I_DATA2TX_I_DATA3TX_I_DATA4TX_I_DATA5TX_I_DATA6TX_I_DATA7TX_I_DATA8TX_I_DATA9

DTX_Q_OUT0DTX_Q_OUT1DTX_Q_OUT2DTX_Q_OUT3DTX_Q_OUT4DTX_Q_OUT5DTX_Q_OUT6DTX_Q_OUT7DTX_Q_OUT8DTX_Q_OUT9

G31F33F32F31E31D33D31C33C32C31

R77R78R79R81R82

R100R130R133R134R152

33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R

TX_Q_DATA0TX_Q_DATA1TX_Q_DATA2TX_Q_DATA3TX_Q_DATA4TX_Q_DATA5TX_Q_DATA6TX_Q_DATA7TX_Q_DATA8TX_Q_DATA9

DRX_I_IN0DRX_I_IN1DRX_I_IN2DRX_I_IN3DRX_I_IN4DRX_I_IN5DRX_I_IN6DRX_I_IN7DRX_I_IN8DRX_I_IN9

B24C24D24B23C23A22B22C22D22A21

RX_I_DATA0RX_I_DATA1RX_I_DATA2RX_I_DATA3RX_I_DATA4RX_I_DATA5RX_I_DATA6RX_I_DATA7RX_I_DATA8RX_I_DATA9

DRX_Q_IN0DRX_Q_IN1DRX_Q_IN2DRX_Q_IN3DRX_Q_IN4DRX_Q_IN5DRX_Q_IN6DRX_Q_IN7DRX_Q_IN8DRX_Q_IN9

B28A28C27B27A27B26C26B25C25A24

RX_Q_DATA0RX_Q_DATA1RX_Q_DATA2RX_Q_DATA3RX_Q_DATA4RX_Q_DATA5RX_Q_DATA6RX_Q_DATA7RX_Q_DATA8RX_Q_DATA9

AGC_STRB R270 33.2R B11

LD R271 OR C13

LD R272 OR B12

TX_EN_U R273 33.2R A11

RX_EN_U R280 33.2R D12

TR_SW_U R282 33.2R C12

RF_ENABLETX_PWR_DETECTRX_PWR_DETECT

R283

R284

R123 OR

R285

33.2R

33.2R

R2610.0K

3V3

33.2R

C4AE32AE31

ATX_I_OUTA+ATX_I_OUTA–

Y32Y33

ATX_Q_OUTA+ AB32

ATX_Q_OUTA– AB33

ARX_I_INA+ L33

ARX_Q_INA– L32

ARX_Q_INA+ T32

ARX_Q_INA– T33

ADC_DAC_CLK G32

BS_SYNC_OUT B5

BS_SYNC_IN B4

FT_INT A4

SED_CLK A5

SED_DATA B6

SED_FS

ARM_EXT_IRQ0

AGC_STROBENLDLDTX_ENRX_ENTR_SWRF_ENABLETX_PWR_DETECTRX_PWR_DETECT

ATX_I_OUT+ATX_I_OUT–

ATX_Q_OUT+ATX_Q_OUT–

ARX_I_IN+ARX_Q_IN–

ARX_Q_IN+ARX_Q_IN–

ADC_DAC_CLKBS_SYNC_OUTBS_SYNC_INFT_INT


C6

MB87M3400


Figure 1:25 Digital RX I/Q Interface using External ADC

The above application of external ADC is reproduced from the Reference Board design.

Sampling Clock for ADC Bypass: ADC_DAC_CLK (sampling clock output) can be used for both ADC_I & ADC_Q, and DAC_I & DAC_Q. The signal from this pin can be used for the external ADC sampling clock when internal Analog ADC is bypassed. In the above figure RXCLK is the same as the ADC_DAC_CLK.

1.5.5.5.2 External DAC ApplicationThe internal DAC can be bypassed and MB87M3400 can be interfaced to external DAC using the output pins DTX_I_OU[9:0] and DTX_Q_OUT[9:0].

The transmitter will interface to dual 10-bit DAC’s running at a nominal sample rate of 46.06 MHz (assuming a 20 MHz channel bandwidth). Figure 1:26 shows the digital TX outputs of the MB87M34 going to an external DAC. The analog I/Q signals of the external DAC are then sent to the Radio Board for modulation and transmission.

2Vpp. 1.1 Vcm input

U23

3V3ADC

3V3ADC

L1ML16A270U

L16

ML16A270U

3V3

3V3

C264

C265

0.1µF

C266

0.1µF

C267

0.1µF

C78

10µF

C79

10µF

C80

10µF

C420

0.1µF 10µF

3V3

D0AD1A

32

1011

567

489

13303148

AINAAINA

AINBAINB

REFINAREFOUTREFINB

DFS/GAINS1S2

VDVDVDVD

D2AD3AD4AD5AD6AD7AD8AD9A

D0BD1BD2BD3BD4BD5BD6BD7BD8BD9B

35363738394041424344

R166

R450ARX_I_INB–

ARX_I_INB+

ARX_Q_INB–

ARX_Q_INB+ R167R168R177R178R179R180R181R182R183

33.2R

100RR451 1.0KR452 100RR453

R292R293R294

R296R298R299

R295

NPPNPPNPP

NPPNPPOR

OR

1.0K

33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R

RX_I_DATA0 RX_I_DATA[0:9][10]

RX_Q_DATA[0:9][10]

RX_I_DATA1RX_I_DATA2RX_I_DATA3RX_I_DATA4RX_I_DATA5RX_I_DATA6RX_I_DATA7RX_I_DATA8RX_I_DATA9

26

ENCA47

ENCB14

GND1

GND12

GND16

GND27

GND29

GND32

GND34

GND45

252423222120191817

R184R185R186R187R188R189R190R191R192R195

33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R33.2R

RX_Q_DATA0RX_Q_DATA1RX_Q_DATA2RX_Q_DATA3RX_Q_DATA4RX_Q_DATA5RX_Q_DATA6RX_Q_DATA7RX_Q_DATA8RX_Q_DATA9

R454 100RR455 1.0KR456 100RR457 1.0K

13303148

VDDVDDVDDVDD

C269

0.1µF

C268

0.1µF

C270

0.1µF

C271

0.1µF

C81

10µF

C82

10µF

C83C84

10µF 10µF

C8547pF

R198100R

TP64

Place C85 and R198 close to U23

RXCLK[10]

AD9218BST–80

External ADC

To MB87M3400 SOCRX Digital Interface

From

Rad

io B

oard



Figure 1:26 Digital TX I/Q Interface Using External DAC

The above application of external ADC is reproduced from the Reference Board design.

Sampling Clock for DAC Bypass: ADC_DAC_CLK (sampling clock output) can be used for both ADC_I & ADC_Q, and DAC_I & DAC_Q. The signal from this pin can be used for the external DAC sampling clock when internal Analog ADC is bypassed. In the above figure TXCLK is the same as the ADC_DAC_CLK.

1.5.5.6 ADC/DAC Power SuppliesThe power supplies for the ADC/DAC are provided next (this data is also provided in MB87M3400 Datasheet, Revision 1):

High-Speed ADC I:

AVDL2A INP 1.8V (Analog Power)AVS2A INP 0.0V (Analog Ground)AVDL3A INP 1.8V (Analog Power)AVS3A INP 0.0V (Analog Ground)ARX_I_INn INPARX_I_INp INPAVDL1A INP 1.8V (Analog Power)AVS1A INP 0.0V (Analog Ground)DVDLA INP 1.8V (Digital Power)DVSA INP 0.0V (Digital GND)DVSGA INP 0.0V (Guard Ring GND)

External DACFrom MB87M3400 SOCTX Digital Interface

From MB87M3400 SOCTX Digital Interface

To R

adio

Boa

rdTo

Rad

io B

oard

L9ML16A270U

3V3

+3.3VA

C7710µF

U25AD9763AST

C7022pF

C7122pF

C7222pF

C2630.1µF

GAIN CONTROL SET FOR SINGLE REFMODE SET FOR NON-INTERLEAVE

0.4781VPP

0.4781VPP

0.4781VPP

Ioutfs = 10mA

0.4781VPPATX_I_OUTB+[10]

ATX_I_OUTB–[10]

ATX_Q_OUTB+[10]

ATX_Q_OUTB–[10]

Add net name here and use plane

TP63

TP50

+3.3VA

TP1321.2VDC

C260

0.1µF

C261

R21175.0R

R21075.0R

R21775.0R

C7322pFR216

75.0R

R2001.1K

Iref = 1.2V/3.84K = 0.3125mA

R201

C262 0.1µF

2.74K

0.1µF

C259

TX_I_DATA0

TX_I_DATA[0:9][10]

TX_Q_DATA[0:9][10]

TXCLK[10]

10IOUTA1

16 22 47

DV

DD

1

DV

DD

2

AV

DD

15 21 38

DC

OM

1

DC

OM

2

AC

OM

TX_I_DATA1 9TX_I_DATA2 8TX_I_DATA3 7

R202R125

C7447pF

U2

DR17

R203 18R204 20R205

33.2R33.2R33.2R33.2R 19

TX_I_DATA4 6TX_I_DATA5 5TX_I_DATA6 4TX_I_DATA7 3TX_I_DATA8 2TX_I_DATA9 1

TX_Q_DATA0 32TX_Q_DATA1 31TX_Q_DATA2 30TX_Q_DATA3 29TX_Q_DATA4 28TX_Q_DATA5 27TX_Q_DATA6 26TX_Q_DATA7 25TX_Q_DATA8 24TX_Q_DATA9 23

DB0–P146

FSADJ144

FSADJ241

REFIO43

39

40

42

4837

IOUTB1

IOUTA2

IOUTB2

GAINCTRL

MODESLEEP

45

R126

R258100R

MC74VHC1G14DFT2

3V3

52

3

4

NNP

DB1–P1DB2–P1DB3–P1DB4–P1DB5–P1DB6–P1DB7–P1DB8–P1DB9–P1

DB0–P2DB1–P2DB2–P2DB3–P2

WRT1/IQWRTCLK1/IQCLXWRT2/IQSELCLK2/IQRESET

DB4–P2DB5–P2DB6–P2DB7–P2DB8–P2DB9–P2

0.1µF

C75

10µF

C76

10µF

MB87M3400


High-Speed DAC I:

DAC_I_COMP OUTP --- ---DAC_I_VREF INP --- ---AVS1 INP 0.0V (Analog Ground)DAC_I_VRO OUTP --- ---AVD1 INP 3.3V (Analog Power)ATX_I_OUTp OUTP --- ---ATX_I_OUTn OUTP --- ---AVD2 INP 3.3V (Analog Power)AVS2 INP 0.0V (Analog Ground)AVS3 INP 0.0V (Analog Ground)

Data is similar for high-speed ADC Q and high-speed DAC Q.

1.5.5.7 Ripple Noise for ADC/DAC Power SuppliesThere is no data available for ripple noise for both the ADC, and the DAC power supply. However, the following value is the recommended value from Fujitsu:

Ideal is less than 10 mV. But it is very difficult to keep this value. Therefore, the actual value is less than 50 mV.

1.5.5.8 ADC Differential Input ImpedanceDifferential (input) impedance of I± and Q± for the ADC is provided in Chapter 8, Section 8.4.4 of the MB87M3400 Datasheet, Revision 1 (Typical Application Circuit) as shown below:

Figure 1:27 MB87M3400 High-Speed ADC Typical Application Circuit

It describes input resistance to be 51 Ω, and input capitance to be 10 pF.

INP

DO9(MSB)

INM SC00XU1APAB13

INP

INM DO0(LSB)

VRIRVRHVRL SG

0.55V

0.55V

51Ω¶

10pF

10pF

(To Other ADC)

OMODE

DVDL

AVDL3

DVS

AVS2

VDD

VSS

1.8V

1.8V

DV

DL2

DV

DL1

Logi

c

DV

S

AV

S3

1000

pF

1000

pF

1000

pF

AV

S2

AV

S1

DV

SC

K

DV

SG

VR

L

SG

VR

H

VR

R

AV

DL3

AV

DL2

AV

DL1

DV

DC

LK

CLK

IN

CLK

OU

T

PD

1.8V

AVDL2

AVS1

AVS3

AVDL1

1.8V

2.2µ

F

+ + + +

0.8V

51Ω¶

0.1µ

F

2.2µ

F

0.1µ

F

2.2µ

F

0.1µ

F

2.2µ

F

0.1µ

F

0.1µ

F

0.1µ

F

0.1µ

F

CLK

DVDLCK1.8V

2.2µ

F

+ 0.1µ

F

DVSCK

DVSG

OUTDIS

0.85V0.55V0.25V



1.5.5.9 DAC Differential Output ImpedanceDifferential (output) impedance of I± and Q± for the DAC depends on other input device specifications. Therefore, Fujitsu cannot recommend the value for this.

Note:

Output impedance, IAOUT, for DAC is given by the following formula:

Zo = (1.0 – 0)/(IAOUT(1.0 V) – IAOUT(0 V))

For example IAOUT(1.0 V) – IAOUT(0 V) = 0.002 mA

Z0 = 1/0.002 mA = 500 KΩ

This value of 500 KΩ shown in Chapter 11, Table 11-9 of the MB87M3400 Datasheet, Revision 1.

1.5.6 RF System Test Plan1.5.6.1 ScopeThis section outlines RF system tests that are performed.

1.5.6.2 Referenced DocumentsDocuments referred to in this section are shown in Table 1-3: Referenced Documents.

Table 1-3: Referenced Documents

1.5.6.3 Equipment1. Spectrum analyzer

2. Vector signal analyzer

3. Miscellaneous RF cables

4. Miscellaneous RF splitters and combiners

5. Variable RF attenuators

6. Averaging power meter

7. Packet generator

8. Miscellaneous test equipment

1.5.6.4 Transmit Parameter Tests1.5.6.4.1 Spectral Mask1.5.6.4.1.1 Test SetupThe test shall be setup as shown in Figure 1:28.

Figure 1:28 Spectral Mask Test Setup

1.5.6.4.1.2 Test OverviewThe UUT is provided data from a packet generator that is random in size and data pattern. The UUT will be set to maximum output power and fixed only to transmit. Please note that the transmit duty cycle will be dependant on the modulation type and will be documented with test results.

This test requires that the spectrum analyzer be setup with a RBW of 100kHz and a VBW of 30kHz. Table 1-4: Spectral Mask Test Vectors shows all vectors required for test completion.

Table 1-4: Spectral Mask Test Vectors

Document Name Revision Date

Conformance Testing to IEEE Std 802.16-2004 – Part 3: Radio Conformance Tests (RCT) for Wireless MAN-OFDM and Wire-lessHUMAN(-OFDM) Air Interface

CS 103 001 v0.3.2 10/3/2005

IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed Broadband Wireless Access Systems

IEEE Std 802.16-2004 10/3/2005

European Standard - ETSI EN 301 021 V1.6.1 (2003-07) 10/18/2005Test Frequency Test Modulation

High Channel

BPSK – 1/2

QPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

Mid Channel

BPSK – 1/2

QPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

Low Channel

BPSK – 1/2

QPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

UUTRF

Splitter

PowerMeter

SpectrumAnalyzer

PacketGenerator

MB87M3400


1.5.6.4.1.3 Required ResultSpectral Mask will be tested as defined in the ETSI EN 301 021 v1.6.1. Our system will be tested to System A specification as outlined in Table 3, section 5.3.3 in the standard.

1.5.6.4.2 Spectral Flatness1.5.6.4.2.1 Test SetupThe test shall be setup as shown in Figure 1:29.

Figure 1:29 Spectral Flatness Test Setup

1.5.6.4.2.2 Test OverviewThe UUT is provided data from a packet generator that is random in size and data pattern. The UUT will be set to maximum output power and fixed only to transmit. Measurement results will be averaged over 100 symbols and will be completed at high, mid and low RF channel.

1.5.6.4.2.3 Required ResultThe following list as found in section 8.2.17 of the Radio Conformance Test document outlines the required results for test completion:

a. The absolute difference between adjacent subcarriers shall not exceed 0.1dB.

b. The spectral energy for each subcarrier from –50 to +50 except for 0, shall be less than ± 2dB from the average energy measured over all 200 tones.

c. The spectral energy for each subcarrier from –100 to –50 and +50 to +100 shall be less then +2dB/-4dB from the average energy measured over all 200 tones.

d. The power transmitted at spectral line 0 shall not exceed –15dB relative to total transmitted power.

1.5.6.4.3 Relative Constellation Error (EVM)1.5.6.4.3.1 Test SetupThe test shall be setup as shown in Figure 1:29.

1.5.6.4.3.2 Test OverviewThe UUT is provided data from a packet generator that is random in size and data pattern. The UUT will be set to maximum output power and fixed only to transmit. The results will not be averaged; none of the VSA demodulations can fall below the values listed in section 1.5.6.4.3.3. This test will be repeated for high and low RF channels as well as largest and smallest cyclic prefix.

The maximum output power has not been tested to date and will be documented with this tests results. Maximum output power, as stated above, means the removal of all transmitter attenuation.

1.5.6.4.3.3 Required ResultsTable 1-5 displays the required results for test completion. All recorded tested values must be greater then values listed.

Table 1-5: RCE Test Parameters

1.5.6.5 Receive Parameter Tests1.5.6.5.1 Receive Sensitivity1.5.6.5.1.1 Test SetupThe test shall be setup as shown in Figure 1:30.

Figure 1:30 Receive Sensitivity Test Setup

UUTRF

Splitter

PowerMeter

VSA

PacketGenerator

Modulation Maximum RCE (dB)

BPSK – 1/2 -13.0

QPSK – 3/4 -18.5

QAM16 – 3/4 -25.0

QAM64 – 3/4 -31.0

TxSource

RFSplitter

PowerMeter

PacketGenerator

UUT VA



1.5.6.5.1.2 Test OverviewThe UUT is provided data from a packet generator that is random in size and data pattern. The variable attenuator will be used to set the input power to the UUT. This input power will be decremented until the values in Table 5 are reached. This test will be repeated at high, mid and low RF channels.

1.5.6.5.1.3 Required ResultThe UUT must report less then 1e-6 BER while above sensitivity. Table 1-6 defines sensitivity for all modulation types and desired channel bandwidths.

Table 1-6: Receive Sensitivity Test Parameters

1.5.6.5.2 RSSI Measurement1.5.6.5.2.1 Test SetupThe test shall be setup as shown in Figure 1:31.

Figure 1:31 RSSI Test Setup

1.5.6.5.2.2 Test OverviewRSSI will be tested starting at maximum receive down to 10 dBm below sensitivity in 2 dB decrements. At every 10 dB interval 10 RSSI readings will be taken over a 5-second interval. For testing ensure either that UUT is fixed in receive or has an output power 40 dBm below that of the Tx Source.

The test will be performed at middle channel using all modulation types.

1.5.6.5.2.3 Required ResultsThe ten RSSI measurements must be within ±4 dB of the actual receive strength and the RMS error shall be less then ±2 dB.

1.5.6.5.3 CINR Measurement 1.5.6.5.3.1 Test SetupThe test shall be setup as shown in Figure 1:32.

Figure 1:32 CINR Test Setup

Channel Bandwidth

BPSK – 1/2 QPSK – 1/2 QPSK – 3/4 QAM16 – 1/2 QAM16 – 3/4 QAM64 – 2/3 QAM64 – 3/4

3.5 MHz -90.6 dB -87.6 dB -85.8 dB -80.6 dB -78.8 dB -74.3 dB -72.6 dB

7.0 MHz -87.6 dB -84.6 dB -82.8 dB -77.6 dB -75.8 dB -71.3 dB -69.6 dB

TxSource

RFSplitter

PowerMeter

PacketGenerator

UUT VA

Tx Source

InterferenceSource

VA

VA

RFCombiner

VSA

VA UUT

MB87M3400


1.5.6.5.3.2 Test OverviewThe variable attenuators between Tx Source, Interference Source and RF Combiner are used to setup the ratio between the useful and interfering signal.

The Interference source is a conforming OFDM signal and is on the same channel with the same bandwidth as the Tx Source signal. It will be set to continuously transmit in a non-synchronized manner.

The CINR measurement will be taken at the VSA and compared to the CINR measurement at the UUT. Ten CINR readings will be taken over 5 seconds and all must be within ± 2 dB of that specified in Table 7.

1.5.6.5.3.3 Required ResultTable 1-7 depicts the results required for test completion.

Table 1-7: CINR Test Parameters

1.5.6.5.4 Adjacent and Alternate Channel Rejection1.5.6.5.4.1 Test SetupThe test shall be setup as shown in Figure 1:33.

Figure 1:33 MB87M3400 High-Speed ADC Typical Application Circuit

1.5.6.5.4.2 Test OverviewThe two variable attenuators are used to adjust the signal strength between the Tx Source and Interference Source. Both sources are conforming OFDM signals that are spaced as defined in Table 1-8.

The test will consist of both Tx and Interference sources transmitting to the UUT. The Interference Source will be spaced ± 1 channel away for adjacent channel testing and ± 2 for alternate channel testing. All required signal levels are defined in the following section.

1.5.6.5.4.3 Required ResultsFor all test vectors listed in Table 1-8 a BER of less then 1e-6 must be maintained.

Table 1-8: Adjacent Channel Test Parameters

Receive Input Signal (Wanted)

Modulation (Wanted)

Receiver Input (C/I)

Interference + 20dB BPSK – 1/2 6.4 dB

Interference + 20dB QAM16 – 3/4 21.2 dB

Interference + 20dB QAM64 – 3/4 27.4 dB

Tx Source

InterferenceSource VA

VA

RFCombiner

VA UUT

Modulation Signal Level Interference Level Frequency Offset

QAM16 – 3/4 3dB > sensitivity 14 dB > sensitivity +1 Channel

QAM16 – 3/4 3dB > sensitivity 14 dB > sensitivity -1 Channel

QAM16 – 3/4 -41 dBm -30 dBm +1 Channel

QAM16 – 3/4 -41 dBm -30 dBm -1 Channel















1.5.6.5.5 Maximum Recievable Signal1.5.6.5.5.1 Test SetupThe test shall be setup as shown in Figure 1:34

Figure 1:34 Maximum Receivable Signal Test Setup

1.5.6.5.5.2 Test OverviewThis test shall verify the maximum receivable signal. The input signal at the UUT will be increased until the test requirement is met.

1.5.6.5.5.3 Required ResultThis test requires that at maximum signal strength of –30 dBm the BER be less then 1e-6 for all modulation types.

1.5.6.5.6 Maximum Tolerable Signal1.5.6.5.6.1 Test SetupThe test shall be setup as shown in Figure 1:34.

1.5.6.5.6.2 Test OverviewThe UUT input signal level will be set at 0dBm for one minute using QPSK – 3/4. Remaining at QPSK – 3/4 decrease power to –75.8 dBm. Check BER and PER for any errors.

1.5.6.5.6.3 Required ResultAfter one minute of maximum tolerable signal ensure that when set down to –75.8 dBm at QPSK – 3/4 the receiver performs at less then 1e-6 with no packet loss.

1.5.6.6 RF System Test Signoff Sheet

TxSource

RFSplitter

PowerMeter

PacketGenerator

UUT VA

Table 1-9: Spectral Mask Test Vectors

Test Section Test Name Channel Modulation Pass/Fail Comments

1 1.5.6.4.1 Spectral Mask

High

BPSK – 1/2

QPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

Mid

BPSK – 1/2

QPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

Low

BPSK – 1/2

QPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

2 1.5.6.4.2 Spectral Flatness

High

BPSK – 1/2

QPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

Mid

BPSK – 1/2

QPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

MB87M3400


2 1.5.6.4.2 Spectral Flatness Low

BPSK – 1/2

QPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

3 1.5.6.4.3 Relative Constellation Error

High

BPSK – 1/2

Smallest CPQPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

High

BPSK – 1/2

Largest CPQPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

Low

BPSK – 1/2

Smallest CPQPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

Low

BPSK – 1/2

Largest CPQPSK – 3/4

QAM16 – 3/4

QAM64 – 3/4

4 1.5.6.5.1 Receive Sensitivity

High

BPSK – 1/2

QPSK – 1/2

QPSK – 3/4

QAM16 – 1/2

QAM16 – 3/4

QAM64 – 2/3

QAM64 – 3/4

Mid

BPSK – 1/2

QPSK – 1/2

QPSK – 3/4

QAM16 – 1/2

QAM16 – 3/4

QAM64 – 2/3

QAM64 – 3/4

Low

BPSK – 1/2

QPSK – 1/2

QPSK – 3/4

QAM16 – 1/2

QAM16 – 3/4

QAM64 – 2/3

QAM64 – 3/4

Table 1-9: Spectral Mask Test Vectors (Continued)




5 0 RSSI Measurement Mid

BPSK - 1/2

Full dynamic Rx Range QPSK – 3/4

QAM16 – 3/4

QAM64 –3/4

6 1.5.6.5.3 CINR Measurement Mid

BPSK – 1/2

QAM16 – 3/4

QAM64 – 3/4

7 1.5.6.5.4Alternate and Adjacent Channel Rejection

** As listed in Table 1-8. **

High

QAM16 – 3/4 +1 Channel

QAM16 – 3/4 -1 Channel















Mid

















Low






MB87M3400


1.6 AGC Operations 1.6.1 SS ReceiverThe AGC is implemented as a look up table and is designed to lock in on the optimum gain during the receipt of a long preamble sequence

from an OFDM transmission. The AGC block will lock the receiver on the optimal gain by controlling the attenuation filters. This is shown in Figure 1:35.

Figure 1:35 MB87M3400 AGC Loop in SS Receive Operation

The AGC generates an internal 8/6-bit output, currentAtten which selects an attenuation level for the I and Q input signals before the ADC’s. Internal register RCR5 is programmed to control various AGC parameters. See MB87M3400 Datasheet, Revision 1, Chapter 5 for more details.

1.6.2 BS ReceiverThe desired receive power level for a BS receiver is determined by numerous factors. As a part of the initial and periodic ranging, the BS tells each SS to adjust its transmit power levels in 1 dB increments over a minimum range of 30 dB so that each UL burst is received by the BS at a similar power level.

7 1.5.6.5.4Alternate and Adjacent Channel Rejection

** As listed in Table 1-8. **














8 1.5.6.5.5 Maximum Receivable Signal Mid QAM64 – 3/4

9 1.5.6.5.6 Maximum Tolerable Signal Mid QAM64 – 3/4



DO(9:0) IADC

QADC

rx_i(9:0)

rx_q(9:0)

ADC control

MCR

AGC

fe_clk

Rx FIFO

DO(9:0) Attenuator + Filter

Attenuator + Filter

agc(9:0) agc_stb

rx_i

rx_q



As a part of system evaluation and testing, the ideal attenuator setting on the BS should be determined and used to yield the optimal receive levels on BS for distant SSs, as well as closer ones. One method to determine the optimal attenuator level is as follows:

1. First, on the BS, configure the receiver to sync to the long preamble with the AGC enabled.

2. Have the SS transmit a UL burst that begins with a long pre-amble. This may be a distant SS operating at minimum power level. You may want to increase the SS power level to get -60 dB RSSI on the BS to ensure that you have a good strong signal for the test. If the transmitter power drifts more than a couple of dB, then you will notice an increase in the BER and will have to adjust the power level on the SS to compensate.

3. Once the BS has synchronized to the UL burst, take note of the final attenuator value that the AGC has settled to.

4. Manually set the attenuators to this AGC value by disabling the AGC automatic operation.

5. Transmit UL traffic to the BS with the same transmitter power level as the burst in step 2.

1.7 AGC Table Calibration Lab Procedure1.7.1 SummaryThis document outlines the steps required to create a functional AGC translation table. The AGC control within the MB87M3400 PHY is used to maintain an optimal signal level at each stage in RF down-conversion. The end result of a correctly balanced RF system is excellent overall system performance.

To aid in the quick setup of the test system, section 1.7.7 is included as a setup calibration guide. This helps determine the actual power at the radio input and implements an offset to a power meter. When offset the power meter will accurately display the power at the antenna port of the radio.

Before continuing with this calibration procedure ensure the operation of the AGC as defined in the MB87M3400 Datasheet is understood, because this document does not detail the operation of the AGC.

1.7.2 Required Materials1. Power meter

2. Oscilloscope

3. Variable RF attenuator

4. Various fixed RF attenuators

5. RF splitter

6. RF signal source

7. RF terminator

8. Various length RF cables

MB87M3400


1.7.3 AGC Operation1.7.3.1 Example System Block Diagram

Figure 1:36 Example Radio Block Diagram Interface to MB87M3400

1.7.3.2 AGC Operation (Details)As shown Figure 1:36, the AGC data lines from the MB87M3400 PHY are connected to attenuator networks on the radio board. These attenuators are used to maintain an optimal signal power throughout the RF system. The values for these attenuators are derived from RF down-conversion testing and are stored in the AGC translation memory. For further detail than listed below see section 5.8.5.2 of the MB87M3400 Datasheet.

1.7.3.2.1 Relevant AGC Parameters1.7.3.2.1.1 AGC Lock Time (agcLockTime)The AGC lock time is the time in samples after the first successful synchronization to the P64 preamble that the AGC will wait before locking.

1.7.3.2.1.2 AGC Delay (agcDelay)The AGC delay is the amount of front end clock cycles allowed for a full AGC iteration. This delay is used to allow for the P32

measurement cycle as well as any external delays required before update.

1.7.3.2.1.3 AGC Averaging Select (agcAvgSel)The averaging allows the MB87M3400 PHY the ability to average 0, 2, or 4 samples together to get the final AGC value. This has the potential to create another AGC iteration and is used to stabilize the AGC as needed.

1.7.3.2.1.4 AGC Offset (agcOffset)This allows the ability to offset the final AGC lock value by a set value. This is used in the event that the AGC is stable but choosing a value that is consistently incorrect.

1.7.3.2.1.5 AGC Power Compare (APCR)The MB87M3400 PHY has several registers referred to as the APCR registers. These registers, the AGC Power Compare Registers, contain two values per register that correspond to a power. This power is compared with the P32 power measurement and determines

RFIn

Rx RF Section Rx IF Section

Rx RF Attenuators Rx IF Attenuators

Base band Rx Filter

Fujitsu MB87M3400SOC

AirMan PHY

+Q and -QDifferential

+I and -IDifferential

AGC (0:9)This bits are devided

between the radioattenuators



the correct AAR value. The MB87M3400 PHY uses the P32 measured power value to determine which jump is correct. A simple comparison is used and if P32≥APCRX it uses the corresponding AAR value.

1.7.3.2.1.6 AGC Attenuator (AAR)The AAR registers are used to define the jump size taken following a power comparison. For a simple example; if P32 < APC3, the jump

size would be defined in AAC3. There is one more AAR register value then APCR; this value is used in the event that the power measurement is less then any APCR values.

1.7.4 AGC Table Calibration Procedure1.7.4.1 Calibration Test SetupThe setup in Figure 1:37 is used for measurements during calibration.

Figure 1:37 Measurement Setup Diagram

1.7.4.2 Measurement ParametersThere are generally three main areas of concern when working to balance the system:

1. RF input level

2. IF input level

3. ADC input level

In order to properly balance the system the signal power at all three areas must be optimized. RF and IF input levels are specific to the RF system being used. The typical ADC input level is 65mVRMS single-ended measured on the preamble section of the data burst. It is very important to maintain an optimal balance throughout the entire RF down-conversion. It is possible to use different combinations of RF and IF attenuation and reach desired base-band level. In order to properly verify the correct balance the FEC bit error rate must be examined.

1.7.4.3 Measurement Steps1. Set highest desired input power which will correspond to high-

est AGC attenuation

2. Add in IF and RF attenuators to optimize the RF down-conversion path.

3. Measure and verify that at MB87M3400 ADC input the pre-amble voltage is 65mVRMS (± 5mVRMS) single-ended. In order to verify the correct settings ensure that FEC bit error rate is 0. This will ensure proper RF attenuator balance.

4. Repeat steps 1, 2, and 3 to refine the base band level or attenu-ator balance to optimize bit error rate.

5. When desired performance is attained record attenuator bit settings.

6. Increase variable attenuator by 1dB.

7. Repeat steps 1 through 5 for each step through the table.

8. After compiling a full bit map for all AGC values the table can be loaded into the MB87M3400 PHY.

1.7.5 VerificationFollowing the completion of the AGC table, run a full system test. To verify correct operation of the system fix the AGC attenuation value and RF input level. If the AGC has been properly calibrated each input power versus fixed AGC setting will have a minimal pre-FEC bit error rate.

RF Traffic Source(Radio)

Variable Attenuator(1dB Resolution)

RFSplitter

PowerMeter

FixedAttenuator Unit Under Test

MB87M3400


1.7.6 ConclusionThe table when implemented will allow the MB87M3400 PHY to associate an input power level with a desired attenuation. When operating properly the AGC should predictably arrive at the desired table value in reference to the RF input level. When correctly balanced, the overall system pre-FEC bit error rate will be extremely low.

1.7.7 System Setup Calibration Procedure1.7.7.1 Calibration OverviewThe purpose of the calibration is to determine the power at the antenna port of the unit under test (UUT). This value is also used to determine the loss from the power meter to the UUT. This loss is used to offset the power meter.

1.7.7.1.1 Calibration Setup

Figure 1:38 Calibration Setup Diagram

Figure 1:39 Splitter Loss Measurement

1.7.7.1.2 Calibration Steps1. Setup as shown in Figure 1:38, using quality RF cables and

ensuring that the power meter is properly calibrated.

2. Set variable attenuator to 0 and record power reading.

3. Adjust RF traffic source until the maximum power for the AGC table is reached. Record the traffic source output power.

4. Ensure the variable attenuator has accurate 1 dB steps and return the variable attenuator to 0.

5. Setup as shown in Figure 1:39.

6. Determine power meter offset. (The offset is calculated by subtracting the value recorded in step 2 from the value recorded in step 5).

7. Apply offset to the power meter.

1.7.8 Notes Regarding the AGC Calibration ProcedureA few comments on APCR and AAR registers on the PHY. We are currently working on finalizing APCR and AAR values. These values will be the same for systems designed using the SoC and should not need to be changed by the customer.



RFSplitter

PowerMeter

FixedAttenuator

Termination



RFSplitter

PowerMeter

FixedAttenuator



The APCR value we are deriving is designed to work with the internal ADC. If the user chooses to use an external ADC, then the value needs to be changed.

AAR defines the jump attenuation values for the AGC, which is an inherent part of the PHY design and is fixed for all applications.

APCR and AAR can only be determined by Simulink models as they impact the PHY system performance. At this time determining APCR and AAR by other methods are extremely tedious and impractical. Therefore we are not able to provide a procedure for deriving APCR and AAR at this time.

Section 1.8 shows an AGC table that can be created based on above lab procedures.

1.8 AGC Programming TableThe AGC translation memory is defined by specifying the 10 data bits required by the SiGe Radio Reference Board to generate a required attenuation value. This is required because the SiGe radio board does not implement a linear binary attenuation. The memory is used to convert the linear binary attenuation value generated by the PHY to the bit pattern required by the radio.

Binary image of the Preamble/AGC memory that you should be using on the PHY is available on request. Note that the AGC table is made up of bits 21 to 12 in the memory.

1.8.1 Default Values for AGC Related RegistersThe value written to the RCR6.agcOffset should be 0, as no post- lock AGC adjustment should be made.

The values for APCR and AAR were chosen based on the simulated performance of the PHY. There is a possibility that these values need to be "tweaked" to optimize performance on the SoC reference kits.

#define DEFAULT_RCR0 0x00000356#define DEFAULT_RCR1 0x0056150C#define DEFAULT_RCR2 0x01001004 #define DEFAULT_RCR3 0x03A9DF4D#define DEFAULT_RCR4 0x0002DA27#define DEFAULT_RCR5 0x4a17e40#define DEFAULT_RCR6 0x00000000

#define DEFAULT_APCR0 0x09070C2B#define DEFAULT_APCR1 0x02F80552#define DEFAULT_APCR2 0x0217025C#define DEFAULT_APCR3 0x01A701DB#define DEFAULT_APCR4 0x01270178#define DEFAULT_APCR5 0x001C008D#define DEFAULT_AAR0 0x040E1A26#define DEFAULT_AAR1 0xFF000102#define DEFAULT_AAR2 0xE6F2FCFE#define DEFAULT_AAR3 0x000000DA

1.8.2 AGC Attenuation Table (Pin vs AGC[9:0] )The following table shows attenuation levels of various RF components and the corresponding value of the AGC[9:0] output of the MB87M3400 SoC. The second column shows the received signal attenuation. Refer to Figure 1:14 to locate IF, RF, ELNA, and ILNA attenuation points. Note that IF attunation is controlled by AGC[5:0], RF attunation is controlled by AGC[8:6], and ILNA is controlled by AGC[9]. ELNA control value is the same as ILNA; note that ILNA, ELNA both have only two attenuation levels.

MB87M3400


Table 1-10: Pin vs. Attenuation and Corresponding AGC Output ValuesWiLAN Map dBm IF att

dBRF att

dBELNA Att

dBILNA Att

dBTotal AGC

dB50-(IF att settting)

RF att settting

ELNA Att settting

ILNA Att settting

IF att binary

RF att binary

ELNA Att binary

ILNA Att binary AGCWORD AGC Table

Value

IF Table

Value

RF att TableValue

ELNA Att TableValue

0 -90 16.56 3.69 0 0 20.25 16 4 0 0 100010 001 1 1 1001100010 262 0x22, 0x1, 0x1,1 -89 17.87 3.69 0 0 21.56 17 4 0 0 100001 001 1 1 1001100001 261 0x21, 0x1, 0x1,2 -88 18.63 3.69 0 0 22.32 18 4 0 0 100000 001 1 1 1001100000 260 0x20, 0x1, 0x1,3 -87 19.39 3.69 0 0 23.08 19 4 0 0 011111 001 1 1 1001011111 25F 0x1F, 0x1, 0x1,4 -86 20.45 3.69 0 0 24.14 20 4 0 0 011110 001 1 1 1001011110 25E 0x1E, 0x1, 0x1,5 -85 21.89 3.69 0 0 25.575 21 4 0 0 011101 001 1 1 1001011101 25D 0x1D, 0x1, 0x1,6 -84 22.33 3.69 0 0 26.02 22 4 0 0 011100 001 1 1 1001011100 25C 0x1C, 0x1, 0x1,7 -83 23.32 3.69 0 0 27.01 23 4 0 0 011011 001 1 1 1001011011 25B 0x1B, 0x1, 0x1,8 -82 24.69 3.69 0 0 28.38 24 4 0 0 011010 001 1 1 1001011010 25A 0x1A, 0x1, 0x1,9 -81 25.57 3.69 0 0 29.26 25 4 0 0 011001 001 1 1 1001011001 259 0x19, 0x1, 0x1,10 -80 26.32 3.69 0 0 30.01 26 4 0 0 011000 001 1 1 1001011000 258 0x18, 0x1, 0x1,11 -79 27.21 3.69 0 0 30.9 27 4 0 0 010111 001 1 1 1001010111 257 0x17, 0x1, 0x1,12 -78 28.48 3.69 0 0 32.17 28 4 0 0 010110 001 1 1 1001010110 256 0x16, 0x1, 0x1,13 -77 29.41 3.69 0 0 33.1 29 4 0 0 010101 001 1 1 1001010101 255 0x15, 0x1, 0x1,14 -76 30.51 3.69 0 0 34.2 30 4 0 0 010100 001 1 1 1001010100 254 0x14, 0x1, 0x1,15 -75 31.62 3.69 0 0 35.31 31 4 0 0 010011 001 1 1 1001010011 253 0x13, 0x1, 0x1,16 -74 32.62 3.69 0 0 36.31 32 4 0 0 010010 001 1 1 1001010010 252 0x12, 0x1, 0x1,17 -73 33.44 3.69 0 0 37.13 33 4 0 0 010001 001 1 1 1001010001 251 0x11, 0x1, 0x1,18 -72 34.44 3.69 0 0 38.13 34 4 0 0 010000 001 1 1 1001010000 250 0x10, 0x1, 0x1,19 -71 35.52 3.69 0 0 39.21 35 4 0 0 001111 001 1 1 1001001111 24F 0x0F, 0x1, 0x1,20 -70 36.77 3.69 0 0 40.46 36 4 0 0 001110 001 1 1 1001001110 24E 0x0E, 0x1, 0x1,21 -69 37.87 3.69 0 0 41.56 37 4 0 0 001101 001 1 1 1001001101 24D 0x0D, 0x1, 0x1,22 -68 38.66 3.69 0 0 42.35 38 4 0 0 001100 001 1 1 1001001100 24C 0x0C, 0x1, 0x1,23 -67 39.49 3.69 0 0 43.18 39 4 0 0 001011 001 1 1 1001001011 24B 0x0B, 0x1, 0x1,24 -66 40.69 3.69 0 0 44.38 40 4 0 0 001010 001 1 1 1001001010 24A 0x0A, 0x1, 0x1,25 -65 41.88 3.69 0 0 45.57 41 4 0 0 001001 001 1 1 1001001001 249 0x09, 0x1, 0x1,26 -64 42.74 3.69 0 0 46.43 42 4 0 0 001000 001 1 1 1001001000 248 0x08, 0x1, 0x1,27 -63 44.26 3.69 0 0 47.95 43 4 0 0 000111 001 1 1 1001000111 247 0x07, 0x1, 0x1,28 -62 45.07 3.69 0 0 48.76 44 4 0 0 000110 001 1 1 1001000110 246 0x06, 0x1, 0x1,29 -61 40.69 7.84 0 0 48.53 40 8 0 0 001010 010 1 1 1010001010 28A 0x0A, 0x2, 0x1,30 -60 41.88 7.84 0 0 49.72 41 8 0 0 001001 010 1 1 1010001001 289 0x09, 0x2, 0x1,31 -59 42.74 7.84 0 0 50.58 42 8 0 0 001000 010 1 1 1010001000 288 0x08, 0x2, 0x1,32 -58 44.26 7.84 0 0 52.1 43 8 0 0 000111 010 1 1 1010000111 287 0x07, 0x2, 0x1,33 -57 40.69 11.31 0 0 52 40 12 0 0 001010 011 1 1 1011001010 2CA 0x0A, 0x3, 0x1,34 -56 41.88 11.31 0 0 53.19 41 12 0 0 001001 011 1 1 1011001001 2C9 0x09, 0x3, 0x1,35 -55 42.74 11.31 0 0 54.05 42 12 0 0 001000 011 1 1 1011001000 2C8 0x08, 0x3, 0x1,36 -54 44.26 11.31 0 0 55.57 43 12 0 0 000111 011 1 1 1011000111 2C7 0x07, 0x3, 0x1,37 -53 40.69 16.68 0 0 57.37 40 16 0 0 001010 100 1 1 1100001010 30A 0x0A, 0x4, 0x1,38 -52 41.88 16.68 0 0 58.56 41 16 0 0 001001 100 1 1 1100001001 309 0x09, 0x4, 0x1,39 -51 42.74 16.68 0 0 59.42 42 16 0 0 001000 100 1 1 1100001000 308 0x08, 0x4, 0x1,40 -50 44.26 16.68 0 0 60.94 43 16 0 0 000111 100 1 1 1100000111 307 0x07, 0x4, 0x1,41 -49 32.62 3.69 14 10.66 60.97 32 4 14 10 010010 001 0 0 0001010010 052 0x12, 0x1, 0x0,42 -48 33.44 3.69 14 10.66 61.79 33 4 14 10 010001 001 0 0 0001010001 051 0x11, 0x1, 0x0,43 -47 34.44 3.69 14 10.66 62.79 34 4 14 10 010000 001 0 0 0001010000 050 0x10, 0x1, 0x0,44 -46 35.52 3.69 14 10.66 63.87 35 4 14 10 001111 001 0 0 0001001111 04F 0x0F, 0x1, 0x0,45 -45 36.77 3.67 14 10.66 65.1 36 4 14 10 001110 001 0 0 0001001110 04E 0x0E, 0x1, 0x0,46 -44 37.87 3.67 14 10.66 66.2 37 4 14 10 001101 001 0 0 0001001101 04D 0x0D, 0x1, 0x0,47 -43 38.68 3.67 14 10.66 67.01 38 4 14 10 001100 001 0 0 0001001100 04C 0x0C, 0x1, 0x0,48 -42 39.49 3.67 14 10.66 67.82 39 4 14 10 001011 001 0 0 0001001011 04B 0x0B, 0x1, 0x0,49 -41 40.69 3.67 14 10.66 69.02 40 4 14 10 001010 001 0 0 0001001010 04A 0x0A, 0x1, 0x0,50 -40 41.88 3.67 14 10.66 70.21 41 4 14 10 001001 001 0 0 0001001001 049 0x09, 0x1, 0x0,51 -39 42.74 3.67 14 10.66 71.07 42 4 14 10 001000 001 0 0 0001001000 048 0x08, 0x1, 0x0,52 -38 44.26 3.67 14 10.66 72.59 43 4 14 10 000111 001 0 0 0001000111 047 0x07, 0x1, 0x0,53 -37 45.07 3.67 14 10.66 73.4 44 4 14 10 000110 001 0 0 0001000110 046 0x06, 0x1, 0x0,54 -36 41.88 7.97 14 10.66 74.51 41 8 14 10 001001 010 0 0 0010001001 089 0x09, 0x2, 0x0,55 -35 42.74 7.97 14 10.66 75.37 42 8 14 10 001000 010 0 0 0010001000 088 0x08, 0x2, 0x0,56 -34 44.26 7.97 14 10.66 76.89 43 8 14 10 000111 010 0 0 0010000111 087 0x07, 0x2, 0x0,57 -33 41.88 11.39 14 10.66 77.93 41 12 14 10 001001 011 0 0 0011001001 0C9 0x09, 0x3, 0x0,58 -32 42.74 11.39 14 10.66 78.79 42 12 14 10 001000 011 0 0 0011001000 0C8 0x08, 0x3, 0x0,59 -31 44.26 11.39 14 10.66 80.31 43 12 14 10 000111 011 0 0 0011000111 0C7 0x07, 0x3, 0x0,60 -30 45.07 11.39 14 10.66 81.12 44 12 14 10 000110 011 0 0 0011000110 0C6 0x06, 0x3, 0x0,61 -29 46 11.39 14 10.66 82.05 45 12 14 10 000101 011 0 0 0011000101 0C5 0x05, 0x3, 0x0,62 -28 40.69 16.77 14 10.66 82.12 40 16 14 10 001010 100 0 0 0100001010 10A 0x0A, 0x4, 0x0,63 -27 41.88 16.77 14 10.66 83.31 41 16 14 10 001001 100 0 0 0100001001 109 0x09, 0x4, 0x0,

"Error found on IF Atten position number ""56"""

should read 43 not 44 = 087 not 086



1.9 Tutorial on Frame Length Calculation for MB87M3400 802.16 SoC 802.16 frame timing is based on the front-end clock (FE_CLK). A sample is defined by the FE_CLK, and the total number of samples (= Nsample) in a frame is 0.5 * (frame duration)*(FE_CLK).

For example, for frame duration = 20 ms, total samples in a frame would be 80000 (with the assumption of FE_CLK = 8 MHz).

A symbol consists of (256 + cpLength) samples. So, for cpLength = 8, 80000 samples will take 80000/264 = 303 (0x12F) symbols. This is the number of symbols in a single 802.16 frame.

In 802.16, a frame does not have to contain an integer number of symbols. So, we express a frame in units of entire symbols plus a

number of samples. For this, we designed the SET_FRLEN message to accept the following parameters:

• Number of entire symbols (in other words, the symbol value at which the frame timer will wrap)

• Number of samples in the final symbol of the frame

Here, frameFinal is the number of samples in the final symbol of the frame, which is only a fractional symbol. Otherwise, all other symbols in the frame will contain exactly (256 + cpLength) samples.

In other words, to calculate the generator payload to be written in SET_FRLEN message, follow the procedure below (Examples 1 and 2):

Example 1:

1) Determine total number of samples in the frame: Nsamples = (frame duration) * FE_CLK / 2;

Example: for frame duration = 20 ms, FE_CLK = 8 MHzNsamples = (20 ms) * 8 MHz /2 = 80,000 Samples

2) Determine the frame length in entire symbols: frameLength = ceiling(Nsamples/(256 + cpLength)) [Unit = # of SYMBOLS]

Example: for Nsamples = 4330, cpLength = 8.frameLength = 80,000/ (256 + 8) = 303.03 SymbolsframeLength = 303 Symbols (rounded down to integer)frameLength = 304 Symbols (if symbols rounded up for register value)

3) Determine the number of samples in the final symbol in the frame: frameFinal = Fractional Symbol * (256 + cpLength) [Unit = # of Samples]

Example: for 303.03 Symbols, Fractional Symbol = 0.03FrameFinal = 0.03 x (256 +8)

= 7.92 Samples= 8 Samples (round off to integer)

4) frame duration = ((frameLength-1) * (256 + cpLength) + frameFinal) * 2/FE_CLOCK= (304 - 1) x 264 x 2) / 8 MHz= 20 ms

5) Find the generator payload in SET_FRLEN message:

Word1 = (frameFinal << 20 + frameLength)

MB87M3400


Example 2:

1) Determine total number of samples in the frame: Nsamples = (frame duration) * FE_CLK / 2;

Example: for frame duration = 2.5 ms, FE_XLK = 3.44 MHzNsamples = (2.5 ms) * 3.44 MHz /2 = 4300 Samples

2) Determine the frame length in entire symbols: frameLength = ceiling(Nsamples/(256 + cpLength)) [Unit = # SYMBOLS]

Example: for Nsamples = 4330, cpLength = 8.frameLength = 4330/ (256 + 8) = 16.29 SymbolsframeLength = 16 Symbols (rounded down to integer)frameLength = 17 Symbols (if symbols rounded up for register value)

3) Determine the number of samples in the final symbol in the frame: frameFinal = Fractional Symbol * (256 + cpLength) [Unit = # of Samples]

Example: for 16.29 Symbols, Fractional Symbol = 0.29FrameFinal = 0.29 x (256 + 8)

= 76.56 Samples= 76 Samples (round off to integer)

4) frame duration = ((frameLength-1) * (256 + cpLength) + frameFinal) * 2/FE_CLOCK= ( (17-1) x 264 + 76 ) x 2 / 3.44 MHz= (4224 + 76) x 2 / 3.44 MHz= (4300 x 2) / 3.44 MHz= 2.5 ms

5) Find the generator payload in SET_FRLEN message: Word1 = (frameFinal << 20 + frameLength)



1.10 Data Endianness Considerations with DSI Bus Access1.10.1 Word Access Through the DSI Bus

Example: The word 0x12345678 is shown

Figure 1:40 Word Access Example through DSI

to/from DSI Logic

MSB

LSB

D31

D0

D24D23

D16D15

D8D7

DSI data bus

78

56

34

12

byte 0

LD/ST RAM orcodeRAM

byte 1

byte 2

byte 312

3456

780001001000110100

0101011001111000

D31 is MSBit and D0 is LSBit Memory System is Little-Endian

Word Access Example: 0x12345678is being written or read

MB87M3400


1.10.2 Byte Access Through the DSI Bus

Example: 0x5A is being written to MSB location in a word

Figure 1:41 Byte Access Example through DSI

1.10.2.1 The Truth Table For DSI Bus Byte Access

Table 1-11: The Truth Table for DSI Bus Byte Access

to/from DSI Logic

MSB

LSB

D31

D0

D24D23

D16D15

D8D7

DSI data bus

NC

NC

NC

5A

byte 0

LD/ST RAM orcodeRAM

byte 1

byte 2

byte 35A

0000

000101101000000000

0000000000000000

D31 is MSBit and D0 is LSBit Memory System is Little-Endian(NC = No Change)

Byte AccessExample: 0x5A is being written or read

to MSB location in the current wordaddress (byte address 0x3)

DSI Address Bus A1 and

A0 LinesBE Signals

DSI Data Bus Lane (Data must appear on this bus lane)

00 1110 D[7:0]

01 1101 D[15:8]

10 1011 D[23:16]

11 0111 D[31:24]



1.11 Channel Delay CalculationThe following example shows how the channel delay between BS and SS can be calculated:

1. Assume the DL frame start time is 0x1 for this example. The SS syncs to and receives this burst; also the frame timer on the SS is cleared once sync is achieved which is due to “adjustTime” being set.

2. UL Initial Ranging (long preamble) burst is transmitted from SS to BS. Lets say UL burst start time is 102.

3. On the BS, it receives the initial ranging burst. The BS RSR9.p64Sample is 0x9a and the RSR9.p64 symbol is 101.

4. Calculate the channel delay for CP = 16. Channel Delay = 0x9A – (64 + 16) = 0x4A samples. If the value comes out to be negative then add another 64.

5. On the SS, write TCR1.offsetSample = 0x4A. Write TCR1.offsetSymbol = 0x1 because SS and BS are offset by 1 symbol because the DL burst start time was 0x1 and that is when the frame timer for SS was cleared to zero.

1.12 VOIP Applications for MB87M3400 SoCTo support VOIP functions for residential/SOHO applications, there are various options to interface an external VOIP chip to MB87M3400.

One of the most common solutions is to use the 10/100 Ethernet MAC Interface provided by MB87M3400 SoC to build a complete WiMAX & VOIP platform. An example of this interface is shown in Figure 1:42:

Figure 1:42 MB87M3400 Interface to a VOIP Chip

Most common off-the-shelf VOIP chip sets contain a 3-port Ethernet Switch with two external ports (MII or PHY interface). One of the two external ports is configured for WAN network connection (WAN), and the other one is configured for a local network connection (LAN). In our WiMAX application, the WAN network interface is used for connecting to network and the LAN port is interfaced to the Ethernet port of MB87M3400. The VOIP chip is programmed to accept VOIP packets and all other packets are

bridged to the LAN port. There are many options for using a VOIP chip. Some of the examples are AudioCodes (AC949), TI (TNETV1050), and BroadCom chip sets. Fujitsu also offers a full VOIP Macro for ASIC integration.

A top-level block diagram of WiMAX reference design enabled with VOIP is represented in Figure 1:43 and the VOIP module is shown in Figure 1:44.

Ethernet Switch

DSP Codec

RISC Engine

802.16PHY

ARCSub-System

LAN

TDM (Voice) Interface(SLIC or Analog Codec)

Network Interface10/100 Ethernet

WiMAX CHIPMB87M3400VOIP CHIP

(MII)Ethernet

MAC

Ethernet MAC

WAN

EthernetMAC

ARMSub-System

MB87M3400


Figure 1:43 VOIP-based WiMAX System

Figure 1:44 VOIP Module (MB87M3400-based)

FujitsuWiMAX

SoC

DDS

VCTCXO

ARMDebug Port

ARCDebug Port

FLASH

SDRAM

Control

20 MHZ Ref-Clock

FS Clock

Clock

SPI

GPIO

RS232C

I2C

Power Module

ADC

ADC

DAC

DAC

ARX_I_IN ±

ARX_Q_IN ±

TX_Q Analog

TX_I Analog

RX & TX Pwr Detect

AGC Control

RF Logic Control

Radio Module

VOIP ModuleRJ45Network

VoiceTelephone

Ethernet

FujitsuWiMAX

SoC

DDS

VCTCXO

ARMDebug Port

ARCDebug Port

FLASH

SDRAM

Control

20 MHZ Ref-Clock

FS Clock

Clock

SPI

GPIO

RS232C

I2C

Power Module

ADC

ADC

DAC

DAC

ARX_I_IN

ARX_Q_IN

TX_Q Analog

TX_I Analog

RX & TX Pwr Detect

AGC Control

RF Logic Control

Radio ModuleRadio Module

VOIP ModuleRJ45Network

VoiceTelephone

EthernetRS-232C

VOIP Module

Debug

VOIP Chip

RS232C

SDRAM

Ethernet

ArbiterMemory

Sequencer

FLASH

Ethernet

Ethernet

Switch

SLIC

Risc CPU

SRAMBUS

Interface

SPI LCD/KyPd

Fax

Phone

CO

ProcessorTDM

DSP

Engine

Voice DSP

WiMAXInterface



1.12.1 VOIP Chip Sets ExamplesThe block diagrams of these chips are given in Figure 1:45, Figure 1:46, and Figure 1:47.

Figure 1:45 show the block diagram of a CODEC VOIP Chip (AC949).

Figure 1:45 ODEC VOIP Chip for MB87M3400-based VOIP System

The block diagram of a VOIP chip from Texas Instruments is shown in Figure 1:46.

The block diagram of a VOIP chip designed at Fujitsu is shown in Figure 1:47.The design can be incorporated in an ASIC.

MIPS(4KEc 165MHz)

Keypad(8x8)

GPIO(8 to 52)

Serialflexible

VLYNQ(5-pin)

VLYNQ(3-pin)

USBHost

USBDevice

DisplayController

DMA4 channel


PHY(10/100)

PHY(10/100)

MAC

MACUART

MDIO, MII,& LED

I-Cache (16KB)

D-Cache (16KB)Regulator

CODEC2 channel

McBSP

McBSP

pDMA

telephonyinterface

EthernetSwitch(3 port)

PH

Y

RAM (4KB)

ROM (4KB)

Timers (x3)

Interrupt

DMA4 channelAC494

Port 2

Por

t 0P

ort 1

DSPAC49x Core

MB87M3400


Figure 1:46 TI VOIP Chip for MB87M34-based VOIP System

Figure 1:47 Fujitsu VOIP Macro for MB87M3400-based VOIP System

TelephonyInterfaceMcBSPMcBSP

VLYNQ™5 Pin

Codec2 Channel

SerialUARTGPIO

Keypad 8x8Clock/Power

Manager

DSP DMA

Ethernet Switch3 port

MACEthernet PHY

VoltageRegulator

TMS320C55x™DSP

MIPS R4000

TNETV1050/1055 IP Phone Processor

VLYNQ™3 Pin*

USB 1.1Host*

USB 1.1Device*

LCDController


Ethernet PHY MAC

DMA

*Available only on TNETV1050

√oiceDSP™

Interrupt

AHB BridgeAHB Arbiter

BUS Bridge

Arbiter

PLL

JTAG

ClockControl

MemorySequencer

AHB Dec/Mux

AHBAPB

BridgeGPIO GPIO

PCM

SPI

UART

I2C

FLASH

SDRAM

EthernetPort #1

EthernetPort #2

LCDKeypad(GPIO)

SPI

UART

I2C

FLASH

SDRAM

LCDKeypad(GPIO)

AH

B B

US SPORT

SPORT DMA

SRAM

Co-Processor

DSP Core

Ethernet Switch

10/100 MAC

10/100 MAC

LoadStore

XYMemory I-Cache

AuxRegister

AuxRegisters

IRQ

DebugPort

DebugPort

Load / Store

RISC Core

IRQ I-Cache

HOST Processor

Debug Port

Debug Port

DP SRAM

Interrupt

DebugPort 1DebugPort 2

RefClock

JTAG



1.13 T1/E1 Application1.13.1 Introduction to T1/E1In time division multiplexing (TDM), the channel is divided into time slots, each user being alloted one time slot. The duration of a time slot depends on the number of channels being multiplexed and the bandwidth of the transmit medium.

In commercial multiplexing systems, the primary rate is defined as a 2.048 Mbps digital stream that is a time-division-multiplexed combination of 30 basic 64-kbps channels. The 30-channel primary rate is the European E1 electrical standard, while in North America

and Japan the primary rate contains 24 64-kbps channels (thus giving a bit rate of 1.544 Mbps) and is called the T1 carrier. A T1/E1 system can be implemented to work with the MB87M3400 SoC when Motorola MPC8560 PowerPC is used in external mode. MPC8560 contains up to eight TDM interfaces for T1/E1 application.

1.13.2 MPC8560 TDM Interface for T1/E1 ApplicationA block diagram of the Motorola MPC8560 is shown in Figure 1:48.

Figure 1:48 MPC8560 Block Diagram with TDM Interface

One major block of the MPC8560 is a high-performance embedded e500 core processor. The e500 core, with its 256 Kbytes of level-2 cache, implements the enhanced Book E instruction set architecture and provides unprecedented levels of hardware and software debug support.

A second major block is the Communications Processor Module (CPM). The CPM of the MPC8560 supports three high-performance fast communications channels (FCCs) for 155 Mbps ATM and Fast Ethernet, and up to 256 full-duplex, time-division-multiplexed (TDM) channels using two multi-channel controllers (MCCs).

A key feature of MPC85604 is the support for T1/E1 Carrier using upto eight TDM interfaces. The TDM interface will provide the following:

1. Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to eight TDM interfaces.

DDR SDRAM Controller

Local Bus Controller

e500Coherency

Module

e500 Core

32 KB L1I Cache

RapidIO-816 Gb/s

PCI-X 64b133 MHz

MII, GMII, TBI,RTBI, RGMIIs

32 KB L1D Cache

Core Complex Bus

OCeaNRapidIO Controller

PCI/PCI-X Controller

DMA Controller

10/100/1000 MAC

10/100/1000 MAC

256KBL2-Cache/

SRAM

Ser

ial I

nter

face

s

TC

- L

ayer

Tim

e S

lot A

ssig

ner

Tim

e S

lot A

ssig

ner

ProgrammableInterrupt Controller

CPMSerialDMA

ROM

I-Memory

DPRAM

RISCEngine

Parallel I/O

Baud RateGenerators

CPMInterrupt

Controller

Timers

MCC

MCC

FCC

FCC

FCC

SCC

SCC

SCC

SCC

SPII2C

DDRSDRAM

GPIO32b

IRQs

UTOPIAs

MIIs

TDMs

I/Os

I2C Controller

4. See MPC8560 PowerQUICC III Integrated Communications Processor User Manual Rev. 2.0 for details.

MB87M3400


2. Time-slot assigner (TSA sub-block) supports multiplexing of data from any of the serial communication controllers (SCCs) and fast communications channels (FCCs) onto eight time-division-multiplexed (TDM) interfaces. The time-slot assigner supports the following TDM formats:

a. T1/CEPT lines

b. T3/E3

The MPC8560 provides TDM support using its Communications Processor Module (CPM). ATM TC-layer functionality is

implemented internally to support applications receiving ATM traffic over standard serial protocols (T1, E1, xDSL) via its serial interface ports. Section 1.13.3 MPC8560 Communication Processor Module provides a brief description of the CPM. (Refer to MPC8560 PowerQUICC III Integrated Communications Processor User Manual Rev. 2.0 for a complete description of CPM).

1.13.3 MPC8560 Communication Processor ModuleA block diagram of the Communication Processor Module is shown in Figure 1:49.

Figure 1:49 MPC8560 Communication Processor Module Block Diagram

Two multichannel controllers (MCCs) can handle an aggregate of 256 x 64 Kbps HDLC or transparent channels, multiplexed on up to eight TDM interfaces. The MCC also supports super-channels of rates higher than 64 Kbps and subchanneling of the 64 Kbps channels.

Protocol data units (PDUs) can navigate through the various MPC8560 I/O ports, for example, data processed by the MPC8560 CPM (as it is received and transmitted through the UTOPIAs, MIIs,

and TDMs associated with the CPM unit) and the local bus. The local bus provides the interface of MPC8560 to Fujitsu MB873400 SoC.

Figure 1:50 shows a block diagram of the TSA. Two serial interface (SI) blocks in the MPC8560 (SI1 and SI2), can be programmed to handle eight TDM lines. TDM channels on SI1 are referred to as TDMa1, TDMb1, TDMc1, TDMd1; TDM channels on SI2 are TDMa2, TDMb2, TDMc2, and TDMd2.

Dual-PortRAM

ROM

2 MCCs 3 FCCs 4 SCCs SPI I2C

4 Timers

Parallel I/O Ports

Baud Rate Generators

Serial Interface (SI) and Time-Slot Assigner (TSA)

Communications Processor

To SIUInterrupt

ControllerBus Interface SDMA

Interrupt Bus

Peripheral Bus

System Bus

Local Bus



ATM TC-layer functionality is implemented internally to support applications receiving ATM traffic over standard serial protocols

(T1, E1, xDSL) via its serial interface ports (Figure 1:50).

Figure 1:50 MPC8560 Serial Interface Block Diagram

Each SI can connect to four independent TDM channels. Each TDM can be one of the following: T1 or E1 lines.

The TSA implements both internal route selection and time division multiplexing (TDM) for multiplexed serial channels. The TSA supports the serial bus rate and format for most standard TDM buses, including T1 and E1 highways, pulse-code modulation (PCM) highway, and the ISDN buses in both basic and primary rates. The two popular ISDN basic-rate buses (interchip digital link (IDL) and general-circuit interface (GCI), also known as IOM-2) are supported.

Because each SI supports four TDMs, it is possible to simultaneously support a combination of up to eight T1 or E1 lines, and basic-rate or primary-rate ISDN channels.

At its most flexible form, the TSA can provide four separate TDM channels, each with independent receive and transmit routing assignments and independent sync pulse and clock inputs. Thus, the TSA can support eight independent, half-duplex TDM sources, four in reception and four in transmission, using eight sync inputs and eight clock inputs.

MUX

To: SCC1 SCC2 SCC3 SCC4 FCC1 FCC2 FCC3

SCC1

TDM A, B, C, DStrobes

TDM A, B, C, DPins

Nonmultiplexed Serial Interface (NMSI) Pins

Note:The CPM mux and the MCCs are not part of the SI.(See their respective chapters for details.)

SCC2 SCC3 SCC4 MII1/UTOPIA

8/16

MII2/UTOPIA

8

MII3

Rx

T cl

ocks

R c

lock

s

T cl

ocks

T sy

nc

R s

ync

R c

lock

s

TxTx

RouteSI RAM

Tx/RxRAM

Control

ModeRegister

CommandRegister

Multi-ChannelControllers

(MCCs)

Time-SlotAssigner (TSA)

RAM

Peripheral Bus CPM Mux

ClockRoute

StatusRegister

Channel #

ShadowAddressRegister

MUX MUX MUX MUX MUX MUX

MB87M3400


1.13.4 Reference Board for T1/E1The MB87M3400 SoC Reference Board in external mode application shown earlier in Section 1.4.2 can be adapted for T1/E1

application. An implementation is shown in Figure 1:51 for SS or BS for TDD or HDX FDD.

Figure 1:51 T1/E1 Application Example Using Reference Board and PowerPC Module

Radio Module



Power Module

VCTCXOPowerPC

Debug Port

FLASH

I2C

DDRSDRAM

Temp.Sensor

TDM/Serial IF

(Network IF)

T1/E1

T1/E1

...

DDS

FS Clock Clock IN

SPI

DSIMB87M3400FujitsuChip PowerPC

MPS8560



2. MB87M3400 Frequently Asked Questions2.1 FAQ on Standards, System Design, and TestingQ. What test equipment can be used for IEEE802.16-2004 protocol

testing?

A. Agilent 89650S wideband VSA including E4440A spectrum analyzer, 80MHz ADC, vector signal analysis software and hardware connectivity equipment can be used. However, there are other protocol analyzers available on the market.

Q. How can a temperature sensor be connected to the MB87M3400?

A. A temperature sensor can be connected to MB87M3400 through the I2C bus.

Q. What are the timing requirements for SDRAM access from MB87M3400?

A. The timings depend on the SDRAM chip used. A set of example timing requirements for Micron MT48LC4M32LFF5-10 SDRAM is shown below for an 80 MHz SDRAM clock.

The value for the register is 0x00111737 (no margin) or 0x00222959 (with margin).

Note: Real value for SDRAM control should be 'program value + 1' clock.

Calculation is as follows.4K / 64 ms refresh: 64 ms/4K = 15.625 µs1 cycle clock for 80 MHz: 1000/80 = 12.5 ns15.625 µs/12.5 ns = required 1250 cycles for refresh = 0x4E2

Q. Is it possible to add a third-party application on top of the existing Fujitsu SS solution on ARM processor?

A. Yes. On its SS reference platform, Fujitsu provides RTOS specific BSP, device drivers, 802.16-2004 SS-UMAC object code, and the SS management application, forming a full 802.16-2004 SS solution. If the customer wishes to develop an application additional to the above configuration (such as a user LCD/keypad-based user interface, etc.), s/he can do so by building the user application with Fujitsu-provided components as above and the RTOS kernel/libraries. It is the customer’s responsibility to obtain a license to use the RTOS kernel and libraries.

Q. Can another RTOS be ported to the on-chip ARM processor?

A. Yes. All the hardware blocks and interfaces surrounding the on-chip ARM processor have been extensively documented and are available to customers who wish to port an operating system of choice to MB87M3400.

2.2 FAQ on Testing and FTRP (Fujitsu Test/Reference Program)Q. What is the“loopback test”? What is the relation of the loopback

test to the PSAP/LMAC?

A. The loopback test utility (a part of the Fujitsu Test/Reference Program) is for test purposes only; it has nothing to do with PSAP/LMAC firmware. The loopback test has a completely different data/control interface and memory map than PSAP/LMAC firmware. The loopback utility is not for UMAC development. UMAC developers must follow the PSAP/LMAC interface specifications.

Q. What CP length and frame length is used during the loopback test?

A. CP length is fixed at 8 and the frame length is fixed at 20ms.

Q. Does the loopback test utility use a standard burst?

A. The loopback test utility transmits a single 802.16-2004 compliant burst as defined in the standard.

Q. How is the DDS reference clock set in loopback levels 3 and 4?

A. Loopback test utility initializes PHY and automatically sets the DDS reference clock to 40MHz. For level3 and level4 to successfully pass, the OFDM PHY front end clock must be running.

SDRAM memory timing register (offset 0x48)

Bit Spec value (matched) value (with margin)

cfg_twr[22:20] 15ns 0x1 0x2

cfg_trcd [18:16] 20ns 0x1 0x2

cfg_trp [14:12] 20ns 0x1 0x2

cfg_trc [11:8] 100ns 0x7 0x9

cfg_tras [6:4] 50ns 0x3 0x5

cfg_trfc [3:0] 100ns 0x7 0x9

SDRAM refresh interval register (offset 0x4C)

Bit Spec value

ref_int [11:0] 4K, 64ms 0x4E0

MB87M3400


Q. How can an analog loopback be placed on MB87M3400 analog I/Q terminals?

A. Connect Tx_I_out ± to the Rx_I_in ± and Tx_Q_out ± to the Rx_Q_in ± to create an analog loopback.

Q. How can a digital loopback be placed on MB87M3400 digital I/Q terminals?

A. Connect DTX_I_OUT [9:0] to DRX_I_IN[9:0] and connect DTX_Q_OUT[9:0] to DRX_Q_IN[9:0].

Q. How can OFDM PHY’s transmit qualities be measured in the most basic sense?

A. Fujitsu provides a complete test suite (FTRP), which includes the advanced loopback test utility. That utility is capable of sending any type of burst out from the PHY and receiving it in a loopback setting. Test equipment can be connected to MB87M3400 I/Q outputs to observe and measure the output burst.

Q. Loopback test at level 4 fails. What could be wrong?

A. There could be many things happening. First off, make sure that the front-end clock (sampling clock) is supplied to MB87M3400. Next, check the loopback cables and, if analog loopback is used, check and calibrate the voltage levels on the I/Q output buffers.

Q. What is the JTAG port on MB87M3400? Can it be used for system debugging?

A. It is the standard IEEE1149.1 Boundary Scan connector. Although it can be used to test the PCB, it has no usage for software development or system debugging and bring-up. The debug ports for on-chip ARM and ARC RISC processors are JTAG based too, but they are marked in a different way to prevent confusion with this JTAG boundary scan port.

Q. Why does the MB87M3400 support BPSK 3/4?

A. Although BPSK 3/4 is not a part of the IEEE802.16-2004 standard, MB87M3400 supports it as an additional feature.

Q. What is the maximum carrier frequency offset tolerated by the MB87M3400 demodulator?

A. This depends on carrier frequency and channel bandwidth. For example, for 3.5 MHz channel bandwidth and 3.5 GHz, OFDM PHY can discern a frequency offset of 8 ppm.

Q. Is the maximum tolerable carrier frequency offset for BS or SS?

A: It is the same for both BS and SS configurations. However, the BS oscillator is required by the standard to be within 8ppm.

2.3 FAQ on Radio InterfaceQ. What is the relation between the RF_Enable signal and RX_EN,

TX_EN, and TR_SW signals?

A. Activation of RF_Enable signal is required for RX_EN, TX_EN, and TR_SW signals to become active.

Q. Is it possible to use the AD8345 as a modulator connected to the analog I/Q port of MB87M3400?

A. Yes.

Q. Can the MB87M3400 I/Q and RF control signals be interfaced with any radio?

A. Yes. They can be interfaced to any RF solution as long as the RF to baseband interface requirements are met.

Q. Does MB87M3400 have any built-in digital filters to reject the adjacent channel?

A. No. MB87M3400 is a baseband processor.

2.4 FAQ on MB87M3400 Pins and Electrical CharacteristicsQ. What is the worst case MB87M3400 power consumption?

A. At VDD = 1. 8 V and VDE = 3. 3 V, the worst case power consumption is 5.15 W for the core (1.8 V) and 0.25 W for I/O (3.3 V). The total worst case power consumption is 5.4 W.

Q. Does MB87M3400 need a heatsink?

A. The heat transfer will largely depend on the system design. The use of a heatsink should be evaluated as a part of system design.

Q. What is the MB87M3400 power consumption in external processor mode?

A. In external processor mode, the on-chip ARM processor and associated on-chip peripherals are disabled. This reduces the typical power consumption to 1.95 W and the worst case consumption to 4.5 W for 1.8 V. For 3.3 V the figures are 0.2 W and 0.4 W, respectively.



Q. What is the common mode voltage (VCM) for the analog I and Q ports?

A. For I and Q input ports (ADC), the common mode voltage (Signal Ground SG) is 0.55 V. For I and Q output ports (DAC), the common mode voltage is 0. (Please see “MB87M3400 The Fujitsu WiMAX 802.16-2004 SoC Datasheet.” A 75Ω resistor is connected to analog ground).

Q. What is the frequency range of I and Q inputs and outputs?

A. MB87M3400 uses 100Msps ADCs and DACs. Up to 50MHz is supported.

Q. Is 10-bit accuracy enough for the I/Q interface?

A. A 10-bit converter is sufficient provided that you have an external analog filter on the DAC side which can meet the transmit mask specification, and on the ADC side you have sufficient analog filtering to take out the non-adjacent channel and a portion of the adjacent channel. The choice of 10 or 12 bit converter is simply a tradeoff between the requirements on the external analog filters with the dynamic range requirements on the ADC/DAC. The choice of 10 or 12-bit converter will also affect the chip power consumption.

Q. Would the S/N ratio be better if 12/14-bit accuracy was used with I/Q interface?

A. The main reason to have more bits on the Rx side is to be able to tolerate more out-of-band interference without saturating the converter. The S/N is adequate with a 10-bit design and you won't see any significant improvement with 12/14-bit converters.

Q. Can external ADCs and DACs be used with the MB87M3400, instead of the on-chip ADCs and DACs?

A. Yes. MB87M3400 provides a digital I/Q interface as well as an analog one. It is possible to use external ADCs and DACs with higher accuracy if desired.

Q. Is a low-pass filter (LPF) required after I/Q interface?

A: It depends on the integrated circuit to which the MB87M3400 I/Q ports are connected. If this chip does not already have an integrated LPF, then an external LPF is needed at MB87M3400 I/Q ports.

Q. What does Fujitsu recommend for the connection of unused pins on MB87M3400?

A. Fujitsu recommends that the basic rules be followed. These rules can be summarized as follows: Output pins, can normally be left open. For an input pin, if there is no internal (on-chip) pull-up or pull-down resistor and if the logic level on this input does not matter, you can normally tie it to GND. Please refer to “MB87M3400 The Fujitsu WiMAX 802.16-2004 SoC Datasheet” for pin descriptions and to find out whether they have internal pull-up of pull-down.

Q. What are SED (symbol error display) pins?

A. SED (symbol error display) pins are for PHY testing. These pins should not be used.

Q. What are PWR_RESET and EXT_RESET pins? How are they different?

A. The PWR_RESET pin is used to issue a full reset to MB87M3400. EXT_RESET pin is for resetting the on-chip PSAP/LMAC (ARC) processor only. The external processor asserts EXT_RESET to hold the on-chip ARC processor in reset condition during the PSAP/LMAC firmware code download.

Q. In external processor mode, can BOOT [1:0] pins be tied to GND?

A. In external processor mode, BOOT[1:0] pins are not used. They can be tied to GND.

Q. What is the RF_ENABLE pin connected to?

A. The RF_ENABLE pin is connected to the external processor through the connector. This signal is used only in external processor mode to receive RF_ENABLE control from the external processor. In the internal processor mode, this pin is not used, and the RF_ENABLE signal should be generated internally by the on-chip ARM processor through the internal ARM GPIO signal.

Q. How is RF_ENABLE control provided in internal processor mode?

A. In internal processor mode, the RF_ENABLE pin is not used, and the RF_ENABLE signal should be generated internally by the on-chip ARM processor through a dedicated internal ARM GPIO signal. Refer to “MB87M3400 The Fujitsu WiMAX 802.16-2004 SoC Programming Guide” for more information.

MB87M3400


Q. What are pins BS_SYNC_OUT and BS_SYNC_IN connected to?

A. These pins are for assisting the frame timer synchronization between multiple BSs. On the Fujitsu Reference Board, these signals are connected to the external processor through a connector.

Q. What are the power-up and power-down sequences and timings?

A. Fujitsu recommends the following sequences for dual-power supply (VDDE, VDDI) devices:

On power-up, the Reference Board design ensures that the 3.3 V supply will start with a delay twice as long as that of the 1.8 V supply. The +6 V regulator has its shutdown pin connected to +3.3 V, ensuring that it won't become active until the +3.3 V supply has properly come up. On power-down, comparators U21 and U24 are designed to check the incoming power rail. The RC circuit for the +6 V shutdown will decay quicker than the 3.3 V shutdown, causing the +6 V supply to shutdown first. The 1. 8 V supply will shutdown on its own when the 8.5 V_INT supply dies.

Note that AVD must not be supplied continuously for more than 1 minute while VDDE and VDDI are off. If the time exceeds 1 minute, it may affect LSI reliability.

Also, please note the restrictions on voltage levels of external signals: The voltage level of analog signals must not exceed that of the power supply by more than 0.5 V or should not be lower by more than 0.5 V below GND (0 V). Otherwise, it may cause permanent damage to the LSI.

Q. What are the setup and hold timings for the DSI bus?

A. For data input to MB87M3400, tsetup = 2 ns and thold = 0.

Q. On which edge of LB_CLK does the MB87M3400 read/write data to/from the DSI bus?

A. It is always on the rising edge of LB_CLK.

Q. What’s the maximum data rate on the DSI bus? Is it adequate for 20MHz channel bandwidth?

A. The DSI bus typically operates at 80 MHz and it is 32-bits wide. The data rate supported by the DSI bus is therefore much higher than that of 20 MHz channel bandwidth.

Q. What are the main features of the DSI bus?

A. DSI is a synchronous bus interface used for the external processor configuration (typically used for BS implementation). An external processor running the 802.16-2004 UMAC layer (such as Motorola PowerPC 8560) can be connected to the DSI bus. For a full-duplex BS implementation, two MB87M3400 SoCs can be connected to the same DSI bus. In this case, the external processor will be the master and SoCs will be the slaves. The physical pins of DSI interface are shared with external memory bus. This means the external memory interface is disabled in the external processor mode and the external processor must use its own memory subsystem.

For optimum data transfer, the external processor bus clock should be run at a multiple of 80MHz. Synchronizing logic synchronizes the external processor data transfer at the beginning of the DSI clock cycle and generates wait signals to extend data latency over the DSI clock cycle. Details of this interface can be found in “MB87M3400 The Fujitsu WiMAX 802.16-2004 SoC Datasheet.”

2.5 FAQ on Fujitsu Reference BoardsQ. Why is the output of DVT4564A (VCTCXO) connected to the

AD8051 and then to CY2305 through an inverter, instead of making a direct connection between DVT4564A and CY2305?

A. The VCTCXO has a 1VPP AC coupled output, which is not suitable for the clock buffer.

Q. What does “NNP” mean in the Reference Board schematics?

A. “NNP” means the component in question will not be normally assembled (populated).

Q. When AD9857 is used, can it also be used to provide the sample clock to MB87M3400 as the SAMPL_CLK_2X signal, synchronizing the two chips?

A. Yes. You can use external clock from AD9857.

Q. How is the DDS output frequency programmed on the Fujitsu Reference board?

A. There are two parts of DDS configuration. (a) Setting the reference input clock to the DDS: MB87M3400 provides the reference clock to the DDS chip. The frequency of this signal is determined by sending a SET_DDS message to the PSAP/LMAC firmware. The choices are: No clock, 40, 80, or 160 MHz. By default, PSAP/LMAC firmware initializes this clock to

Power-on sequence:

VDDI (internal) VDDE (external) AVD (analog) Signal (including analog)

Power-off sequence:

Signal (including analog) AVD (analog) VDDE (external) VDDI (internal)



40 MHz. (b) Setting the frequency of DDS output: To change the DDS output clock frequency, the DDS chip needs to be controlled (programmed) through the SPI interface of MB87M3400. Refer to the DDS chip datasheet for more information on specifics of DDS programming.

2.6 FAQ on UMAC/LMAC InterfaceQ. Why can’t a READY message be received after PSAP/LMAC is

downloaded and started?

A. Make sure OFDM PHY front-end clock is supplied to MB87M3400.

Q. What is the significance of “sequence number” found in control/status structures such as TCT, RBCT, RSI?

A. “Sequence number” is intended to function as a vehicle for burst control and management by UMAC and LMAC, for example, when BS-UMAC generates RBCTs to acquire uplink bursts and in turn, PSAP/LMAC generates RSIs to report the status of the acquisition. Then the BS-UMAC can associate RBCTs and RSIs through the “sequence number” fields. Note that the UMAC must use unique sequence numbers for adjacent bursts. Since sequence number is only a 4-bit field, after 16 unique numbers it will have to repeat, but this is not a problem because 16 bursts provide enough margin to distinguish and identify bursts from one another. On SS, sequence numbers are not as important as in BS. However, they must still be provided uniquely by UMAC because many processes within PSAP/LMAC depend on varying sequence numbering in adjacent bursts.

Q. What are the absolute physical address of the on-chip memories (such as Code RAM, LD/ST RAM) as seen by the external processor?

A. The address of Code RAM and LD/ST RAM depends on your board design. Fujitsu specifies only the relative addresses. The physical address of these memories will depend on the memory map of the address decoding logic on your board. These memories will appear just like any other bus peripheral (through the DSI bus). You need to create a memory map for your board and employ address decoding and chip select circuits to select and address these memories. The relative addresses, as seen through the DSI bus, are as follows: Code RAM is at DSI bus address 0 to 0xFFFF and LD/ST RAM is at DSI bus address 0x10000 to 17FFF.

Q. Should BS-UMAC calculate the HCS field when sending out an FCH burst?

A. BS-UMAC should set the TCT properly to indicate that the burst type is FCH. PSAP/LMAC will then calculate and insert the HCS field.

Q. Are the CRC parts in MAC PDUs included in the TCT byte length field?

A. Yes. Although the CRC is calculated by LMAC, UMAC still needs to allocate the CRC area by padding the MAC PDU with 4 bytes. The PSAP/LMAC will fill these bytes with the result of the CRC calculation. The number of bytes in TCT reflects all these bytes, including the CRC bytes.

Q. Can some of the TCTs written by UMAC belong to the next frame, rather than the current one?

A. Yes, provided that they contain proper frame sequence numbers. PSAP/LMAC processes the frame sequence number in the TCTs and transmits the associated bursts in their respective frames.

Q. What is the length field in RBCT? How does it differ from the length field in TCT?

A. This is the length of burst in OFDM symbols. For example, if the data is 11 bytes long and the burst profile is BPSK, then the burst will occupy 3 OFDM symbols. The length field in TCT is, however, in bytes. Therefore, the corresponding TCT for the above example should have a length field of 11. Transmitting 11 bytes in BPSK takes 3 OFDM symbols. Therefore, we use “3” in RBCT to receive those 11 bytes transmitted.

Q. When the CI bit in the MAC PDU header is set, MAC PDUs with a length less than 10 bytes do not get thru. Why?

A. According to IEEE802.16-2004, the minimum MAC PDU length is 10 bytes when CI bit is set.

Q. What does TXLOW interrupt indicate?

A. TXLOW interrupt signals that the preset TX watermark level has been reached, which indicates that MAC_TX_BUFFER is ready to accept more data for transmission.

Q. What does RXHIGH interrupt indicate?

A. RXHIGH interrupt signals that the preset RX watermark level has been reached, which indicates that MAC_RX_BUFFER is getting full and UMAC must drain some data as soon as possible.

MB87M3400


Q. Is it OK for UMAC to modify both IP and OP for a certain data structure in the UMAC/LMAC interface as a part of recovery when a PSAP/LMAC exception occurs?

A. No. UMAC is allowed to modify one pointer depending on the particular data structure in question. The best method of recovery would be to remedy the cause of the exception and modify the pointer for which UMAC is responsible. PSAP/LMAC will try to resume traffic from the frame boundary if the conditions that caused the exception are no longer extant.

Q. What is the best time to initialize PSAP/LMAC watermark levels and configuration words?

A. When PSAP/LMAC is started up, UMAC should wait until it gets a READY message from PSAP/LMAC. This means PSAP/LMAC has completed initializing all the data structures and is waiting in idle for further initialization by UMAC. At this time, UMAC can set the configuration words, watermark levels, etc.

Q. What is the best approach for successful transmission?

A. Due to separate buffer implementation, writing the transmission data and TCTs are independent of each other. However, transmit data and control streams are naturally associated with each other and some measures must be observed. Here is the typical procedure to be observed by UMAC:

– Write some data to MAC_TX_BUFFER

– Write the TCT to TX_CTRL_BUFFER for the data just written. When PSAP/LMAC senses that a TCT has been written, it starts draining data from the MAC_TX_BUFFER. Therefore, it is important that at least some data has been deposited in the MAC_TX_BUFFER before issuing a TCT. Do not write TCT first. If you do, PSAP/LMAC will find no data in MAC_TX_BUFFER and raise an exception.

– In the course of normal operation, data can be written as soon as it is available without waiting for TXLOW watermark interrupt, provided that free space is available. You don’t have to use TXLOW interrupt. It is a convenience feature. You can write data anytime you want if there is any room in MAC_TX_BUFFER.

Q. Given that the sizes of MAC_TX_BUFFER and MAC_RX_BUFFER are 8 KB each, how does PSAP/LMAC handle bursts larger than 8 KB?

A. These buffers are implemented as circular buffers, each having an IP (input pointer) and an OP (output pointer). IP is maintained by the feeder and OP is maintained by the drainer of the corresponding buffer. When maintained properly, these circular buffers appear to be “endless” and can handle much larger bursts.

Q. What happens if the size of the transmit burst is larger than the size of MAC_TX_BUFFER?

A. After UMAC writes some data to MAC_TX_BUFFER, it writes a TCT into TX_CTRL_BUFFER. This event triggers the transmit process in PSAP/LMAC and data starts being drained from MAC_TX_BUFFER. At this time, while PSAP/LMAC drains it, UMAC keeps on writing transmit data to MAC_TX_BUFFER. This process goes on until UMAC runs out of transmit data. In a typical BS or SS, new transmit data will always be flowing in from the Ethernet interface. Therefore, the process will go on forever. At this point, MAC_TX_BUFFER appears to be of virtually infinite size.

Q. Given that PSAP/LMAC on SS automatically receives downlink bursts based on DLFP and DL_MAP, how does the descrambler work?

A. PSAP/LMAC automatically re-initializes the randomizer as specified by IEEE802.16-2004 Section 8.3.3.1. There is no need for UMAC intervention.

Q. There are control bits in TCT and RBCT to enable and disable the scrambler and the descrambler, respectively. When do the scrambler and descrambler get disabled?

A. The scrambler and descrambler should be enabled all the time.

Q. What value should be written in the RBCT field: “Length of Time in Symbols from the Start of the Search before searchFailed is asserted”?

A. This field refers to the length of the search window in which a search for a UL long preamble is conducted. The BS-UMAC should adjust this length based on the length of the contention slot it opens.

Q. On SS, how is the scrambler seed obtained?

A. The scrambler seed on SS is automatically derived by PSAP/LMAC based on the frame sequence and is used in receiving DL bursts. This procedure is specified in IEEE802.16-2004.



Q. Can the descrambler on SS temporarily be disabled during system debugging?

A. No. The descrambler on SS is enabled all the time as per the standard. There is no way to disable the descrambler at the SS receiver. PSAP/LMAC automatically receives DL with descrambler enabled. It is not possible to disable it.

Q. How can UMAC follow the exact frame timing so that it can better synchronize?

A. For UMAC-frame synchronization, MB87M3400 outputs a pulse at each frame. This can be connected to an interrupt input of the UMAC processor. By that, UMAC will be aware of the frame timing and schedule transmission and reception accordingly. The pulse is output on the ft_int pin of MB87M3400. The width of the pulse is about 160 ns (assuming the OFDM PHY operates at 100 MHz). The exact position of the pulse with respect to the frame is programmable. So, UMAC will need to tune the pulse position based on its latencies and scheduling overhead. To change the position of this pulse, send a SET_REG message to the PSAP/LMAC using FTINTR0 OFDM PHY register as the message argument. By default, PSAP/LMAC sets this pulse to occur at the beginning (0th symbol) of the frame.

Q. On BS, must transmission data for frame n+1 sometimes be written during frame n?

A. Yes. In 802.16-2004 frames are contiguous. That means, if you want a burst to be transmitted in the very first symbol of frame n+1, you must give it to PSAP/LMAC before that frame starts. This is usually the case for a BS, where an FCH burst is transmitted in the very beginning of each frame. A convenient way for UMAC to achieve this is as follows:

(a) Set ft_int pulse to occur some time earlier than the start of frame

(b) Upon receiving the ft_int pulse, start writing TCTs belonging to the imminent frame

(c) Write all TCTs ordered by the starting symbol number

Note that UMAC should be able to generate transmission data earlier than it is actually needed. The UMAC developer will need to determine the time offset in step (a) above based on his/her particular UMAC implementation and scheduling. A small additional offset is also needed to cover up for PSAP/LMAC processing latency.

Q. What is the typical PSAP/LMAC latency from the point when UMAC writes the TCT to the point when the OFDM PHY actually gets programmed by PSAP/LMAC for the transmission?

A. The time needed by PSAP/LMAC from “TCT Write” to the actual programming of the OFDM PHY for the transmission is not constant and varies based on PSAP/LMAC’s load. If there are a lot of data waiting to be processed, it will take PSAP/LMAC more time to start processing that particular TCT. On top of this, there is the processing delay, which varies based on numerous factors, such as the burst length, encryption, CRC and HCS insertion, etc. Overall, PSAP/LMAC has been designed as a very low latency firmware. In most cases, the system will need to be tuned during the system integration and bring up phase to perform at the optimum level.

Q. What triggers the transmission in PSAP/LMAC?

A. The data transmission is triggered by a change in TX_CTRL_BUFFER IP (input pointer) as a result of a TCT write by UMAC. After the trigger, PSAP/LMAC processes the bursts and schedules them for transmission at the specified time slot.

Q. What is the “Antenna Selector” bit in TCT and RBCT for?

A. The “antenna selector” bit is for future use and has no function in MB87M3400 SoC Rev1 with PSAP/LMAC component Id EC55AA01 and EC55AA02.

Q. How should the subchannel index field in TCT or RBCT be set when no subchannels are used?

A. When no subchannels are used, set the subchannel index field in TCT or RBCT to 0 for BPSK bursts. For all other bursts, set this field to 16 (10000b).

Q. Which is generated by PSAP/LMAC first, the received data or the RSI?

A. The RSI is generated after the data have been placed in the data buffer.

Q. How can the received data and the RSI be linked?

A. The RSI and the data can be linked through the RSI fields burst start index, number of MPDUs, etc.

Q. Does PSAP/LMAC parse the DL_MAP and UL_MAP messages from the BS?

A. PSAP/LMAC parses and processes the DL_MAP message per IEEE802.16-2004. As a result, the OFDM PHY is

MB87M3400


reprogrammed to acquire subsequent downlink bursts. DL_MAP message is also passed to UMAC for possible further processing. PSAP/LMAC never processes the UL_MAP message. It is UMAC’s responsibility to parse and process the UL_MAP message.

Q. What are the main differences between a BS version of PSAP/LMAC firmware and an SS version?

A. The biggest difference is the lack of SCAN mode in the BS version. SCAN mode is one of the three operational modes in the SS version of PSAP/LMAC firmware, and it is used to scan and synchronize to a BS signal.

Q. How does the SCAN mode work?

A. The SCAN mode exists only for the SS version of PSAP/LMAC firmware; it is for initial searching and synchronization to a BS signal. The PSAP/LMAC is put in the SCAN mode by the UMAC using the SET_MODE message. Before starting the SCAN mode, the UMAC should initialize CP length and frame length. In SCAN mode, an attempt to locate and synchronize with a service is made. During the SCAN mode, PSAP continuously sends status indicators and data to the SS-UMAC to assist the initial tuning and network entry process by the SS-UMAC. Once these have been completed, the PSAP/LMAC has to be switched to the RUN mode by the SS-UMAC. This not only terminates the SCAN mode but also starts the RUN mode, where full data traffic is delivered by PSAP in both directions. Note that SCAN mode is not available in the BS version of PSAP/LMAC firmware.

Q. Is the SS-UMAC allowed to transmit in SCAN mode?

A. No, SS-UMAC can not transmit but can only receive during the SCAN mode.

Q. What are the typical (recommended) values for OFDM PHY registers in BS and SS?

A. “MB87M3400 The Fujitsu WiMAX 802.16-2004 SoC PSAP/LMAC Interface Specification for UMAC Developers” provides the default values used by the PSAP/LMAC firmware along with a list of available OFDM registers that need to be changed by the BS or SS-UMAC.

Q. Does the SS-UMAC have to initialize CP length and frame length before entering the SCAN mode?

A. If the CP length is known, SS-UMAC should be initialized by the SET_CPLEN message before entering the SCAN mode to speed

up the SCAN process. Otherwise, the PSAP/LMAC will determine the correct CP length.

The frame length need not be initialized before the SCAN mode. However, it must be initialized sometime before switching to RUN mode. If frame length is known, it is suggested that SS-UMAC initialize it even before entering the SCAN mode. Otherwise, SS-UMAC must deduce the frame length from the information provided by the PSAP/LMAC during the SCAN mode and initialize it using a SET_FRLEN message before entering the RUN mode.

Q. How can the SCAN mode assist RF tuning on SS?

A. If nothing is received in a long time or errors are continuously reported by the PSAP/LMAC, this may indicate that certain RF parameters may be off. SS-UMAC can then attempt to make adjustments, if possible, on the radio. This is a system specific feature and this type of tuning may not be applicable on all systems.

Q. How long will the typical SCAN mode last?

A. The length of SCAN mode depends on various factors. If, for example, a BS is not within the receiving range, the SCAN mode will never terminate. Typically, it takes a very short time, in the order of a few seconds depending in SS-UMAC implementation. Note that if there is something wrong it can take longer.

Q. Will the PSAP/LMAC try different frame lengths in the SCAN mode?

A. PSAP/LMAC will not try different frame lengths during the SCAN mode. It will either use the frame length set by the SS-UMAC before entering the SCAN mode, or if this was not set, it will use the default frame length as given in “MB87M3400 The Fujitsu WiMAX 802.16-2004 SoC PSAP/LMAC Interface Specification for UMAC Developers”. Although PSAP/LMAC can determine the CP length, it cannot determine the frame length on its own. If the frame length is not known , the SS-UMAC will have to determine it during the SCAN mode and initialize it by a SET_FRLEN message before switching to RUN mode.

Q. Will PSAP/LMAC pass FCH contents to SS-UMAC?

A. Yes. FCH contents are passed to SS-UMAC. The RSI for the FCH burst will indicate in the burst type field as “FCH”. This feature can be turned off by a SET_CONFIG message.



Q. Can the SS transmit uplink data before it synchronizes to the BS successfully?

A. As a rule, you must complete the SCAN mode successfully and move to RUN mode before sending any uplink traffic. Completing the SCAN mode means getting consistent “search pass” RSIs with no errors. Only then can you move to RUN mode and send initial ranging in the uplink contention slot to enter the network.

Q. Does the CID filtering on SS filter out such special CIDs as broadcast, ranging, padding, etc.?

A. The special CIDs such as broadcast and initial ranging are never filtered out by the CID filtering on SS.

Q. What is the function of the CID table on a BS?

A. On a BS there is no CID filtering. However, BS still needs to maintain a CID table in order to associate the CIDs with TEKs.

Q. How can the CID table search be made faster on BS?

A. Since a BS may have to maintain a larger number of CIDs compared to an SS, the size of the CID table is typically larger on a BS than that on an SS. Therefore, the CID search may take a long time, affecting the system performance. To prevent this, BS-UMAC can tell PSAP/LMAC where to start the CID search for each SS. In order for this method to work efficiently, BS-UMAC should group CIDs based on SSs for which they are allocated, such that all the CIDs allocated for a particular SS reside contiguously as a group in the CID table. In this case, BS-UMAC could provide the starting index in the CID table of the CID group allocated for the particular SS at the time of generating an RBCT. As a result, PSAP/LMAC would start its CID table search directly from the index given, reducing the search time.

Here is an example:

• BS places all the CIDs allocated for SS #5 into its CID table starting from the table index 40 and on.

• When expecting a burst from SS #5, BS-UMAC generates an RBCT to PSAP/LMAC with CID Table starting index field set to 40.

• Upon burst acquisition, PSAP/LMAC starts the CID table search from table index 40, rather than table index 0. This drastically reduces search time.

Q. What is the maximum number of connections?

A. According to IEEE802.16-2004, a CID (connection ID) is a 16-bit number. Therefore the number of unique CIDs available is 65536. However, the CID filter on PSAP/LMAC allows for a maximum of 1024 CIDs. Typically, an SS will have a much smaller number of CIDs than that. If CID filtering is enabled on an SS, it is recommended that the number of CIDs on an SS should not exceed 16 for performance purposes. On a BS, there is no CID filtering and the CID table is used only to associate TEKs with CIDs. Having 1024 CIDs will allow for up to 1024 encrypted connections on a BS on uplink. The number of CIDs supported is purely a software feature and may be changed in future revisions of PSAP/LMAC firmware.

Q. How does UMAC delete an entry in the CID table?

A. UMAC should write 0 onto the entry to be deleted. The best approach would be to renew/update the whole CID table from time to time.

Q. How does PSAP/LMAC know the number of CID entries in the CID table?

A. UMAC should use SET_CIDN message to inform PSAP/LMAC of the number of CIDs in the CID table.

Q. What is the maximum number of TEKs (Traffic Encryption Keys)?

A. PSAP/LMAC supports 256 TEKs. This allows for 256 simultaneous encrypted connections, without any encryption key sharing.

Q. Should UMAC initialize CID and TEK Tables?

A. UMAC does not need to initialize CID Table and TEK Table. These are initialized (zeroed-out) by PSAP/LMAC at power-up. UMAC only needs to insert/delete elements to these tables.

Q. How will the BS receive bursts from SSs in different uplink slots?

A. BS-UMAC must program PSAP/LMAC with an appropriate RBCT for each uplink slot in which it plans to hear from an SS. Note that the BS determines the uplink slot in which a particular SS is supposed to transmit. Then, the BS informs the SS in advance about this allocation, so that the scheduled transmission from the SS can commence right at the expected time.

Q. Who is responsible for calculating RSSI and CINR?

A. UMAC is responsible for calculating and storing RSSI, CINR and other statistical data based on the input provided by PSAP/LMAC.

MB87M3400


Q. Will MAC_RX_BUFFER ever contain an erroneous MAC PDU?

A. All MAC PDUs with CRC and/or HCS errors will be filtered out by the PSAP/LMAC and will never be placed in MAC_RX_BUFFER.

Q. Why does PSAP/LMAC maintain two DIUC tables?

A. PSAP/LMAC maintains two DIUC tables (main and alternate) to map DIUCs to the OFDM PHY control settings. The main DIUC table is continuously used until PSAP/LMAC detects a change in the configuration count in the DL_MAP message. When this change is detected, PSAP/LMAC copies contents of the alternate DIUC table onto the main DIUC table and continues using the main DIUC table. That means, the SS-UMAC must keep the alternate DIUC table up-to-date, based on DIUC messages it receives from the BS. Normally, there is no need for SS-UMAC to modify the main DIUC table.

Q. How does PSAP/LMAC update the DIUC mapping when a DCD message is received from BS?

A. PSAP/LMAC never updates the DIUC mapping (DIUC table) by itself. It is the UMAC’s responsibility to process DCDs and update the ADT (Alternate DIUC Table) in a timely manner. PSAP/LMAC copies the contents of ADT onto MDT (Main DIUC Table) exactly when DCD count changes to a new value. By this, the new DIUC mapping will always be taken into effect at the right time.

Q. What should be written to the unused entries in the DIUC table?

A. Write 0 into the unused entries in the DIUC table.

Q. In the time offset calculation formula, how is it exactly determined whether to use (cp + 64) or (cp + 64 + 128)?

A. Since SS can not be too far off, the closest point should be used for comparison purposes. For example, if cpLength = 8, cpLength + 64 = 72 and cpLength + 64 + 128 = 200. If we read a value of 195, we could assume that the SS is off by 5 (200 - 195). If we read a value of 76, we could assume that the SS is off by 2 (76 - 74).

Q. Why does the time offset formula sometimes yields a negative time offset value?

A. Depending on the exact spot at which the matched filter has given a positive match, a negative number can sometimes come out when the time offset formula is applied. When this happens, simply add 64 to the negative result.

Q. On BS, is the AGC circuit still operational?

A. Typically AGC is set to a fixed value on a BS. This can be done by writing a constant value to OFDM PHY register RCR5, bit field 22 downto 15 by a SET_REG message sent to PSAP/LMAC firmware. In this case, bit 23 should also be set to 1 to override the internal AGC. The constant value is used in calculating RSSI.

Q. How does the PSAP/LMAC assist initial ranging?

A. PSAP/LMAC assists the initial ranging by reporting burst-related power and timing values in the associated RSI.

Q. Right after the start-up, does UMAC have to initialize all the IPs and OPs for data and control interface between UMAC and LMAC?

A. PSAP/LMAC initializes all IPs and OPs.

Q. How does UMAC get extended burst status information?

A. PSAP/LMAC provides in the RSI, a copy of OFDM burst status registers retrieved particularly for that burst. These are labeled as RSI fields RSR0 through RSR9. The UMAC can get extended burst information from these RSI fields. UMAC must never directly read OFDM PHY machine registers (for example, using GET_REG message) to obtain burst status.

Q. Does the length indicated in RSI include the padding part?

A. No. It does not include the padding part.

Q. Do the OP and IP of the RX_STAT_BUFFER always point to an RSI boundary?

A. Yes. These pointers as well as all other IPs and OPs always point to element boundaries in their respective buffers. For example, RX_STAT_BUFFER IP and OP always point to an RSI boundary, that is they point to the start of an RBCT (assuming that RSIP generation is turned off), and RX_CTRL_BUFFER IP and OP always point to the start of an RBCT.

Q. Does channel estimation apply only for preamble or both preamble and data?.

A. The channel estimate is generated on the preamble and applied to the received data symbols. The channel estimate remains in effect for the received burst until another preamble or midamble symbol is received.



Q. What happens if a message was not read by the receiver in a timely manner?

A. Any new messages will be discarded by the transmitter until the existing message is read by the receiver. Dropped Message Counter will be incremented by the transmitter.

Q. Who will unlock the UMAC mailbox after the message in the mailbox has been read by UMAC?

A. After UMAC reads the message from its own mailbox, it should unlock the mailbox. PSAP/LMAC does not unlock UMAC’s mailbox. It is the UMAC’s responsibility to retrieve the message and then unlock its own mailbox.

Q. What is a PSAP/LMAC Exception?

A. When an exception occurs PSAP sends an EXC message to UMAC. Depending on the nature of the exception, PSAP/LMAC may generate more exceptions messages of the same type. UMAC must clear the conditions causing the exception. In most cases, this is enough to have PSAP/LMAC continue its operation. PSAP/LMAC will then attempt to resume from the next MAC PDU, burst or frame boundary.

Q. When the buffer overflows, what will be the information in RSI?

A. There will be an exception. Partial data flag in RSI may be set but the exception message will signal the overflow.

Q. What are the most common PSAP/LMAC exceptions and can you provide any suggestions for recovery?

A. The exceptions raised by PSAP/LMAC are TX Data Underrun, RX Data Overrun, RX Stat Overrun, and RSIP Overrun.

The TX Data Underrun exception occurs when there is no data to be transmitted in the MAC_TX_BUFFER even though the current TCT indicates that more data must be transmitted and a transmit opportunity is imminent. For a graceful recovery, UMAC could repeat the burst in question once again in future frames, paying attention not to starve the MAC_TX_BUFFER.

The Rx Data Overrun exception occurs when there is not enough free space in MAC_RX_DATA for newly received data. UMAC must promptly drain the buffer and update the OP of MAC_RX_BUFFER for PSAP/LMAC to attempt to continue normally from the next burst or frame boundary. Otherwise, the exception will be reported again.

The RX STAT Overrun exception occurs when there is not enough free space in RX_STAT_BUFFER for new RSI to be stored. UMAC must promptly drain this buffer and update the OP for PSAP/LMAC to attempt to resume.

The RSIP Overrun exception occurs either when there is not enough free space in RX_STAT_BUFFER for new RSIP to be stored or when the number of RSIPs in the current burst has reached the predefined limit (400 RSIPs). RX_STAT_BUFFER allows a maximum of 400 RSIPs and the RSIP generation feature is turned off after the 400th RSIP, at the same time as the RSIP Overrun exception is issued. UMAC must turn on this feature again, if desired, using the SET_CONFIG message. In essence, if the RSIP generation feature is desired, UMAC should pay attention that a burst will not have more than 400 MAC PDUs or this exception will occur and the feature will automatically be turned off. Additionally, similar measures as in the case of RX_STAT_Overrun should also be taken by UMAC to properly drain RX_STAT_BUFFER when this exception occurs.

Q. How does PSAP/MAC determine the UMAC configuration (internal UMAC or external UMAC)?

A. The ARC_GPIO3 pin is used by PSAP/LMAC to determine the UMAC mode. This pin is sampled only once during the IDLE mode initialization. If PSAP finds out that the pin is active as shown in “MB87M3400 The Fujitsu WiMAX 802.16-2004 SoC PSAP/LMAC Interface Specification for UMAC Developers,” it will run in external UMAC mode. Otherwise, it will run in internal UMAC mode. This is a board-level configuration and sampled only at the start-up. Thus, changing the pin polarity afterwards will not be detected by the PSAP/LMAC. This pin can be externally shorted to the CMODE pin, which enables or disables the internal ARM processor. Refer to “MB87M3400 The Fujitsu WiMAX 802.16-2004 SoC Datasheet” for more information on the CMODE pin.

Q. Do “External UMAC” and “Internal UMAC” always mean “BS” and “SS”, recpectively?

A. No. “Internal UMAC” and “External UMAC” only denote the processor configuration on which the UMAC runs. There is no reason why an SS-UMAC cannot run on an external processor. Therefore, there is no direct relation of being internal or external with being BS or SS versions.

MB87M3400


Q. How can the BS and SS versions of PSAP/LMAC be distinguished?

A. Use the GET_COMPID message to identify them.

Q. How can the PSAP/LMAC firmware version and release codes be obtained?

A. Use a GET_FWID message. The first word of the response payload contains version and release codes.

Q. How can the chip hardware revision code be obtained?

A. Use the GET_FWID message. The second word of the response payload contains the SoC hardware revision code.

Q. Can the ARC_GPIOx pins on MB87M3400 be used as general purpose I/O pins?

A. ARC_GPIOx pins are exclusively used by PSAP/LMAC firmware for specific functions, as explained in “MB87M3400 The Fujitsu WiMAX 802.16-2004 SoC PSAP/LMAC Interface Specification for UMAC Developers.” They cannot be used for any other purpose.

Q. Does PSAP/LMAC provide a system log?

A. No. PSAP/LMAC does not provide a system log. It uses the messaging subsystem to communicate important events to UMAC.

Q. What are the ways to alter the OFDM PHY registers?

A. The only way for UMAC to alter the OFDM PHY hardware registers is through SET_REG and GET_REG messages sent to PSAP/LMAC.

Q. What functionality is implemented by PSAP/LMAC as far as data security and privacy is concerned?

A. PSAP/LMAC implements only the low-level support functions, such as DES and AES data encryption/decryption to support data security and privacy. A full implementation of IEEE802.16-2004 security and privacy sublayers is UMAC’s responsibility.

Q. Does PSAP/LMAC provide 3-DES service in addition to the DES service?

A. No. The 3-DES function must be implemented by UMAC.

Q. Why does PSAP/LMAC provide the sums of pilot power and pilot error instead of the ultimate CINR result?

A. PSAP/LMAC has been implemented as a thin firmware and it

does not have the math libraries to implement logarithmic functions to calculate the ultimate CINR result.

Q. The frequency offset data read from the RSI fields show large fluctuations. Is this normal?

A. In order to do any frequency offset measurements or adjustments you need to be using an RF link between the BS and SS. If you are using baseband, you will not be able to estimate the phase offset. The fluctuation you see could be normal depending on the test setup.

Q. What does the notation <x.x> mean, as in <3.12>signed?

A. The notation represents a fixed-point representation of a signed or unsigned number. For example, for <3.12> signed, the top (MSB) bit is the sign bit, the next two bits refer to the whole numbers on the left side of the decimal point, and the remaining 12 bits refer to the bits on the right side of the decimal point.

Q. How is the phi64 value found, if it is given as <1.14> signed number?

A. Let’s assume we got RSI[RSR3]=0x5D8C3A, then phi64 field=0x0c3a or 3130 in decimal. Now to convert this decimal number to its fixed point representation, we would divide it by 2^14 phi64 (decimal) = 3130 / 214 = 0.16104; this is the arctangent of the P64 correlation

Q. What is the actual meaning of frequency offset?

A. An SS is required to synchronize its frequency to the BS by the standard as described in the IEEE 802.16-2004 standard. Frequency offset is used to measure the frequency error in the received signal. This information would then be used by the SS to adjust its clock (by means of an external VCO) to perform automatic frequency adjustment (AFC). Note that the application of the offset to the VCO is not accomplished directly by the PSAP/LMAC. The UMAC processor must use the values reported by PSAP/LMAC (in the fields of RSI) and calculate and apply the correction value to the external VCO.

The frequency offset estimate is generated after reception of a long preamble during initial FCH reception. The frequency offset values are provided by RSR3.phi64 and RSR4.phi128, which are the angles calculated from the cross correlation of the received P64 and P128 preambles. Note that phi64 and phi128 are <1.14> signed fixed-point values and are constrained to ± 0.5. Both values are in units of radians/(2 * pi). Phi64 provides



a coarse angular frequency offset estimate in the range of ± 0.5. The phi128 value gives the residual estimated frequency offset after digital application of the phi64 offset in the frequency tracking loop. The total frequency offset is calculated using the following formula:

Foffset = (phi64/64 + phi128/128) / 214 * Fs (Hz) (after a successful detection of a long preamble!)

The frequency offset is the offset of the channel center frequency. The actual VCO offset will be proportional to the ratio of the channel center frequency to Fs. The above formula to calculate the frequency offset is already given in PSAP I/F Spec Section 3.2.3.1.2.3 on page 20.

It is possible to calculate the “coarse” frequency offset using only phi64 (without phi128). The following formula shows you how to calculate the “coarse” frequency offset from the phi64 register value ONLY.

Foffset = phi64 / 214 / 64 * Fs

So, to calculate the frequency offset from your first number (assuming a 3.5 MHz channel bandwidth (Fs = 8 MHz/2)), it would be: Foffset = (3130/ (214 * 64)) * (8E6/2) = 11.94 KHz

Remember, the phi64 register gives a coarse AFC adjustment and you could also utilize the phi128 register along with the phi64 to calculate a more accurate frequency offset. Then the total frequency offset is calculated (including both phi64 and phi128) as given in the first formula above.

Example:

An example calculation of how much frequency offset MB87M3400 OFDM PHY can discern is shown below for Fs = 8 MHz/2 operating at 3.5 GHz RF center frequency:

Fmax = Fs / 128 = 31.25 kHz (the maximum detectable frequency offset, dictated by the P64 preamble spacing: Fs/128)

Fcenter = 3.5 GHz

Fmax-ppm = 31.25 kHz / 3.5 GHz = 8.93 ppm

In this case, the PHY can discern a ±8 ppm offset in the received signal.

Q. How is the OFDM symbol padding handled?

A. If the data payload cannot fill up an OFDM symbol, the OFDM PHY automatically pads the remaining bytes with FFs. However, if the number of remaining bytes is more than 5, the UMAC must insert a padding MAC PDU with the special padding CID in this area.

MB87M3400


3. 802-16-2004 OFDM PHY Performance3.1 IntroductionThe purpose of this section is to present the performance characteristics of the 802.16-2004 OFDM PHY. Simulation results for bit error rates (BER) in additive white gaussian (AWGN) are shown. Margins for system implementation are shown in a table.

3.2 BER Performance in AWGNThe bit error rate (BER) performance of the WMAN_PHY has been characterized for all the mandatory rates of operation in additive white gaussian noise (AWGN). The simulations have the following characteristics:

• Downlink transmission/reception of 1536-byte packets

• Complete receiver synchronization, AGC and AFC on every packet

• Inclusion of –32 dBc integrated phase noise

• The results from the BER simulations for 20 MHz channel bandwidth are shown in Figure 3:1.

Figure 3:1 BER Plot for AWGN

3.3 System Implemantation MarginThe calculation of the system implementation margin for the WMAN_PHY is shown in Table 3-1: Calculation of System Implementation Margin. The results show that the total system margin is approximately 7 dB when all potential impairments are included.

Table 3-1: Calculation of System Implementation Margin

DescriptionValue (dB)

Comment

SNR for 10-6 BER 24.4Receiver SNR specified for QAM-64 in 802.16 specification

Implementation Loss (IL) 55 dB implementation loss as accounted for in Rss (receiver minimum input level sensitivity) calculation in 802.16 spec

SNR + IL 29.4

Simulation result for QAM-64 at 10-6 BER

21 See BER plot

Margin (SNR + IL - BER simulation result)

8.4System margin before any additional impairments not considered in simulation

Additional impairments not in simulations:

Amplifier and mixer non-linearity

0.1240 dB signal to interference ratio assumed

IQ imbalance 0.7 32 dB negative frequency rejection

ADC clock jitter 0.511% of clock period produces 0.5 dB at 10E-5

ADC spurious noise 0.015Assumed to be ±0.5 bit of ADC at 10 dB backoff

Input filter degradation 0.1Non-optimum sync due to input filter non-linearity

Total Additional Impairments

1.335 Loss from impairments not in simulations

Estimated System Margin = Margin - Additional Impairments

7.065



4. Simulation Results Using SUI5 Channel Models4.1 SNR vs BER simulations of the 802.16d PHYThis section outlines the bit error (BER) performance of the WMAN PHY as the signal to noise ratio (SNR) is varied in simulated SUI channel models.

For each simulation, a 3.5 MHz DL burst that consists of a long preamble and 8 data symbols, comprising a total length of 10 OFDM symbols was used. The amount of data for each modulation type was varied to generate the full 8 data symbol payload.

Using a SUI channel model, the SNR was swept from 0 dB upwards in 1 dB increments until a BER of 10-4 was reached. This simulation was repeated for the best and worst cases of the SUI channel model by manually choosing the best and worst case multipath initial seed between 1 and 100.

The other details used for this simulation are: Channel bandwidth: 3.5 MHzFrequency offset: -313 Hz (-2% sub carrier spacing)Phase noise: -97 dBc/Hz

4.2 SUI-1 Channel Model Simulation ResultsSUI-1 simulation results are shown in the following graphs (Figure 4:1 through Figure 4:8):

Figure 4:1 QAM64-3/4 BER vs SNR Simulation Plot



5. SUI Model – Stanford University Interim Model

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Figure 4:5 QPSK-3/4 BER vs SNR Simulation Plot


Figure 4:7 BPSK-3/4 BER vs SNR Simulation Plot




4.3 SUI-3 Channel Model Simulation ResultsSUI-3 simulation results are shown in the following graphs (Figure 4:9 through Figure 4:16):



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5. Performance Measurements5.1 SiGe Radio Performance TestingThe information provided for SiGe Radio Testing is early and is subject to update when final results are available.

5.1.1 RF Performance Testing5.1.1.1 Relative Constellation ErrorThe IEEE 802.16 – 2004 standard lists the following table of values relating modulation type to acceptable relative constellation error.

Table 5-1: Allowed Relative Constellation Error Versus Data Rate

5.1.1.1.1 BPSK 3/4 RF Testing ResultsUsing simulations of EIB PHY output frames uploaded to a signal generator continuous burst traffic was transmitted over the RF Integrations radio. DL frames of different modulation types were used to characterize the radio with different modulation types. The optimal performance area was determined through trial and error. All of the following tests in Section 5.1 were done using the same power output and Tx attenuation settings.

Result:

The following constellation and error was recorded (see Figure 5:1 and Figure 5:2, respectively).

Figure 5:1 Constellation Diagram of BPSK 3/4

Figure 5:2 Error Data from VSA (BPSK 3/4)

Figure 5:3 CCDF Curve from VSA (BPSK 3/4)

The data were recorded with an input voltage of approximately 145 mVp-p using a common mode voltage of 1.5 V. The Sapphire program was used with the modulator attenuation set at 18 dB and IF attenuation set at 21 dB (all others set to 0). The output power was measured to be –14.7 dBm. After examining the data and averaging the results the average EVM would be very close to –30 dB. The CCDF curve (Figure 5:3) shows a BPSK signal that has a below average peak to average power ratio. This is the result of the very short data burst used and is acceptable.

5.1.1.1.2 QPSK 3/4 RF testing resultsTest setup for this is the same as Section 5.1.1.1.1 with the only change being modulation type.

Results:The following constellation and error was recorded (see Figure 5:4 and Figure 5:5, respectively):

Burst Type Relative Constellation Error (dB)

BPSK 1/2 -13.0

QPSK 1/2 -16.0

QPSK 3/4 -18.5

16-QAM 1/2 -21.5

16-QAM 3/4 -25.0

64-QAM 2/3 -28.5

64-QAM 3/4 -31.0



Figure 5:4 Constellation Diagram of QPSK 3/4

Figure 5:5 Error Data from VSA (QPSK 3/4)

Figure 5:6 CCDF Curve from VSA (QPSK 3/4)

The comment here is much the same as Section 5.1.1.1.1 with all inputs remaining the same. The standard requires RCE of –18.5 dB of error. The main difference here is the CCDF curve (Figure 5:6) which shows a signal that has a higher peak to average power ratio than the BPSK test done but still has a lower then average ratio.

5.1.1.1.3 16-QAM 3/4 RF Testing ResultsTest setup for this is the same as Section 5.1.1.1.1 with the only change being modulation type.

Results:The following constellation and error was recorded (See Figure 5:7 and Figure 5:8, respectively):

Figure 5:7 Constellation Diagram of QAM16 3/4

Figure 5:8 Error Data from VSA (QAM16 3/4)

Figure 5:9 CCDF Curve from VSA (QAM16 3/4)

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The comment here is much the same as in Section 5.1.1.1.3 16-QAM 3/4 RF Testing Results. The standard requires RCE of –25 dB of error. The CCDF curve is shown in Figure 5:9.

5.1.1.1.4 64-QAM 3/4 RF Testing ResultsTest setup for this is the same as Section 5.1.1.1.1 with the only change being modulation type.

Results:The following constellation and error was recorded (See Figure 5:10 and Figure 5:11, respectively):

Figure 5:10 Constellation Diagram of QAM64 3/4

Figure 5:11 Error Data from VSA (QAM64 3/4)

Figure 5:12 CCDF Curve from VSA (QAM64 3/4)

The comment here is much the same as in Section 5.1.1.1.1. The standard requires RCE of –31 dB of error. Receiver Operation. The CCD curve is shown in Figure 5:12.

FUJITSU MICROELECTRONICS AMERICA, INC.Corporate Headquarters1250 East Arques Avenue, M/S 333, Sunnyvale, California 94088-3470Tel: (800) 866-8608 Fax: (408) 737-5999E-mail: [email protected] Web Site: http://www.fma.fujitsu.com

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BMS-DS-21059-5/2005Confidential

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